fetch.hh revision 10331:ed05298e8566
12568SN/A/* 22568SN/A * Copyright (c) 2010-2012, 2014 ARM Limited 32568SN/A * All rights reserved 42568SN/A * 52568SN/A * The license below extends only to copyright in the software and shall 62568SN/A * not be construed as granting a license to any other intellectual 72568SN/A * property including but not limited to intellectual property relating 82568SN/A * to a hardware implementation of the functionality of the software 92568SN/A * licensed hereunder. You may use the software subject to the license 102568SN/A * terms below provided that you ensure that this notice is replicated 112568SN/A * unmodified and in its entirety in all distributions of the software, 122568SN/A * modified or unmodified, in source code or in binary form. 132568SN/A * 142568SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 152568SN/A * All rights reserved. 162568SN/A * 172568SN/A * Redistribution and use in source and binary forms, with or without 182568SN/A * modification, are permitted provided that the following conditions are 192568SN/A * met: redistributions of source code must retain the above copyright 202568SN/A * notice, this list of conditions and the following disclaimer; 212568SN/A * redistributions in binary form must reproduce the above copyright 222568SN/A * notice, this list of conditions and the following disclaimer in the 232568SN/A * documentation and/or other materials provided with the distribution; 242568SN/A * neither the name of the copyright holders nor the names of its 252568SN/A * contributors may be used to endorse or promote products derived from 262568SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302568SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312568SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322568SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332982Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342982Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352568SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362568SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372568SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382568SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392568SN/A * 402568SN/A * Authors: Kevin Lim 412568SN/A * Korey Sewell 422568SN/A */ 432568SN/A 442568SN/A#ifndef __CPU_O3_FETCH_HH__ 452568SN/A#define __CPU_O3_FETCH_HH__ 462568SN/A 472568SN/A#include "arch/decoder.hh" 482568SN/A#include "arch/utility.hh" 492568SN/A#include "base/statistics.hh" 502568SN/A#include "config/the_isa.hh" 512568SN/A#include "cpu/pc_event.hh" 522568SN/A#include "cpu/pred/bpred_unit.hh" 532982Sstever@eecs.umich.edu#include "cpu/timebuf.hh" 542568SN/A#include "cpu/translation.hh" 552568SN/A#include "mem/packet.hh" 562568SN/A#include "mem/port.hh" 572643Sstever@eecs.umich.edu#include "sim/eventq.hh" 582568SN/A#include "sim/probe/probe.hh" 592568SN/A 602643Sstever@eecs.umich.edustruct DerivO3CPUParams; 612643Sstever@eecs.umich.edu 622643Sstever@eecs.umich.edu/** 632643Sstever@eecs.umich.edu * DefaultFetch class handles both single threaded and SMT fetch. Its 642643Sstever@eecs.umich.edu * width is specified by the parameters; each cycle it tries to fetch 652643Sstever@eecs.umich.edu * that many instructions. It supports using a branch predictor to 662643Sstever@eecs.umich.edu * predict direction and targets. 672643Sstever@eecs.umich.edu * It supports the idling functionality of the CPU by indicating to 682643Sstever@eecs.umich.edu * the CPU when it is active and inactive. 694435Ssaidi@eecs.umich.edu */ 704435Ssaidi@eecs.umich.edutemplate <class Impl> 714435Ssaidi@eecs.umich.educlass DefaultFetch 724432Ssaidi@eecs.umich.edu{ 734432Ssaidi@eecs.umich.edu public: 742643Sstever@eecs.umich.edu /** Typedefs from Impl. */ 752643Sstever@eecs.umich.edu typedef typename Impl::CPUPol CPUPol; 762643Sstever@eecs.umich.edu typedef typename Impl::DynInst DynInst; 772643Sstever@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 783349Sbinkertn@umich.edu typedef typename Impl::O3CPU O3CPU; 792643Sstever@eecs.umich.edu 802643Sstever@eecs.umich.edu /** Typedefs from the CPU policy. */ 812643Sstever@eecs.umich.edu typedef typename CPUPol::FetchStruct FetchStruct; 822643Sstever@eecs.umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 834432Ssaidi@eecs.umich.edu 844432Ssaidi@eecs.umich.edu /** Typedefs from ISA. */ 854433Ssaidi@eecs.umich.edu typedef TheISA::MachInst MachInst; 864432Ssaidi@eecs.umich.edu typedef TheISA::ExtMachInst ExtMachInst; 874433Ssaidi@eecs.umich.edu 882643Sstever@eecs.umich.edu class FetchTranslation : public BaseTLB::Translation 892643Sstever@eecs.umich.edu { 904433Ssaidi@eecs.umich.edu protected: 914433Ssaidi@eecs.umich.edu DefaultFetch<Impl> *fetch; 924433Ssaidi@eecs.umich.edu 932643Sstever@eecs.umich.edu public: 944433Ssaidi@eecs.umich.edu FetchTranslation(DefaultFetch<Impl> *_fetch) 952657Ssaidi@eecs.umich.edu : fetch(_fetch) 962643Sstever@eecs.umich.edu {} 972643Sstever@eecs.umich.edu 983349Sbinkertn@umich.edu void 992643Sstever@eecs.umich.edu markDelayed() 1002643Sstever@eecs.umich.edu {} 1012643Sstever@eecs.umich.edu 1022643Sstever@eecs.umich.edu void 1034432Ssaidi@eecs.umich.edu finish(Fault fault, RequestPtr req, ThreadContext *tc, 1044432Ssaidi@eecs.umich.edu BaseTLB::Mode mode) 1052643Sstever@eecs.umich.edu { 1064432Ssaidi@eecs.umich.edu assert(mode == BaseTLB::Execute); 1074432Ssaidi@eecs.umich.edu fetch->finishTranslation(fault, req); 1084432Ssaidi@eecs.umich.edu delete this; 1094432Ssaidi@eecs.umich.edu } 1104432Ssaidi@eecs.umich.edu }; 1114432Ssaidi@eecs.umich.edu 1124432Ssaidi@eecs.umich.edu private: 1134432Ssaidi@eecs.umich.edu /* Event to delay delivery of a fetch translation result in case of 1144432Ssaidi@eecs.umich.edu * a fault and the nop to carry the fault cannot be generated 1154432Ssaidi@eecs.umich.edu * immediately */ 1164432Ssaidi@eecs.umich.edu class FinishTranslationEvent : public Event 1174432Ssaidi@eecs.umich.edu { 1184432Ssaidi@eecs.umich.edu private: 1194432Ssaidi@eecs.umich.edu DefaultFetch<Impl> *fetch; 1204432Ssaidi@eecs.umich.edu Fault fault; 1214432Ssaidi@eecs.umich.edu RequestPtr req; 1224432Ssaidi@eecs.umich.edu 1234432Ssaidi@eecs.umich.edu public: 1244432Ssaidi@eecs.umich.edu FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 1254432Ssaidi@eecs.umich.edu : fetch(_fetch) 1264432Ssaidi@eecs.umich.edu {} 1274432Ssaidi@eecs.umich.edu 1284432Ssaidi@eecs.umich.edu void setFault(Fault _fault) 1294432Ssaidi@eecs.umich.edu { 1304432Ssaidi@eecs.umich.edu fault = _fault; 1314432Ssaidi@eecs.umich.edu } 1324432Ssaidi@eecs.umich.edu 1334432Ssaidi@eecs.umich.edu void setReq(RequestPtr _req) 1344432Ssaidi@eecs.umich.edu { 1354432Ssaidi@eecs.umich.edu req = _req; 1364432Ssaidi@eecs.umich.edu } 1374432Ssaidi@eecs.umich.edu 1384432Ssaidi@eecs.umich.edu /** Process the delayed finish translation */ 1394432Ssaidi@eecs.umich.edu void process() 1404432Ssaidi@eecs.umich.edu { 1414432Ssaidi@eecs.umich.edu assert(fetch->numInst < fetch->fetchWidth); 1424432Ssaidi@eecs.umich.edu fetch->finishTranslation(fault, req); 1432643Sstever@eecs.umich.edu } 1442643Sstever@eecs.umich.edu 1452643Sstever@eecs.umich.edu const char *description() const 1462643Sstever@eecs.umich.edu { 1472643Sstever@eecs.umich.edu return "FullO3CPU FetchFinishTranslation"; 1482643Sstever@eecs.umich.edu } 1492643Sstever@eecs.umich.edu }; 1502643Sstever@eecs.umich.edu 1512643Sstever@eecs.umich.edu public: 1522643Sstever@eecs.umich.edu /** Overall fetch status. Used to determine if the CPU can 1534433Ssaidi@eecs.umich.edu * deschedule itsef due to a lack of activity. 1542643Sstever@eecs.umich.edu */ 1554435Ssaidi@eecs.umich.edu enum FetchStatus { 1564435Ssaidi@eecs.umich.edu Active, 1574435Ssaidi@eecs.umich.edu Inactive 1582643Sstever@eecs.umich.edu }; 1594435Ssaidi@eecs.umich.edu 1604435Ssaidi@eecs.umich.edu /** Individual thread status. */ 1614435Ssaidi@eecs.umich.edu enum ThreadStatus { 1624435Ssaidi@eecs.umich.edu Running, 1632643Sstever@eecs.umich.edu Idle, 1642643Sstever@eecs.umich.edu Squashing, 1652643Sstever@eecs.umich.edu Blocked, 1662643Sstever@eecs.umich.edu Fetching, 1674435Ssaidi@eecs.umich.edu TrapPending, 1684435Ssaidi@eecs.umich.edu QuiescePending, 1692643Sstever@eecs.umich.edu ItlbWait, 1704433Ssaidi@eecs.umich.edu IcacheWaitResponse, 1712643Sstever@eecs.umich.edu IcacheWaitRetry, 1722643Sstever@eecs.umich.edu IcacheAccessComplete, 1732643Sstever@eecs.umich.edu NoGoodAddr 1744433Ssaidi@eecs.umich.edu }; 1754433Ssaidi@eecs.umich.edu 1762643Sstever@eecs.umich.edu /** Fetching Policy, Add new policies here.*/ 1772643Sstever@eecs.umich.edu enum FetchPriority { 1782643Sstever@eecs.umich.edu SingleThread, 1792643Sstever@eecs.umich.edu RoundRobin, 1802643Sstever@eecs.umich.edu Branch, 1812643Sstever@eecs.umich.edu IQ, 1822643Sstever@eecs.umich.edu LSQ 1832643Sstever@eecs.umich.edu }; 1842643Sstever@eecs.umich.edu 1852643Sstever@eecs.umich.edu private: 1862643Sstever@eecs.umich.edu /** Fetch status. */ 1872643Sstever@eecs.umich.edu FetchStatus _status; 1882643Sstever@eecs.umich.edu 1892643Sstever@eecs.umich.edu /** Per-thread status. */ 1902643Sstever@eecs.umich.edu ThreadStatus fetchStatus[Impl::MaxThreads]; 1912643Sstever@eecs.umich.edu 1922643Sstever@eecs.umich.edu /** Fetch policy. */ 1932643Sstever@eecs.umich.edu FetchPriority fetchPolicy; 1942643Sstever@eecs.umich.edu 1952643Sstever@eecs.umich.edu /** List that has the threads organized by priority. */ 1962643Sstever@eecs.umich.edu std::list<ThreadID> priorityList; 1972568SN/A 1982568SN/A /** Probe points. */ 1992568SN/A ProbePointArg<DynInstPtr> *ppFetch; 2004435Ssaidi@eecs.umich.edu 2014435Ssaidi@eecs.umich.edu public: 2024435Ssaidi@eecs.umich.edu /** DefaultFetch constructor. */ 2032568SN/A DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2042568SN/A 2052568SN/A /** Returns the name of fetch. */ 2062643Sstever@eecs.umich.edu std::string name() const; 2072643Sstever@eecs.umich.edu 2083349Sbinkertn@umich.edu /** Registers statistics. */ 2092568SN/A void regStats(); 2102643Sstever@eecs.umich.edu 2112568SN/A /** Registers probes. */ 2122657Ssaidi@eecs.umich.edu void regProbePoints(); 2132568SN/A 2142643Sstever@eecs.umich.edu /** Sets the main backwards communication time buffer pointer. */ 2152568SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2163349Sbinkertn@umich.edu 2172568SN/A /** Sets pointer to list of active threads. */ 2182643Sstever@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 2192568SN/A 2203349Sbinkertn@umich.edu /** Sets pointer to time buffer used to communicate to the next stage. */ 2212568SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2222643Sstever@eecs.umich.edu 2232568SN/A /** Initialize stage. */ 2242643Sstever@eecs.umich.edu void startupStage(); 2252568SN/A 2262643Sstever@eecs.umich.edu /** Handles retrying the fetch access. */ 2272568SN/A void recvRetry(); 2282643Sstever@eecs.umich.edu 2292643Sstever@eecs.umich.edu /** Processes cache completion event. */ 2302568SN/A void processCacheCompletion(PacketPtr pkt); 2312568SN/A 2322643Sstever@eecs.umich.edu /** Resume after a drain. */ 2332568SN/A void drainResume(); 2342568SN/A 2352568SN/A /** Perform sanity checks after a drain. */ 2362568SN/A void drainSanityCheck() const; 2372568SN/A 2384435Ssaidi@eecs.umich.edu /** Has the stage drained? */ 2394435Ssaidi@eecs.umich.edu bool isDrained() const; 2404435Ssaidi@eecs.umich.edu 2414435Ssaidi@eecs.umich.edu /** Takes over from another CPU's thread. */ 2424435Ssaidi@eecs.umich.edu void takeOverFrom(); 2434435Ssaidi@eecs.umich.edu 2444435Ssaidi@eecs.umich.edu /** 2454435Ssaidi@eecs.umich.edu * Stall the fetch stage after reaching a safe drain point. 2464435Ssaidi@eecs.umich.edu * 2474435Ssaidi@eecs.umich.edu * The CPU uses this method to stop fetching instructions from a 2484435Ssaidi@eecs.umich.edu * thread that has been drained. The drain stall is different from 2494435Ssaidi@eecs.umich.edu * all other stalls in that it is signaled instantly from the 2504435Ssaidi@eecs.umich.edu * commit stage (without the normal communication delay) when it 2514435Ssaidi@eecs.umich.edu * has reached a safe point to drain from. 2524435Ssaidi@eecs.umich.edu */ 2534435Ssaidi@eecs.umich.edu void drainStall(ThreadID tid); 2544435Ssaidi@eecs.umich.edu 2554435Ssaidi@eecs.umich.edu /** Tells fetch to wake up from a quiesce instruction. */ 2564435Ssaidi@eecs.umich.edu void wakeFromQuiesce(); 2572568SN/A 2582568SN/A /** For priority-based fetch policies, need to keep update priorityList */ 2592738Sstever@eecs.umich.edu void deactivateThread(ThreadID tid); 2602568SN/A private: 2612568SN/A /** Reset this pipeline stage */ 2622568SN/A void resetStage(); 2634435Ssaidi@eecs.umich.edu 2642568SN/A /** Changes the status of this stage to active, and indicates this 2652568SN/A * to the CPU. 2662568SN/A */ 267 inline void switchToActive(); 268 269 /** Changes the status of this stage to inactive, and indicates 270 * this to the CPU. 271 */ 272 inline void switchToInactive(); 273 274 /** 275 * Looks up in the branch predictor to see if the next PC should be 276 * either next PC+=MachInst or a branch target. 277 * @param next_PC Next PC variable passed in by reference. It is 278 * expected to be set to the current PC; it will be updated with what 279 * the next PC will be. 280 * @param next_NPC Used for ISAs which use delay slots. 281 * @return Whether or not a branch was predicted as taken. 282 */ 283 bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 284 285 /** 286 * Fetches the cache line that contains the fetch PC. Returns any 287 * fault that happened. Puts the data into the class variable 288 * fetchBuffer, which may not hold the entire fetched cache line. 289 * @param vaddr The memory address that is being fetched from. 290 * @param ret_fault The fault reference that will be set to the result of 291 * the icache access. 292 * @param tid Thread id. 293 * @param pc The actual PC of the current instruction. 294 * @return Any fault that occured. 295 */ 296 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 297 void finishTranslation(Fault fault, RequestPtr mem_req); 298 299 300 /** Check if an interrupt is pending and that we need to handle 301 */ 302 bool 303 checkInterrupt(Addr pc) 304 { 305 return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 306 } 307 308 /** Squashes a specific thread and resets the PC. */ 309 inline void doSquash(const TheISA::PCState &newPC, 310 const DynInstPtr squashInst, ThreadID tid); 311 312 /** Squashes a specific thread and resets the PC. Also tells the CPU to 313 * remove any instructions between fetch and decode that should be sqaushed. 314 */ 315 void squashFromDecode(const TheISA::PCState &newPC, 316 const DynInstPtr squashInst, 317 const InstSeqNum seq_num, ThreadID tid); 318 319 /** Checks if a thread is stalled. */ 320 bool checkStall(ThreadID tid) const; 321 322 /** Updates overall fetch stage status; to be called at the end of each 323 * cycle. */ 324 FetchStatus updateFetchStatus(); 325 326 public: 327 /** Squashes a specific thread and resets the PC. Also tells the CPU to 328 * remove any instructions that are not in the ROB. The source of this 329 * squash should be the commit stage. 330 */ 331 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 332 DynInstPtr squashInst, ThreadID tid); 333 334 /** Ticks the fetch stage, processing all inputs signals and fetching 335 * as many instructions as possible. 336 */ 337 void tick(); 338 339 /** Checks all input signals and updates the status as necessary. 340 * @return: Returns if the status has changed due to input signals. 341 */ 342 bool checkSignalsAndUpdate(ThreadID tid); 343 344 /** Does the actual fetching of instructions and passing them on to the 345 * next stage. 346 * @param status_change fetch() sets this variable if there was a status 347 * change (ie switching to IcacheMissStall). 348 */ 349 void fetch(bool &status_change); 350 351 /** Align a PC to the start of a fetch buffer block. */ 352 Addr fetchBufferAlignPC(Addr addr) 353 { 354 return (addr & ~(fetchBufferMask)); 355 } 356 357 /** The decoder. */ 358 TheISA::Decoder *decoder[Impl::MaxThreads]; 359 360 private: 361 DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 362 StaticInstPtr curMacroop, TheISA::PCState thisPC, 363 TheISA::PCState nextPC, bool trace); 364 365 /** Returns the appropriate thread to fetch, given the fetch policy. */ 366 ThreadID getFetchingThread(FetchPriority &fetch_priority); 367 368 /** Returns the appropriate thread to fetch using a round robin policy. */ 369 ThreadID roundRobin(); 370 371 /** Returns the appropriate thread to fetch using the IQ count policy. */ 372 ThreadID iqCount(); 373 374 /** Returns the appropriate thread to fetch using the LSQ count policy. */ 375 ThreadID lsqCount(); 376 377 /** Returns the appropriate thread to fetch using the branch count 378 * policy. */ 379 ThreadID branchCount(); 380 381 /** Pipeline the next I-cache access to the current one. */ 382 void pipelineIcacheAccesses(ThreadID tid); 383 384 /** Profile the reasons of fetch stall. */ 385 void profileStall(ThreadID tid); 386 387 private: 388 /** Pointer to the O3CPU. */ 389 O3CPU *cpu; 390 391 /** Time buffer interface. */ 392 TimeBuffer<TimeStruct> *timeBuffer; 393 394 /** Wire to get decode's information from backwards time buffer. */ 395 typename TimeBuffer<TimeStruct>::wire fromDecode; 396 397 /** Wire to get rename's information from backwards time buffer. */ 398 typename TimeBuffer<TimeStruct>::wire fromRename; 399 400 /** Wire to get iew's information from backwards time buffer. */ 401 typename TimeBuffer<TimeStruct>::wire fromIEW; 402 403 /** Wire to get commit's information from backwards time buffer. */ 404 typename TimeBuffer<TimeStruct>::wire fromCommit; 405 406 //Might be annoying how this name is different than the queue. 407 /** Wire used to write any information heading to decode. */ 408 typename TimeBuffer<FetchStruct>::wire toDecode; 409 410 /** BPredUnit. */ 411 BPredUnit *branchPred; 412 413 TheISA::PCState pc[Impl::MaxThreads]; 414 415 Addr fetchOffset[Impl::MaxThreads]; 416 417 StaticInstPtr macroop[Impl::MaxThreads]; 418 419 /** Can the fetch stage redirect from an interrupt on this instruction? */ 420 bool delayedCommit[Impl::MaxThreads]; 421 422 /** Memory request used to access cache. */ 423 RequestPtr memReq[Impl::MaxThreads]; 424 425 /** Variable that tracks if fetch has written to the time buffer this 426 * cycle. Used to tell CPU if there is activity this cycle. 427 */ 428 bool wroteToTimeBuffer; 429 430 /** Tracks how many instructions has been fetched this cycle. */ 431 int numInst; 432 433 /** Source of possible stalls. */ 434 struct Stalls { 435 bool decode; 436 bool drain; 437 }; 438 439 /** Tracks which stages are telling fetch to stall. */ 440 Stalls stalls[Impl::MaxThreads]; 441 442 /** Decode to fetch delay. */ 443 Cycles decodeToFetchDelay; 444 445 /** Rename to fetch delay. */ 446 Cycles renameToFetchDelay; 447 448 /** IEW to fetch delay. */ 449 Cycles iewToFetchDelay; 450 451 /** Commit to fetch delay. */ 452 Cycles commitToFetchDelay; 453 454 /** The width of fetch in instructions. */ 455 unsigned fetchWidth; 456 457 /** The width of decode in instructions. */ 458 unsigned decodeWidth; 459 460 /** Is the cache blocked? If so no threads can access it. */ 461 bool cacheBlocked; 462 463 /** The packet that is waiting to be retried. */ 464 PacketPtr retryPkt; 465 466 /** The thread that is waiting on the cache to tell fetch to retry. */ 467 ThreadID retryTid; 468 469 /** Cache block size. */ 470 unsigned int cacheBlkSize; 471 472 /** The size of the fetch buffer in bytes. The fetch buffer 473 * itself may be smaller than a cache line. 474 */ 475 unsigned fetchBufferSize; 476 477 /** Mask to align a fetch address to a fetch buffer boundary. */ 478 Addr fetchBufferMask; 479 480 /** The fetch data that is being fetched and buffered. */ 481 uint8_t *fetchBuffer[Impl::MaxThreads]; 482 483 /** The PC of the first instruction loaded into the fetch buffer. */ 484 Addr fetchBufferPC[Impl::MaxThreads]; 485 486 /** The size of the fetch queue in micro-ops */ 487 unsigned fetchQueueSize; 488 489 /** Queue of fetched instructions. Per-thread to prevent HoL blocking. */ 490 std::deque<DynInstPtr> fetchQueue[Impl::MaxThreads]; 491 492 /** Whether or not the fetch buffer data is valid. */ 493 bool fetchBufferValid[Impl::MaxThreads]; 494 495 /** Size of instructions. */ 496 int instSize; 497 498 /** Icache stall statistics. */ 499 Counter lastIcacheStall[Impl::MaxThreads]; 500 501 /** List of Active Threads */ 502 std::list<ThreadID> *activeThreads; 503 504 /** Number of threads. */ 505 ThreadID numThreads; 506 507 /** Number of threads that are actively fetching. */ 508 ThreadID numFetchingThreads; 509 510 /** Thread ID being fetched. */ 511 ThreadID threadFetched; 512 513 /** Checks if there is an interrupt pending. If there is, fetch 514 * must stop once it is not fetching PAL instructions. 515 */ 516 bool interruptPending; 517 518 /** Set to true if a pipelined I-cache request should be issued. */ 519 bool issuePipelinedIfetch[Impl::MaxThreads]; 520 521 /** Event used to delay fault generation of translation faults */ 522 FinishTranslationEvent finishTranslationEvent; 523 524 // @todo: Consider making these vectors and tracking on a per thread basis. 525 /** Stat for total number of cycles stalled due to an icache miss. */ 526 Stats::Scalar icacheStallCycles; 527 /** Stat for total number of fetched instructions. */ 528 Stats::Scalar fetchedInsts; 529 /** Total number of fetched branches. */ 530 Stats::Scalar fetchedBranches; 531 /** Stat for total number of predicted branches. */ 532 Stats::Scalar predictedBranches; 533 /** Stat for total number of cycles spent fetching. */ 534 Stats::Scalar fetchCycles; 535 /** Stat for total number of cycles spent squashing. */ 536 Stats::Scalar fetchSquashCycles; 537 /** Stat for total number of cycles spent waiting for translation */ 538 Stats::Scalar fetchTlbCycles; 539 /** Stat for total number of cycles spent blocked due to other stages in 540 * the pipeline. 541 */ 542 Stats::Scalar fetchIdleCycles; 543 /** Total number of cycles spent blocked. */ 544 Stats::Scalar fetchBlockedCycles; 545 /** Total number of cycles spent in any other state. */ 546 Stats::Scalar fetchMiscStallCycles; 547 /** Total number of cycles spent in waiting for drains. */ 548 Stats::Scalar fetchPendingDrainCycles; 549 /** Total number of stall cycles caused by no active threads to run. */ 550 Stats::Scalar fetchNoActiveThreadStallCycles; 551 /** Total number of stall cycles caused by pending traps. */ 552 Stats::Scalar fetchPendingTrapStallCycles; 553 /** Total number of stall cycles caused by pending quiesce instructions. */ 554 Stats::Scalar fetchPendingQuiesceStallCycles; 555 /** Total number of stall cycles caused by I-cache wait retrys. */ 556 Stats::Scalar fetchIcacheWaitRetryStallCycles; 557 /** Stat for total number of fetched cache lines. */ 558 Stats::Scalar fetchedCacheLines; 559 /** Total number of outstanding icache accesses that were dropped 560 * due to a squash. 561 */ 562 Stats::Scalar fetchIcacheSquashes; 563 /** Total number of outstanding tlb accesses that were dropped 564 * due to a squash. 565 */ 566 Stats::Scalar fetchTlbSquashes; 567 /** Distribution of number of instructions fetched each cycle. */ 568 Stats::Distribution fetchNisnDist; 569 /** Rate of how often fetch was idle. */ 570 Stats::Formula idleRate; 571 /** Number of branch fetches per cycle. */ 572 Stats::Formula branchRate; 573 /** Number of instruction fetched per cycle. */ 574 Stats::Formula fetchRate; 575}; 576 577#endif //__CPU_O3_FETCH_HH__ 578