fetch.hh revision 9480
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37849SAli.Saidi@ARM.com * All rights reserved 47849SAli.Saidi@ARM.com * 57849SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67849SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77849SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87849SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97849SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107849SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117849SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127849SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137849SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_FETCH_HH__ 452292SN/A#define __CPU_O3_FETCH_HH__ 461060SN/A 479020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 482669Sktlim@umich.edu#include "arch/utility.hh" 491461SN/A#include "base/statistics.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 511060SN/A#include "cpu/pc_event.hh" 529480Snilay@cs.wisc.edu#include "cpu/pred/bpred_unit.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 547849SAli.Saidi@ARM.com#include "cpu/translation.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 562669Sktlim@umich.edu#include "mem/port.hh" 571461SN/A#include "sim/eventq.hh" 581060SN/A 598737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 605529Snate@binkert.org 611060SN/A/** 622329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 632329SN/A * width is specified by the parameters; each cycle it tries to fetch 642329SN/A * that many instructions. It supports using a branch predictor to 652329SN/A * predict direction and targets. 662348SN/A * It supports the idling functionality of the CPU by indicating to 672329SN/A * the CPU when it is active and inactive. 681060SN/A */ 691060SN/Atemplate <class Impl> 702292SN/Aclass DefaultFetch 711060SN/A{ 721060SN/A public: 731060SN/A /** Typedefs from Impl. */ 741061SN/A typedef typename Impl::CPUPol CPUPol; 751060SN/A typedef typename Impl::DynInst DynInst; 761061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 772733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 781060SN/A 792292SN/A /** Typedefs from the CPU policy. */ 801061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 811061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 821060SN/A 831060SN/A /** Typedefs from ISA. */ 842107SN/A typedef TheISA::MachInst MachInst; 852292SN/A typedef TheISA::ExtMachInst ExtMachInst; 862632Sstever@eecs.umich.edu 877849SAli.Saidi@ARM.com class FetchTranslation : public BaseTLB::Translation 887849SAli.Saidi@ARM.com { 897849SAli.Saidi@ARM.com protected: 907849SAli.Saidi@ARM.com DefaultFetch<Impl> *fetch; 917849SAli.Saidi@ARM.com 927849SAli.Saidi@ARM.com public: 937849SAli.Saidi@ARM.com FetchTranslation(DefaultFetch<Impl> *_fetch) 947849SAli.Saidi@ARM.com : fetch(_fetch) 957849SAli.Saidi@ARM.com {} 967849SAli.Saidi@ARM.com 977849SAli.Saidi@ARM.com void 987944SGiacomo.Gabrielli@arm.com markDelayed() 997944SGiacomo.Gabrielli@arm.com {} 1007944SGiacomo.Gabrielli@arm.com 1017944SGiacomo.Gabrielli@arm.com void 1027849SAli.Saidi@ARM.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 1037849SAli.Saidi@ARM.com BaseTLB::Mode mode) 1047849SAli.Saidi@ARM.com { 1057849SAli.Saidi@ARM.com assert(mode == BaseTLB::Execute); 1067849SAli.Saidi@ARM.com fetch->finishTranslation(fault, req); 1077849SAli.Saidi@ARM.com delete this; 1087849SAli.Saidi@ARM.com } 1097849SAli.Saidi@ARM.com }; 1102935Sksewell@umich.edu 1118462Sgeoffrey.blake@arm.com private: 1128462Sgeoffrey.blake@arm.com /* Event to delay delivery of a fetch translation result in case of 1138462Sgeoffrey.blake@arm.com * a fault and the nop to carry the fault cannot be generated 1148462Sgeoffrey.blake@arm.com * immediately */ 1158462Sgeoffrey.blake@arm.com class FinishTranslationEvent : public Event 1168462Sgeoffrey.blake@arm.com { 1178462Sgeoffrey.blake@arm.com private: 1188462Sgeoffrey.blake@arm.com DefaultFetch<Impl> *fetch; 1198462Sgeoffrey.blake@arm.com Fault fault; 1208462Sgeoffrey.blake@arm.com RequestPtr req; 1218462Sgeoffrey.blake@arm.com 1228462Sgeoffrey.blake@arm.com public: 1238462Sgeoffrey.blake@arm.com FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 1248462Sgeoffrey.blake@arm.com : fetch(_fetch) 1258462Sgeoffrey.blake@arm.com {} 1268462Sgeoffrey.blake@arm.com 1278462Sgeoffrey.blake@arm.com void setFault(Fault _fault) 1288462Sgeoffrey.blake@arm.com { 1298462Sgeoffrey.blake@arm.com fault = _fault; 1308462Sgeoffrey.blake@arm.com } 1318462Sgeoffrey.blake@arm.com 1328462Sgeoffrey.blake@arm.com void setReq(RequestPtr _req) 1338462Sgeoffrey.blake@arm.com { 1348462Sgeoffrey.blake@arm.com req = _req; 1358462Sgeoffrey.blake@arm.com } 1368462Sgeoffrey.blake@arm.com 1378462Sgeoffrey.blake@arm.com /** Process the delayed finish translation */ 1388462Sgeoffrey.blake@arm.com void process() 1398462Sgeoffrey.blake@arm.com { 1408462Sgeoffrey.blake@arm.com assert(fetch->numInst < fetch->fetchWidth); 1418462Sgeoffrey.blake@arm.com fetch->finishTranslation(fault, req); 1428462Sgeoffrey.blake@arm.com } 1438462Sgeoffrey.blake@arm.com 1448462Sgeoffrey.blake@arm.com const char *description() const 1458462Sgeoffrey.blake@arm.com { 1468462Sgeoffrey.blake@arm.com return "FullO3CPU FetchFinishTranslation"; 1478462Sgeoffrey.blake@arm.com } 1488462Sgeoffrey.blake@arm.com }; 1498462Sgeoffrey.blake@arm.com 1501060SN/A public: 1512329SN/A /** Overall fetch status. Used to determine if the CPU can 1522329SN/A * deschedule itsef due to a lack of activity. 1532292SN/A */ 1542292SN/A enum FetchStatus { 1552292SN/A Active, 1562292SN/A Inactive 1572292SN/A }; 1582292SN/A 1592292SN/A /** Individual thread status. */ 1602292SN/A enum ThreadStatus { 1611060SN/A Running, 1621060SN/A Idle, 1631060SN/A Squashing, 1641060SN/A Blocked, 1652292SN/A Fetching, 1662292SN/A TrapPending, 1672292SN/A QuiescePending, 1687849SAli.Saidi@ARM.com ItlbWait, 1692669Sktlim@umich.edu IcacheWaitResponse, 1702696Sktlim@umich.edu IcacheWaitRetry, 1718460SAli.Saidi@ARM.com IcacheAccessComplete, 1728460SAli.Saidi@ARM.com NoGoodAddr 1731060SN/A }; 1741060SN/A 1752292SN/A /** Fetching Policy, Add new policies here.*/ 1762292SN/A enum FetchPriority { 1772292SN/A SingleThread, 1782292SN/A RoundRobin, 1792292SN/A Branch, 1802292SN/A IQ, 1812292SN/A LSQ 1822292SN/A }; 1831060SN/A 1842292SN/A private: 1852292SN/A /** Fetch status. */ 1862292SN/A FetchStatus _status; 1872292SN/A 1882292SN/A /** Per-thread status. */ 1892292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1902292SN/A 1912292SN/A /** Fetch policy. */ 1922292SN/A FetchPriority fetchPolicy; 1932292SN/A 1942292SN/A /** List that has the threads organized by priority. */ 1956221Snate@binkert.org std::list<ThreadID> priorityList; 1961060SN/A 1971060SN/A public: 1982292SN/A /** DefaultFetch constructor. */ 1995529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2001684SN/A 2012292SN/A /** Returns the name of fetch. */ 2022292SN/A std::string name() const; 2031684SN/A 2042292SN/A /** Registers statistics. */ 2051062SN/A void regStats(); 2061062SN/A 2072292SN/A /** Sets the main backwards communication time buffer pointer. */ 2081060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2091060SN/A 2102292SN/A /** Sets pointer to list of active threads. */ 2116221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 2122292SN/A 2132292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 2141060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2151060SN/A 2162292SN/A /** Initialize stage. */ 2179427SAndreas.Sandberg@ARM.com void startupStage(); 2182292SN/A 2194302Sktlim@umich.edu /** Tells the fetch stage that the Icache is set. */ 2204302Sktlim@umich.edu void setIcache(); 2214302Sktlim@umich.edu 2228707Sandreas.hansson@arm.com /** Handles retrying the fetch access. */ 2238707Sandreas.hansson@arm.com void recvRetry(); 2248707Sandreas.hansson@arm.com 2252292SN/A /** Processes cache completion event. */ 2262669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 2272292SN/A 2289444SAndreas.Sandberg@ARM.com /** Resume after a drain. */ 2299444SAndreas.Sandberg@ARM.com void drainResume(); 2302843Sktlim@umich.edu 2319444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 2329444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2332843Sktlim@umich.edu 2349444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 2359444SAndreas.Sandberg@ARM.com bool isDrained() const; 2362307SN/A 2372348SN/A /** Takes over from another CPU's thread. */ 2382307SN/A void takeOverFrom(); 2392307SN/A 2409444SAndreas.Sandberg@ARM.com /** 2419444SAndreas.Sandberg@ARM.com * Stall the fetch stage after reaching a safe drain point. 2429444SAndreas.Sandberg@ARM.com * 2439444SAndreas.Sandberg@ARM.com * The CPU uses this method to stop fetching instructions from a 2449444SAndreas.Sandberg@ARM.com * thread that has been drained. The drain stall is different from 2459444SAndreas.Sandberg@ARM.com * all other stalls in that it is signaled instantly from the 2469444SAndreas.Sandberg@ARM.com * commit stage (without the normal communication delay) when it 2479444SAndreas.Sandberg@ARM.com * has reached a safe point to drain from. 2489444SAndreas.Sandberg@ARM.com */ 2499444SAndreas.Sandberg@ARM.com void drainStall(ThreadID tid); 2502307SN/A 2512348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2522292SN/A void wakeFromQuiesce(); 2531060SN/A 2541061SN/A private: 2559444SAndreas.Sandberg@ARM.com /** Reset this pipeline stage */ 2569444SAndreas.Sandberg@ARM.com void resetStage(); 2579444SAndreas.Sandberg@ARM.com 2582329SN/A /** Changes the status of this stage to active, and indicates this 2592329SN/A * to the CPU. 2602292SN/A */ 2612292SN/A inline void switchToActive(); 2622292SN/A 2632329SN/A /** Changes the status of this stage to inactive, and indicates 2642329SN/A * this to the CPU. 2652292SN/A */ 2662292SN/A inline void switchToInactive(); 2672292SN/A 2681061SN/A /** 2691061SN/A * Looks up in the branch predictor to see if the next PC should be 2701061SN/A * either next PC+=MachInst or a branch target. 2711763SN/A * @param next_PC Next PC variable passed in by reference. It is 2721061SN/A * expected to be set to the current PC; it will be updated with what 2731061SN/A * the next PC will be. 2742935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 2751061SN/A * @return Whether or not a branch was predicted as taken. 2761061SN/A */ 2777720Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2781062SN/A 2791062SN/A /** 2801062SN/A * Fetches the cache line that contains fetch_PC. Returns any 2811062SN/A * fault that happened. Puts the data into the class variable 2821062SN/A * cacheData. 2837764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 2842292SN/A * @param ret_fault The fault reference that will be set to the result of 2852292SN/A * the icache access. 2862292SN/A * @param tid Thread id. 2877764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 2881062SN/A * @return Any fault that occured. 2891062SN/A */ 2907849SAli.Saidi@ARM.com bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 2917849SAli.Saidi@ARM.com void finishTranslation(Fault fault, RequestPtr mem_req); 2921062SN/A 2937847Sminkyu.jeong@arm.com 2947847Sminkyu.jeong@arm.com /** Check if an interrupt is pending and that we need to handle 2957847Sminkyu.jeong@arm.com */ 2967847Sminkyu.jeong@arm.com bool 2977847Sminkyu.jeong@arm.com checkInterrupt(Addr pc) 2987847Sminkyu.jeong@arm.com { 2997847Sminkyu.jeong@arm.com return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 3007847Sminkyu.jeong@arm.com } 3017847Sminkyu.jeong@arm.com 3022292SN/A /** Squashes a specific thread and resets the PC. */ 3038503Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, 3048503Sgblack@eecs.umich.edu const DynInstPtr squashInst, ThreadID tid); 3051684SN/A 3062292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3072292SN/A * remove any instructions between fetch and decode that should be sqaushed. 3082292SN/A */ 3097720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 3108503Sgblack@eecs.umich.edu const DynInstPtr squashInst, 3118503Sgblack@eecs.umich.edu const InstSeqNum seq_num, ThreadID tid); 3122292SN/A 3132292SN/A /** Checks if a thread is stalled. */ 3146221Snate@binkert.org bool checkStall(ThreadID tid) const; 3152292SN/A 3162292SN/A /** Updates overall fetch stage status; to be called at the end of each 3172292SN/A * cycle. */ 3182292SN/A FetchStatus updateFetchStatus(); 3191684SN/A 3201684SN/A public: 3212292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3222292SN/A * remove any instructions that are not in the ROB. The source of this 3232292SN/A * squash should be the commit stage. 3242292SN/A */ 3258503Sgblack@eecs.umich.edu void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3268503Sgblack@eecs.umich.edu DynInstPtr squashInst, ThreadID tid); 3271684SN/A 3282292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 3292292SN/A * as many instructions as possible. 3302292SN/A */ 3311684SN/A void tick(); 3321684SN/A 3332292SN/A /** Checks all input signals and updates the status as necessary. 3342292SN/A * @return: Returns if the status has changed due to input signals. 3352292SN/A */ 3366221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 3371684SN/A 3382292SN/A /** Does the actual fetching of instructions and passing them on to the 3392292SN/A * next stage. 3402292SN/A * @param status_change fetch() sets this variable if there was a status 3412292SN/A * change (ie switching to IcacheMissStall). 3422292SN/A */ 3432292SN/A void fetch(bool &status_change); 3442292SN/A 3452292SN/A /** Align a PC to the start of an I-cache block. */ 3461062SN/A Addr icacheBlockAlignPC(Addr addr) 3471062SN/A { 3481062SN/A return (addr & ~(cacheBlkMask)); 3491062SN/A } 3501061SN/A 3518541Sgblack@eecs.umich.edu /** The decoder. */ 3529023Sgblack@eecs.umich.edu TheISA::Decoder *decoder[Impl::MaxThreads]; 3538541Sgblack@eecs.umich.edu 3541060SN/A private: 3557764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3567764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3577764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 3587764Sgblack@eecs.umich.edu 3592292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3606221Snate@binkert.org ThreadID getFetchingThread(FetchPriority &fetch_priority); 3612292SN/A 3622292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3636221Snate@binkert.org ThreadID roundRobin(); 3642292SN/A 3652292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3666221Snate@binkert.org ThreadID iqCount(); 3672292SN/A 3682292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3696221Snate@binkert.org ThreadID lsqCount(); 3702292SN/A 3716221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 3726221Snate@binkert.org * policy. */ 3736221Snate@binkert.org ThreadID branchCount(); 3742292SN/A 3758462Sgeoffrey.blake@arm.com /** Pipeline the next I-cache access to the current one. */ 3768462Sgeoffrey.blake@arm.com void pipelineIcacheAccesses(ThreadID tid); 3778462Sgeoffrey.blake@arm.com 3788462Sgeoffrey.blake@arm.com /** Profile the reasons of fetch stall. */ 3798462Sgeoffrey.blake@arm.com void profileStall(ThreadID tid); 3808462Sgeoffrey.blake@arm.com 3812292SN/A private: 3822733Sktlim@umich.edu /** Pointer to the O3CPU. */ 3832733Sktlim@umich.edu O3CPU *cpu; 3841060SN/A 3851060SN/A /** Time buffer interface. */ 3861060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3871060SN/A 3881060SN/A /** Wire to get decode's information from backwards time buffer. */ 3891060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3901060SN/A 3911060SN/A /** Wire to get rename's information from backwards time buffer. */ 3921060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3931060SN/A 3941060SN/A /** Wire to get iew's information from backwards time buffer. */ 3951060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3961060SN/A 3971060SN/A /** Wire to get commit's information from backwards time buffer. */ 3981060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3991060SN/A 4001060SN/A /** Internal fetch instruction queue. */ 4011060SN/A TimeBuffer<FetchStruct> *fetchQueue; 4021060SN/A 4031060SN/A //Might be annoying how this name is different than the queue. 4041060SN/A /** Wire used to write any information heading to decode. */ 4051060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 4061060SN/A 4071061SN/A /** BPredUnit. */ 4089480Snilay@cs.wisc.edu BPredUnit *branchPred; 4091061SN/A 4107720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4112292SN/A 4127764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 4137764Sgblack@eecs.umich.edu 4147764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 4157764Sgblack@eecs.umich.edu 4168314Sgeoffrey.blake@arm.com /** Can the fetch stage redirect from an interrupt on this instruction? */ 4178314Sgeoffrey.blake@arm.com bool delayedCommit[Impl::MaxThreads]; 4188314Sgeoffrey.blake@arm.com 4192678Sktlim@umich.edu /** Memory request used to access cache. */ 4202678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 4212292SN/A 4222292SN/A /** Variable that tracks if fetch has written to the time buffer this 4232292SN/A * cycle. Used to tell CPU if there is activity this cycle. 4242292SN/A */ 4252292SN/A bool wroteToTimeBuffer; 4262292SN/A 4272292SN/A /** Tracks how many instructions has been fetched this cycle. */ 4282292SN/A int numInst; 4292292SN/A 4302292SN/A /** Source of possible stalls. */ 4312292SN/A struct Stalls { 4322292SN/A bool decode; 4332292SN/A bool rename; 4342292SN/A bool iew; 4352292SN/A bool commit; 4369444SAndreas.Sandberg@ARM.com bool drain; 4372292SN/A }; 4382292SN/A 4392292SN/A /** Tracks which stages are telling fetch to stall. */ 4402292SN/A Stalls stalls[Impl::MaxThreads]; 4411060SN/A 4429184Sandreas.hansson@arm.com /** Decode to fetch delay. */ 4439184Sandreas.hansson@arm.com Cycles decodeToFetchDelay; 4441060SN/A 4459184Sandreas.hansson@arm.com /** Rename to fetch delay. */ 4469184Sandreas.hansson@arm.com Cycles renameToFetchDelay; 4471060SN/A 4489184Sandreas.hansson@arm.com /** IEW to fetch delay. */ 4499184Sandreas.hansson@arm.com Cycles iewToFetchDelay; 4501060SN/A 4519184Sandreas.hansson@arm.com /** Commit to fetch delay. */ 4529184Sandreas.hansson@arm.com Cycles commitToFetchDelay; 4531060SN/A 4541060SN/A /** The width of fetch in instructions. */ 4551060SN/A unsigned fetchWidth; 4561060SN/A 4572696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 4582696Sktlim@umich.edu bool cacheBlocked; 4592696Sktlim@umich.edu 4602696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 4612696Sktlim@umich.edu PacketPtr retryPkt; 4622696Sktlim@umich.edu 4632696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 4646221Snate@binkert.org ThreadID retryTid; 4652696Sktlim@umich.edu 4661060SN/A /** Cache block size. */ 4671062SN/A int cacheBlkSize; 4681060SN/A 4691060SN/A /** Mask to get a cache block's address. */ 4701062SN/A Addr cacheBlkMask; 4711060SN/A 4721062SN/A /** The cache line being fetched. */ 4732292SN/A uint8_t *cacheData[Impl::MaxThreads]; 4741060SN/A 4752893Sktlim@umich.edu /** The PC of the cacheline that has been loaded. */ 4762893Sktlim@umich.edu Addr cacheDataPC[Impl::MaxThreads]; 4772893Sktlim@umich.edu 4782906Sktlim@umich.edu /** Whether or not the cache data is valid. */ 4792906Sktlim@umich.edu bool cacheDataValid[Impl::MaxThreads]; 4802906Sktlim@umich.edu 4811060SN/A /** Size of instructions. */ 4821060SN/A int instSize; 4831060SN/A 4841060SN/A /** Icache stall statistics. */ 4852292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 4861062SN/A 4872292SN/A /** List of Active Threads */ 4886221Snate@binkert.org std::list<ThreadID> *activeThreads; 4892292SN/A 4902292SN/A /** Number of threads. */ 4916221Snate@binkert.org ThreadID numThreads; 4922292SN/A 4932292SN/A /** Number of threads that are actively fetching. */ 4946221Snate@binkert.org ThreadID numFetchingThreads; 4952292SN/A 4962292SN/A /** Thread ID being fetched. */ 4976221Snate@binkert.org ThreadID threadFetched; 4982292SN/A 4992348SN/A /** Checks if there is an interrupt pending. If there is, fetch 5002348SN/A * must stop once it is not fetching PAL instructions. 5012348SN/A */ 5022292SN/A bool interruptPending; 5032292SN/A 5048462Sgeoffrey.blake@arm.com /** Set to true if a pipelined I-cache request should be issued. */ 5058462Sgeoffrey.blake@arm.com bool issuePipelinedIfetch[Impl::MaxThreads]; 5068462Sgeoffrey.blake@arm.com 5078462Sgeoffrey.blake@arm.com /** Event used to delay fault generation of translation faults */ 5088462Sgeoffrey.blake@arm.com FinishTranslationEvent finishTranslationEvent; 5098462Sgeoffrey.blake@arm.com 5102292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 5112292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 5125999Snate@binkert.org Stats::Scalar icacheStallCycles; 5132292SN/A /** Stat for total number of fetched instructions. */ 5145999Snate@binkert.org Stats::Scalar fetchedInsts; 5152727Sktlim@umich.edu /** Total number of fetched branches. */ 5165999Snate@binkert.org Stats::Scalar fetchedBranches; 5172292SN/A /** Stat for total number of predicted branches. */ 5185999Snate@binkert.org Stats::Scalar predictedBranches; 5192292SN/A /** Stat for total number of cycles spent fetching. */ 5205999Snate@binkert.org Stats::Scalar fetchCycles; 5212292SN/A /** Stat for total number of cycles spent squashing. */ 5225999Snate@binkert.org Stats::Scalar fetchSquashCycles; 5237849SAli.Saidi@ARM.com /** Stat for total number of cycles spent waiting for translation */ 5247849SAli.Saidi@ARM.com Stats::Scalar fetchTlbCycles; 5252292SN/A /** Stat for total number of cycles spent blocked due to other stages in 5262292SN/A * the pipeline. 5272292SN/A */ 5285999Snate@binkert.org Stats::Scalar fetchIdleCycles; 5292348SN/A /** Total number of cycles spent blocked. */ 5305999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 5312348SN/A /** Total number of cycles spent in any other state. */ 5325999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 5338462Sgeoffrey.blake@arm.com /** Total number of cycles spent in waiting for drains. */ 5348462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingDrainCycles; 5358462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by no active threads to run. */ 5368462Sgeoffrey.blake@arm.com Stats::Scalar fetchNoActiveThreadStallCycles; 5378462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending traps. */ 5388462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingTrapStallCycles; 5398462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending quiesce instructions. */ 5408462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingQuiesceStallCycles; 5418462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by I-cache wait retrys. */ 5428462Sgeoffrey.blake@arm.com Stats::Scalar fetchIcacheWaitRetryStallCycles; 5432292SN/A /** Stat for total number of fetched cache lines. */ 5445999Snate@binkert.org Stats::Scalar fetchedCacheLines; 5452348SN/A /** Total number of outstanding icache accesses that were dropped 5462348SN/A * due to a squash. 5472348SN/A */ 5485999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 5498064SAli.Saidi@ARM.com /** Total number of outstanding tlb accesses that were dropped 5508064SAli.Saidi@ARM.com * due to a squash. 5518064SAli.Saidi@ARM.com */ 5528064SAli.Saidi@ARM.com Stats::Scalar fetchTlbSquashes; 5532292SN/A /** Distribution of number of instructions fetched each cycle. */ 5545999Snate@binkert.org Stats::Distribution fetchNisnDist; 5552348SN/A /** Rate of how often fetch was idle. */ 5562292SN/A Stats::Formula idleRate; 5572348SN/A /** Number of branch fetches per cycle. */ 5582292SN/A Stats::Formula branchRate; 5592348SN/A /** Number of instruction fetched per cycle. */ 5602292SN/A Stats::Formula fetchRate; 5611060SN/A}; 5621060SN/A 5632292SN/A#endif //__CPU_O3_FETCH_HH__ 564