fetch.hh revision 9184
11689SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2010-2011 ARM Limited 37849SAli.Saidi@ARM.com * All rights reserved 47849SAli.Saidi@ARM.com * 57849SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67849SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77849SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87849SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97849SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107849SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117849SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127849SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137849SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_FETCH_HH__ 452292SN/A#define __CPU_O3_FETCH_HH__ 461060SN/A 479020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 482669Sktlim@umich.edu#include "arch/utility.hh" 491461SN/A#include "base/statistics.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 511060SN/A#include "cpu/pc_event.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 537849SAli.Saidi@ARM.com#include "cpu/translation.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 552669Sktlim@umich.edu#include "mem/port.hh" 561461SN/A#include "sim/eventq.hh" 571060SN/A 588737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 595529Snate@binkert.org 601060SN/A/** 612329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 622329SN/A * width is specified by the parameters; each cycle it tries to fetch 632329SN/A * that many instructions. It supports using a branch predictor to 642329SN/A * predict direction and targets. 652348SN/A * It supports the idling functionality of the CPU by indicating to 662329SN/A * the CPU when it is active and inactive. 671060SN/A */ 681060SN/Atemplate <class Impl> 692292SN/Aclass DefaultFetch 701060SN/A{ 711060SN/A public: 721060SN/A /** Typedefs from Impl. */ 731061SN/A typedef typename Impl::CPUPol CPUPol; 741060SN/A typedef typename Impl::DynInst DynInst; 751061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 762733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 771060SN/A 782292SN/A /** Typedefs from the CPU policy. */ 791061SN/A typedef typename CPUPol::BPredUnit BPredUnit; 801061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 811061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 821060SN/A 831060SN/A /** Typedefs from ISA. */ 842107SN/A typedef TheISA::MachInst MachInst; 852292SN/A typedef TheISA::ExtMachInst ExtMachInst; 862632Sstever@eecs.umich.edu 877849SAli.Saidi@ARM.com class FetchTranslation : public BaseTLB::Translation 887849SAli.Saidi@ARM.com { 897849SAli.Saidi@ARM.com protected: 907849SAli.Saidi@ARM.com DefaultFetch<Impl> *fetch; 917849SAli.Saidi@ARM.com 927849SAli.Saidi@ARM.com public: 937849SAli.Saidi@ARM.com FetchTranslation(DefaultFetch<Impl> *_fetch) 947849SAli.Saidi@ARM.com : fetch(_fetch) 957849SAli.Saidi@ARM.com {} 967849SAli.Saidi@ARM.com 977849SAli.Saidi@ARM.com void 987944SGiacomo.Gabrielli@arm.com markDelayed() 997944SGiacomo.Gabrielli@arm.com {} 1007944SGiacomo.Gabrielli@arm.com 1017944SGiacomo.Gabrielli@arm.com void 1027849SAli.Saidi@ARM.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 1037849SAli.Saidi@ARM.com BaseTLB::Mode mode) 1047849SAli.Saidi@ARM.com { 1057849SAli.Saidi@ARM.com assert(mode == BaseTLB::Execute); 1067849SAli.Saidi@ARM.com fetch->finishTranslation(fault, req); 1077849SAli.Saidi@ARM.com delete this; 1087849SAli.Saidi@ARM.com } 1097849SAli.Saidi@ARM.com }; 1102935Sksewell@umich.edu 1118462Sgeoffrey.blake@arm.com private: 1128462Sgeoffrey.blake@arm.com /* Event to delay delivery of a fetch translation result in case of 1138462Sgeoffrey.blake@arm.com * a fault and the nop to carry the fault cannot be generated 1148462Sgeoffrey.blake@arm.com * immediately */ 1158462Sgeoffrey.blake@arm.com class FinishTranslationEvent : public Event 1168462Sgeoffrey.blake@arm.com { 1178462Sgeoffrey.blake@arm.com private: 1188462Sgeoffrey.blake@arm.com DefaultFetch<Impl> *fetch; 1198462Sgeoffrey.blake@arm.com Fault fault; 1208462Sgeoffrey.blake@arm.com RequestPtr req; 1218462Sgeoffrey.blake@arm.com 1228462Sgeoffrey.blake@arm.com public: 1238462Sgeoffrey.blake@arm.com FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 1248462Sgeoffrey.blake@arm.com : fetch(_fetch) 1258462Sgeoffrey.blake@arm.com {} 1268462Sgeoffrey.blake@arm.com 1278462Sgeoffrey.blake@arm.com void setFault(Fault _fault) 1288462Sgeoffrey.blake@arm.com { 1298462Sgeoffrey.blake@arm.com fault = _fault; 1308462Sgeoffrey.blake@arm.com } 1318462Sgeoffrey.blake@arm.com 1328462Sgeoffrey.blake@arm.com void setReq(RequestPtr _req) 1338462Sgeoffrey.blake@arm.com { 1348462Sgeoffrey.blake@arm.com req = _req; 1358462Sgeoffrey.blake@arm.com } 1368462Sgeoffrey.blake@arm.com 1378462Sgeoffrey.blake@arm.com /** Process the delayed finish translation */ 1388462Sgeoffrey.blake@arm.com void process() 1398462Sgeoffrey.blake@arm.com { 1408462Sgeoffrey.blake@arm.com assert(fetch->numInst < fetch->fetchWidth); 1418462Sgeoffrey.blake@arm.com fetch->finishTranslation(fault, req); 1428462Sgeoffrey.blake@arm.com } 1438462Sgeoffrey.blake@arm.com 1448462Sgeoffrey.blake@arm.com const char *description() const 1458462Sgeoffrey.blake@arm.com { 1468462Sgeoffrey.blake@arm.com return "FullO3CPU FetchFinishTranslation"; 1478462Sgeoffrey.blake@arm.com } 1488462Sgeoffrey.blake@arm.com }; 1498462Sgeoffrey.blake@arm.com 1501060SN/A public: 1512329SN/A /** Overall fetch status. Used to determine if the CPU can 1522329SN/A * deschedule itsef due to a lack of activity. 1532292SN/A */ 1542292SN/A enum FetchStatus { 1552292SN/A Active, 1562292SN/A Inactive 1572292SN/A }; 1582292SN/A 1592292SN/A /** Individual thread status. */ 1602292SN/A enum ThreadStatus { 1611060SN/A Running, 1621060SN/A Idle, 1631060SN/A Squashing, 1641060SN/A Blocked, 1652292SN/A Fetching, 1662292SN/A TrapPending, 1672292SN/A QuiescePending, 1682307SN/A SwitchOut, 1697849SAli.Saidi@ARM.com ItlbWait, 1702669Sktlim@umich.edu IcacheWaitResponse, 1712696Sktlim@umich.edu IcacheWaitRetry, 1728460SAli.Saidi@ARM.com IcacheAccessComplete, 1738460SAli.Saidi@ARM.com NoGoodAddr 1741060SN/A }; 1751060SN/A 1762292SN/A /** Fetching Policy, Add new policies here.*/ 1772292SN/A enum FetchPriority { 1782292SN/A SingleThread, 1792292SN/A RoundRobin, 1802292SN/A Branch, 1812292SN/A IQ, 1822292SN/A LSQ 1832292SN/A }; 1841060SN/A 1852292SN/A private: 1862292SN/A /** Fetch status. */ 1872292SN/A FetchStatus _status; 1882292SN/A 1892292SN/A /** Per-thread status. */ 1902292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1912292SN/A 1922292SN/A /** Fetch policy. */ 1932292SN/A FetchPriority fetchPolicy; 1942292SN/A 1952292SN/A /** List that has the threads organized by priority. */ 1966221Snate@binkert.org std::list<ThreadID> priorityList; 1971060SN/A 1981060SN/A public: 1992292SN/A /** DefaultFetch constructor. */ 2005529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2011684SN/A 2022292SN/A /** Returns the name of fetch. */ 2032292SN/A std::string name() const; 2041684SN/A 2052292SN/A /** Registers statistics. */ 2061062SN/A void regStats(); 2071062SN/A 2082292SN/A /** Sets the main backwards communication time buffer pointer. */ 2091060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2101060SN/A 2112292SN/A /** Sets pointer to list of active threads. */ 2126221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 2132292SN/A 2142292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 2151060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2161060SN/A 2172292SN/A /** Initialize stage. */ 2182292SN/A void initStage(); 2192292SN/A 2204302Sktlim@umich.edu /** Tells the fetch stage that the Icache is set. */ 2214302Sktlim@umich.edu void setIcache(); 2224302Sktlim@umich.edu 2238707Sandreas.hansson@arm.com /** Handles retrying the fetch access. */ 2248707Sandreas.hansson@arm.com void recvRetry(); 2258707Sandreas.hansson@arm.com 2262292SN/A /** Processes cache completion event. */ 2272669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 2282292SN/A 2292843Sktlim@umich.edu /** Begins the drain of the fetch stage. */ 2302863Sktlim@umich.edu bool drain(); 2312843Sktlim@umich.edu 2322843Sktlim@umich.edu /** Resumes execution after a drain. */ 2332843Sktlim@umich.edu void resume(); 2342843Sktlim@umich.edu 2352843Sktlim@umich.edu /** Tells fetch stage to prepare to be switched out. */ 2362307SN/A void switchOut(); 2372307SN/A 2382348SN/A /** Takes over from another CPU's thread. */ 2392307SN/A void takeOverFrom(); 2402307SN/A 2412348SN/A /** Checks if the fetch stage is switched out. */ 2422307SN/A bool isSwitchedOut() { return switchedOut; } 2432307SN/A 2442348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2452292SN/A void wakeFromQuiesce(); 2461060SN/A 2471061SN/A private: 2482329SN/A /** Changes the status of this stage to active, and indicates this 2492329SN/A * to the CPU. 2502292SN/A */ 2512292SN/A inline void switchToActive(); 2522292SN/A 2532329SN/A /** Changes the status of this stage to inactive, and indicates 2542329SN/A * this to the CPU. 2552292SN/A */ 2562292SN/A inline void switchToInactive(); 2572292SN/A 2581061SN/A /** 2591061SN/A * Looks up in the branch predictor to see if the next PC should be 2601061SN/A * either next PC+=MachInst or a branch target. 2611763SN/A * @param next_PC Next PC variable passed in by reference. It is 2621061SN/A * expected to be set to the current PC; it will be updated with what 2631061SN/A * the next PC will be. 2642935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 2651061SN/A * @return Whether or not a branch was predicted as taken. 2661061SN/A */ 2677720Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2681062SN/A 2691062SN/A /** 2701062SN/A * Fetches the cache line that contains fetch_PC. Returns any 2711062SN/A * fault that happened. Puts the data into the class variable 2721062SN/A * cacheData. 2737764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 2742292SN/A * @param ret_fault The fault reference that will be set to the result of 2752292SN/A * the icache access. 2762292SN/A * @param tid Thread id. 2777764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 2781062SN/A * @return Any fault that occured. 2791062SN/A */ 2807849SAli.Saidi@ARM.com bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 2817849SAli.Saidi@ARM.com void finishTranslation(Fault fault, RequestPtr mem_req); 2821062SN/A 2837847Sminkyu.jeong@arm.com 2847847Sminkyu.jeong@arm.com /** Check if an interrupt is pending and that we need to handle 2857847Sminkyu.jeong@arm.com */ 2867847Sminkyu.jeong@arm.com bool 2877847Sminkyu.jeong@arm.com checkInterrupt(Addr pc) 2887847Sminkyu.jeong@arm.com { 2897847Sminkyu.jeong@arm.com return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 2907847Sminkyu.jeong@arm.com } 2917847Sminkyu.jeong@arm.com 2922292SN/A /** Squashes a specific thread and resets the PC. */ 2938503Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, 2948503Sgblack@eecs.umich.edu const DynInstPtr squashInst, ThreadID tid); 2951684SN/A 2962292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2972292SN/A * remove any instructions between fetch and decode that should be sqaushed. 2982292SN/A */ 2997720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 3008503Sgblack@eecs.umich.edu const DynInstPtr squashInst, 3018503Sgblack@eecs.umich.edu const InstSeqNum seq_num, ThreadID tid); 3022292SN/A 3032292SN/A /** Checks if a thread is stalled. */ 3046221Snate@binkert.org bool checkStall(ThreadID tid) const; 3052292SN/A 3062292SN/A /** Updates overall fetch stage status; to be called at the end of each 3072292SN/A * cycle. */ 3082292SN/A FetchStatus updateFetchStatus(); 3091684SN/A 3101684SN/A public: 3112292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3122292SN/A * remove any instructions that are not in the ROB. The source of this 3132292SN/A * squash should be the commit stage. 3142292SN/A */ 3158503Sgblack@eecs.umich.edu void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3168503Sgblack@eecs.umich.edu DynInstPtr squashInst, ThreadID tid); 3171684SN/A 3182292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 3192292SN/A * as many instructions as possible. 3202292SN/A */ 3211684SN/A void tick(); 3221684SN/A 3232292SN/A /** Checks all input signals and updates the status as necessary. 3242292SN/A * @return: Returns if the status has changed due to input signals. 3252292SN/A */ 3266221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 3271684SN/A 3282292SN/A /** Does the actual fetching of instructions and passing them on to the 3292292SN/A * next stage. 3302292SN/A * @param status_change fetch() sets this variable if there was a status 3312292SN/A * change (ie switching to IcacheMissStall). 3322292SN/A */ 3332292SN/A void fetch(bool &status_change); 3342292SN/A 3352292SN/A /** Align a PC to the start of an I-cache block. */ 3361062SN/A Addr icacheBlockAlignPC(Addr addr) 3371062SN/A { 3381062SN/A return (addr & ~(cacheBlkMask)); 3391062SN/A } 3401061SN/A 3418541Sgblack@eecs.umich.edu /** The decoder. */ 3429023Sgblack@eecs.umich.edu TheISA::Decoder *decoder[Impl::MaxThreads]; 3438541Sgblack@eecs.umich.edu 3441060SN/A private: 3457764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3467764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3477764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 3487764Sgblack@eecs.umich.edu 3492292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3506221Snate@binkert.org ThreadID getFetchingThread(FetchPriority &fetch_priority); 3512292SN/A 3522292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3536221Snate@binkert.org ThreadID roundRobin(); 3542292SN/A 3552292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3566221Snate@binkert.org ThreadID iqCount(); 3572292SN/A 3582292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3596221Snate@binkert.org ThreadID lsqCount(); 3602292SN/A 3616221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 3626221Snate@binkert.org * policy. */ 3636221Snate@binkert.org ThreadID branchCount(); 3642292SN/A 3658462Sgeoffrey.blake@arm.com /** Pipeline the next I-cache access to the current one. */ 3668462Sgeoffrey.blake@arm.com void pipelineIcacheAccesses(ThreadID tid); 3678462Sgeoffrey.blake@arm.com 3688462Sgeoffrey.blake@arm.com /** Profile the reasons of fetch stall. */ 3698462Sgeoffrey.blake@arm.com void profileStall(ThreadID tid); 3708462Sgeoffrey.blake@arm.com 3712292SN/A private: 3722733Sktlim@umich.edu /** Pointer to the O3CPU. */ 3732733Sktlim@umich.edu O3CPU *cpu; 3741060SN/A 3751060SN/A /** Time buffer interface. */ 3761060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3771060SN/A 3781060SN/A /** Wire to get decode's information from backwards time buffer. */ 3791060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3801060SN/A 3811060SN/A /** Wire to get rename's information from backwards time buffer. */ 3821060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3831060SN/A 3841060SN/A /** Wire to get iew's information from backwards time buffer. */ 3851060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3861060SN/A 3871060SN/A /** Wire to get commit's information from backwards time buffer. */ 3881060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3891060SN/A 3901060SN/A /** Internal fetch instruction queue. */ 3911060SN/A TimeBuffer<FetchStruct> *fetchQueue; 3921060SN/A 3931060SN/A //Might be annoying how this name is different than the queue. 3941060SN/A /** Wire used to write any information heading to decode. */ 3951060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 3961060SN/A 3971061SN/A /** BPredUnit. */ 3981061SN/A BPredUnit branchPred; 3991061SN/A 4007720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4012292SN/A 4027764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 4037764Sgblack@eecs.umich.edu 4047764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 4057764Sgblack@eecs.umich.edu 4068314Sgeoffrey.blake@arm.com /** Can the fetch stage redirect from an interrupt on this instruction? */ 4078314Sgeoffrey.blake@arm.com bool delayedCommit[Impl::MaxThreads]; 4088314Sgeoffrey.blake@arm.com 4092678Sktlim@umich.edu /** Memory request used to access cache. */ 4102678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 4112292SN/A 4122292SN/A /** Variable that tracks if fetch has written to the time buffer this 4132292SN/A * cycle. Used to tell CPU if there is activity this cycle. 4142292SN/A */ 4152292SN/A bool wroteToTimeBuffer; 4162292SN/A 4172292SN/A /** Tracks how many instructions has been fetched this cycle. */ 4182292SN/A int numInst; 4192292SN/A 4202292SN/A /** Source of possible stalls. */ 4212292SN/A struct Stalls { 4222292SN/A bool decode; 4232292SN/A bool rename; 4242292SN/A bool iew; 4252292SN/A bool commit; 4262292SN/A }; 4272292SN/A 4282292SN/A /** Tracks which stages are telling fetch to stall. */ 4292292SN/A Stalls stalls[Impl::MaxThreads]; 4301060SN/A 4319184Sandreas.hansson@arm.com /** Decode to fetch delay. */ 4329184Sandreas.hansson@arm.com Cycles decodeToFetchDelay; 4331060SN/A 4349184Sandreas.hansson@arm.com /** Rename to fetch delay. */ 4359184Sandreas.hansson@arm.com Cycles renameToFetchDelay; 4361060SN/A 4379184Sandreas.hansson@arm.com /** IEW to fetch delay. */ 4389184Sandreas.hansson@arm.com Cycles iewToFetchDelay; 4391060SN/A 4409184Sandreas.hansson@arm.com /** Commit to fetch delay. */ 4419184Sandreas.hansson@arm.com Cycles commitToFetchDelay; 4421060SN/A 4431060SN/A /** The width of fetch in instructions. */ 4441060SN/A unsigned fetchWidth; 4451060SN/A 4462696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 4472696Sktlim@umich.edu bool cacheBlocked; 4482696Sktlim@umich.edu 4492696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 4502696Sktlim@umich.edu PacketPtr retryPkt; 4512696Sktlim@umich.edu 4522696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 4536221Snate@binkert.org ThreadID retryTid; 4542696Sktlim@umich.edu 4551060SN/A /** Cache block size. */ 4561062SN/A int cacheBlkSize; 4571060SN/A 4581060SN/A /** Mask to get a cache block's address. */ 4591062SN/A Addr cacheBlkMask; 4601060SN/A 4611062SN/A /** The cache line being fetched. */ 4622292SN/A uint8_t *cacheData[Impl::MaxThreads]; 4631060SN/A 4642893Sktlim@umich.edu /** The PC of the cacheline that has been loaded. */ 4652893Sktlim@umich.edu Addr cacheDataPC[Impl::MaxThreads]; 4662893Sktlim@umich.edu 4672906Sktlim@umich.edu /** Whether or not the cache data is valid. */ 4682906Sktlim@umich.edu bool cacheDataValid[Impl::MaxThreads]; 4692906Sktlim@umich.edu 4701060SN/A /** Size of instructions. */ 4711060SN/A int instSize; 4721060SN/A 4731060SN/A /** Icache stall statistics. */ 4742292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 4751062SN/A 4762292SN/A /** List of Active Threads */ 4776221Snate@binkert.org std::list<ThreadID> *activeThreads; 4782292SN/A 4792292SN/A /** Number of threads. */ 4806221Snate@binkert.org ThreadID numThreads; 4812292SN/A 4822292SN/A /** Number of threads that are actively fetching. */ 4836221Snate@binkert.org ThreadID numFetchingThreads; 4842292SN/A 4852292SN/A /** Thread ID being fetched. */ 4866221Snate@binkert.org ThreadID threadFetched; 4872292SN/A 4882348SN/A /** Checks if there is an interrupt pending. If there is, fetch 4892348SN/A * must stop once it is not fetching PAL instructions. 4902348SN/A */ 4912292SN/A bool interruptPending; 4922292SN/A 4932843Sktlim@umich.edu /** Is there a drain pending. */ 4942843Sktlim@umich.edu bool drainPending; 4952843Sktlim@umich.edu 4962348SN/A /** Records if fetch is switched out. */ 4972307SN/A bool switchedOut; 4982307SN/A 4998462Sgeoffrey.blake@arm.com /** Set to true if a pipelined I-cache request should be issued. */ 5008462Sgeoffrey.blake@arm.com bool issuePipelinedIfetch[Impl::MaxThreads]; 5018462Sgeoffrey.blake@arm.com 5028462Sgeoffrey.blake@arm.com /** Event used to delay fault generation of translation faults */ 5038462Sgeoffrey.blake@arm.com FinishTranslationEvent finishTranslationEvent; 5048462Sgeoffrey.blake@arm.com 5052292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 5062292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 5075999Snate@binkert.org Stats::Scalar icacheStallCycles; 5082292SN/A /** Stat for total number of fetched instructions. */ 5095999Snate@binkert.org Stats::Scalar fetchedInsts; 5102727Sktlim@umich.edu /** Total number of fetched branches. */ 5115999Snate@binkert.org Stats::Scalar fetchedBranches; 5122292SN/A /** Stat for total number of predicted branches. */ 5135999Snate@binkert.org Stats::Scalar predictedBranches; 5142292SN/A /** Stat for total number of cycles spent fetching. */ 5155999Snate@binkert.org Stats::Scalar fetchCycles; 5162292SN/A /** Stat for total number of cycles spent squashing. */ 5175999Snate@binkert.org Stats::Scalar fetchSquashCycles; 5187849SAli.Saidi@ARM.com /** Stat for total number of cycles spent waiting for translation */ 5197849SAli.Saidi@ARM.com Stats::Scalar fetchTlbCycles; 5202292SN/A /** Stat for total number of cycles spent blocked due to other stages in 5212292SN/A * the pipeline. 5222292SN/A */ 5235999Snate@binkert.org Stats::Scalar fetchIdleCycles; 5242348SN/A /** Total number of cycles spent blocked. */ 5255999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 5262348SN/A /** Total number of cycles spent in any other state. */ 5275999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 5288462Sgeoffrey.blake@arm.com /** Total number of cycles spent in waiting for drains. */ 5298462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingDrainCycles; 5308462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by no active threads to run. */ 5318462Sgeoffrey.blake@arm.com Stats::Scalar fetchNoActiveThreadStallCycles; 5328462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending traps. */ 5338462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingTrapStallCycles; 5348462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending quiesce instructions. */ 5358462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingQuiesceStallCycles; 5368462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by I-cache wait retrys. */ 5378462Sgeoffrey.blake@arm.com Stats::Scalar fetchIcacheWaitRetryStallCycles; 5382292SN/A /** Stat for total number of fetched cache lines. */ 5395999Snate@binkert.org Stats::Scalar fetchedCacheLines; 5402348SN/A /** Total number of outstanding icache accesses that were dropped 5412348SN/A * due to a squash. 5422348SN/A */ 5435999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 5448064SAli.Saidi@ARM.com /** Total number of outstanding tlb accesses that were dropped 5458064SAli.Saidi@ARM.com * due to a squash. 5468064SAli.Saidi@ARM.com */ 5478064SAli.Saidi@ARM.com Stats::Scalar fetchTlbSquashes; 5482292SN/A /** Distribution of number of instructions fetched each cycle. */ 5495999Snate@binkert.org Stats::Distribution fetchNisnDist; 5502348SN/A /** Rate of how often fetch was idle. */ 5512292SN/A Stats::Formula idleRate; 5522348SN/A /** Number of branch fetches per cycle. */ 5532292SN/A Stats::Formula branchRate; 5542348SN/A /** Number of instruction fetched per cycle. */ 5552292SN/A Stats::Formula fetchRate; 5561060SN/A}; 5571060SN/A 5582292SN/A#endif //__CPU_O3_FETCH_HH__ 559