fetch.hh revision 9023
12SN/A/* 29955SGeoffrey.Blake@arm.com * Copyright (c) 2010-2011 ARM Limited 39955SGeoffrey.Blake@arm.com * All rights reserved 49955SGeoffrey.Blake@arm.com * 59955SGeoffrey.Blake@arm.com * The license below extends only to copyright in the software and shall 69955SGeoffrey.Blake@arm.com * not be construed as granting a license to any other intellectual 79955SGeoffrey.Blake@arm.com * property including but not limited to intellectual property relating 89955SGeoffrey.Blake@arm.com * to a hardware implementation of the functionality of the software 99955SGeoffrey.Blake@arm.com * licensed hereunder. You may use the software subject to the license 109955SGeoffrey.Blake@arm.com * terms below provided that you ensure that this notice is replicated 119955SGeoffrey.Blake@arm.com * unmodified and in its entirety in all distributions of the software, 129955SGeoffrey.Blake@arm.com * modified or unmodified, in source code or in binary form. 139955SGeoffrey.Blake@arm.com * 141762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157778Sgblack@eecs.umich.edu * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392SN/A * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412665Ssaidi@eecs.umich.edu * Korey Sewell 422665Ssaidi@eecs.umich.edu */ 437778Sgblack@eecs.umich.edu 449955SGeoffrey.Blake@arm.com#ifndef __CPU_O3_FETCH_HH__ 452SN/A#define __CPU_O3_FETCH_HH__ 462SN/A 471078SN/A#include "arch/decoder.hh" 481078SN/A#include "arch/utility.hh" 491078SN/A#include "base/statistics.hh" 501114SN/A#include "config/the_isa.hh" 511078SN/A#include "cpu/pc_event.hh" 521114SN/A#include "cpu/timebuf.hh" 531114SN/A#include "cpu/translation.hh" 541114SN/A#include "mem/packet.hh" 556216Snate@binkert.org#include "mem/port.hh" 561114SN/A#include "sim/eventq.hh" 571078SN/A 581078SN/Astruct DerivO3CPUParams; 591078SN/A 601078SN/A/** 611078SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 621078SN/A * width is specified by the parameters; each cycle it tries to fetch 631078SN/A * that many instructions. It supports using a branch predictor to 641078SN/A * predict direction and targets. 651078SN/A * It supports the idling functionality of the CPU by indicating to 661078SN/A * the CPU when it is active and inactive. 671078SN/A */ 681078SN/Atemplate <class Impl> 691078SN/Aclass DefaultFetch 701078SN/A{ 712SN/A public: 721114SN/A /** Typedefs from Impl. */ 732SN/A typedef typename Impl::CPUPol CPUPol; 741114SN/A typedef typename Impl::DynInst DynInst; 751114SN/A typedef typename Impl::DynInstPtr DynInstPtr; 761114SN/A typedef typename Impl::O3CPU O3CPU; 771114SN/A 781114SN/A /** Typedefs from the CPU policy. */ 791114SN/A typedef typename CPUPol::BPredUnit BPredUnit; 801114SN/A typedef typename CPUPol::FetchStruct FetchStruct; 811078SN/A typedef typename CPUPol::TimeStruct TimeStruct; 821114SN/A 831114SN/A /** Typedefs from ISA. */ 841114SN/A typedef TheISA::MachInst MachInst; 851114SN/A typedef TheISA::ExtMachInst ExtMachInst; 861114SN/A 871114SN/A class FetchTranslation : public BaseTLB::Translation 881114SN/A { 891079SN/A protected: 901114SN/A DefaultFetch<Impl> *fetch; 911114SN/A 921114SN/A public: 931114SN/A FetchTranslation(DefaultFetch<Impl> *_fetch) 941114SN/A : fetch(_fetch) 951114SN/A {} 9610251Satgutier@umich.edu 9710251Satgutier@umich.edu void 9810251Satgutier@umich.edu markDelayed() 9910251Satgutier@umich.edu {} 10010251Satgutier@umich.edu 10110251Satgutier@umich.edu void 10210251Satgutier@umich.edu finish(Fault fault, RequestPtr req, ThreadContext *tc, 10310251Satgutier@umich.edu BaseTLB::Mode mode) 10410251Satgutier@umich.edu { 10510251Satgutier@umich.edu assert(mode == BaseTLB::Execute); 10610251Satgutier@umich.edu fetch->finishTranslation(fault, req); 10710251Satgutier@umich.edu delete this; 1081114SN/A } 1091137SN/A }; 1101137SN/A 1111137SN/A private: 1121137SN/A /* Event to delay delivery of a fetch translation result in case of 1131137SN/A * a fault and the nop to carry the fault cannot be generated 1141137SN/A * immediately */ 1151137SN/A class FinishTranslationEvent : public Event 1161137SN/A { 1171137SN/A private: 1181137SN/A DefaultFetch<Impl> *fetch; 1191137SN/A Fault fault; 1201137SN/A RequestPtr req; 1211137SN/A 1221114SN/A public: 1231114SN/A FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 1241114SN/A : fetch(_fetch) 1251114SN/A {} 1261114SN/A 1271114SN/A void setFault(Fault _fault) 1281078SN/A { 1299955SGeoffrey.Blake@arm.com fault = _fault; 1309955SGeoffrey.Blake@arm.com } 1319955SGeoffrey.Blake@arm.com 1329955SGeoffrey.Blake@arm.com void setReq(RequestPtr _req) 1339955SGeoffrey.Blake@arm.com { 1349955SGeoffrey.Blake@arm.com req = _req; 1359955SGeoffrey.Blake@arm.com } 1369955SGeoffrey.Blake@arm.com 1379955SGeoffrey.Blake@arm.com /** Process the delayed finish translation */ 1389955SGeoffrey.Blake@arm.com void process() 1399955SGeoffrey.Blake@arm.com { 1409955SGeoffrey.Blake@arm.com assert(fetch->numInst < fetch->fetchWidth); 1419955SGeoffrey.Blake@arm.com fetch->finishTranslation(fault, req); 1429955SGeoffrey.Blake@arm.com } 1439955SGeoffrey.Blake@arm.com 1449955SGeoffrey.Blake@arm.com const char *description() const 1451114SN/A { 1461114SN/A return "FullO3CPU FetchFinishTranslation"; 1471079SN/A } 1489955SGeoffrey.Blake@arm.com }; 1499955SGeoffrey.Blake@arm.com 1509955SGeoffrey.Blake@arm.com public: 1519955SGeoffrey.Blake@arm.com /** Overall fetch status. Used to determine if the CPU can 1529955SGeoffrey.Blake@arm.com * deschedule itsef due to a lack of activity. 1539955SGeoffrey.Blake@arm.com */ 1541079SN/A enum FetchStatus { 1551079SN/A Active, 1561079SN/A Inactive 1571079SN/A }; 1581079SN/A 1591078SN/A /** Individual thread status. */ 1601078SN/A enum ThreadStatus { 1611114SN/A Running, 1621114SN/A Idle, 1631114SN/A Squashing, 1641114SN/A Blocked, 1659955SGeoffrey.Blake@arm.com Fetching, 1662566SN/A TrapPending, 1671114SN/A QuiescePending, 1681114SN/A SwitchOut, 1691114SN/A ItlbWait, 1702566SN/A IcacheWaitResponse, 1711114SN/A IcacheWaitRetry, 1721114SN/A IcacheAccessComplete, 1731114SN/A NoGoodAddr 1741114SN/A }; 1751114SN/A 1761114SN/A /** Fetching Policy, Add new policies here.*/ 1771114SN/A enum FetchPriority { 1781114SN/A SingleThread, 1791114SN/A RoundRobin, 1802566SN/A Branch, 1811114SN/A IQ, 1822566SN/A LSQ 1832566SN/A }; 1841114SN/A 18510469Sandreas.hansson@arm.com private: 1865782Ssaidi@eecs.umich.edu /** Fetch status. */ 1875782Ssaidi@eecs.umich.edu FetchStatus _status; 1881114SN/A 1891114SN/A /** Per-thread status. */ 1901114SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1911114SN/A 1921114SN/A /** Fetch policy. */ 1937777Sgblack@eecs.umich.edu FetchPriority fetchPolicy; 1947777Sgblack@eecs.umich.edu 1957777Sgblack@eecs.umich.edu /** List that has the threads organized by priority. */ 1967777Sgblack@eecs.umich.edu std::list<ThreadID> priorityList; 1977777Sgblack@eecs.umich.edu 1987777Sgblack@eecs.umich.edu public: 1997777Sgblack@eecs.umich.edu /** DefaultFetch constructor. */ 2007777Sgblack@eecs.umich.edu DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2017777Sgblack@eecs.umich.edu 2027777Sgblack@eecs.umich.edu /** Returns the name of fetch. */ 2037777Sgblack@eecs.umich.edu std::string name() const; 2047777Sgblack@eecs.umich.edu 2057777Sgblack@eecs.umich.edu /** Registers statistics. */ 2067777Sgblack@eecs.umich.edu void regStats(); 2077777Sgblack@eecs.umich.edu 2087777Sgblack@eecs.umich.edu /** Sets the main backwards communication time buffer pointer. */ 2097777Sgblack@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2107777Sgblack@eecs.umich.edu 2117777Sgblack@eecs.umich.edu /** Sets pointer to list of active threads. */ 2127777Sgblack@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 2137777Sgblack@eecs.umich.edu 2147777Sgblack@eecs.umich.edu /** Sets pointer to time buffer used to communicate to the next stage. */ 2157777Sgblack@eecs.umich.edu void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2167777Sgblack@eecs.umich.edu 2177777Sgblack@eecs.umich.edu /** Initialize stage. */ 2187777Sgblack@eecs.umich.edu void initStage(); 2197777Sgblack@eecs.umich.edu 2207777Sgblack@eecs.umich.edu /** Tells the fetch stage that the Icache is set. */ 2217777Sgblack@eecs.umich.edu void setIcache(); 2227777Sgblack@eecs.umich.edu 2237777Sgblack@eecs.umich.edu /** Handles retrying the fetch access. */ 2247777Sgblack@eecs.umich.edu void recvRetry(); 2257777Sgblack@eecs.umich.edu 2267777Sgblack@eecs.umich.edu /** Processes cache completion event. */ 2277777Sgblack@eecs.umich.edu void processCacheCompletion(PacketPtr pkt); 2287777Sgblack@eecs.umich.edu 2297777Sgblack@eecs.umich.edu /** Begins the drain of the fetch stage. */ 2307777Sgblack@eecs.umich.edu bool drain(); 2317777Sgblack@eecs.umich.edu 2327777Sgblack@eecs.umich.edu /** Resumes execution after a drain. */ 2337777Sgblack@eecs.umich.edu void resume(); 2347777Sgblack@eecs.umich.edu 2357777Sgblack@eecs.umich.edu /** Tells fetch stage to prepare to be switched out. */ 2367777Sgblack@eecs.umich.edu void switchOut(); 2377777Sgblack@eecs.umich.edu 2387777Sgblack@eecs.umich.edu /** Takes over from another CPU's thread. */ 2397777Sgblack@eecs.umich.edu void takeOverFrom(); 2407777Sgblack@eecs.umich.edu 2417777Sgblack@eecs.umich.edu /** Checks if the fetch stage is switched out. */ 2427777Sgblack@eecs.umich.edu bool isSwitchedOut() { return switchedOut; } 2437777Sgblack@eecs.umich.edu 2447777Sgblack@eecs.umich.edu /** Tells fetch to wake up from a quiesce instruction. */ 2457777Sgblack@eecs.umich.edu void wakeFromQuiesce(); 2467777Sgblack@eecs.umich.edu 2477777Sgblack@eecs.umich.edu private: 2487777Sgblack@eecs.umich.edu /** Changes the status of this stage to active, and indicates this 2497777Sgblack@eecs.umich.edu * to the CPU. 2507777Sgblack@eecs.umich.edu */ 2517777Sgblack@eecs.umich.edu inline void switchToActive(); 2521114SN/A 2531114SN/A /** Changes the status of this stage to inactive, and indicates 2541078SN/A * this to the CPU. 2551078SN/A */ 2561092SN/A inline void switchToInactive(); 2571078SN/A 2581078SN/A /** 2591078SN/A * Looks up in the branch predictor to see if the next PC should be 2601078SN/A * either next PC+=MachInst or a branch target. 2611078SN/A * @param next_PC Next PC variable passed in by reference. It is 2621078SN/A * expected to be set to the current PC; it will be updated with what 2631078SN/A * the next PC will be. 2641092SN/A * @param next_NPC Used for ISAs which use delay slots. 2651078SN/A * @return Whether or not a branch was predicted as taken. 2661078SN/A */ 2671078SN/A bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2681092SN/A 2695761Ssaidi@eecs.umich.edu /** 2705761Ssaidi@eecs.umich.edu * Fetches the cache line that contains fetch_PC. Returns any 2715761Ssaidi@eecs.umich.edu * fault that happened. Puts the data into the class variable 2721114SN/A * cacheData. 2731079SN/A * @param vaddr The memory address that is being fetched from. 2741079SN/A * @param ret_fault The fault reference that will be set to the result of 2751079SN/A * the icache access. 2761079SN/A * @param tid Thread id. 2771079SN/A * @param pc The actual PC of the current instruction. 2781079SN/A * @return Any fault that occured. 2791078SN/A */ 2801078SN/A bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 2811114SN/A void finishTranslation(Fault fault, RequestPtr mem_req); 2821114SN/A 2831114SN/A 2841114SN/A /** Check if an interrupt is pending and that we need to handle 2851114SN/A */ 2862566SN/A bool 2879955SGeoffrey.Blake@arm.com checkInterrupt(Addr pc) 2881114SN/A { 2892566SN/A return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 2901114SN/A } 2915484Snate@binkert.org 2929955SGeoffrey.Blake@arm.com /** Squashes a specific thread and resets the PC. */ 2935484Snate@binkert.org inline void doSquash(const TheISA::PCState &newPC, 2945484Snate@binkert.org const DynInstPtr squashInst, ThreadID tid); 2955484Snate@binkert.org 2965484Snate@binkert.org /** Squashes a specific thread and resets the PC. Also tells the CPU to 2975484Snate@binkert.org * remove any instructions between fetch and decode that should be sqaushed. 2989955SGeoffrey.Blake@arm.com */ 2999955SGeoffrey.Blake@arm.com void squashFromDecode(const TheISA::PCState &newPC, 3005484Snate@binkert.org const DynInstPtr squashInst, 3011114SN/A const InstSeqNum seq_num, ThreadID tid); 3021114SN/A 3031114SN/A /** Checks if a thread is stalled. */ 3049955SGeoffrey.Blake@arm.com bool checkStall(ThreadID tid) const; 3059955SGeoffrey.Blake@arm.com 3069955SGeoffrey.Blake@arm.com /** Updates overall fetch stage status; to be called at the end of each 3079955SGeoffrey.Blake@arm.com * cycle. */ 3081114SN/A FetchStatus updateFetchStatus(); 3099955SGeoffrey.Blake@arm.com 3109955SGeoffrey.Blake@arm.com public: 3115484Snate@binkert.org /** Squashes a specific thread and resets the PC. Also tells the CPU to 3125484Snate@binkert.org * remove any instructions that are not in the ROB. The source of this 3131114SN/A * squash should be the commit stage. 3145484Snate@binkert.org */ 3159955SGeoffrey.Blake@arm.com void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3169955SGeoffrey.Blake@arm.com DynInstPtr squashInst, ThreadID tid); 3175484Snate@binkert.org 3185484Snate@binkert.org /** Ticks the fetch stage, processing all inputs signals and fetching 3191114SN/A * as many instructions as possible. 3202566SN/A */ 3211114SN/A void tick(); 3221114SN/A 3231114SN/A /** Checks all input signals and updates the status as necessary. 3242566SN/A * @return: Returns if the status has changed due to input signals. 3252566SN/A */ 3261114SN/A bool checkSignalsAndUpdate(ThreadID tid); 32710469Sandreas.hansson@arm.com 3289955SGeoffrey.Blake@arm.com /** Does the actual fetching of instructions and passing them on to the 3299955SGeoffrey.Blake@arm.com * next stage. 3301114SN/A * @param status_change fetch() sets this variable if there was a status 3311114SN/A * change (ie switching to IcacheMissStall). 3321114SN/A */ 3331114SN/A void fetch(bool &status_change); 3341114SN/A 3351114SN/A /** Align a PC to the start of an I-cache block. */ 3361114SN/A Addr icacheBlockAlignPC(Addr addr) 3371114SN/A { 3381114SN/A return (addr & ~(cacheBlkMask)); 3391114SN/A } 3401114SN/A 3411114SN/A /** The decoder. */ 3421114SN/A TheISA::Decoder *decoder[Impl::MaxThreads]; 3431114SN/A 3441114SN/A private: 3451114SN/A DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3461114SN/A StaticInstPtr curMacroop, TheISA::PCState thisPC, 3471114SN/A TheISA::PCState nextPC, bool trace); 3481114SN/A 3491114SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3501114SN/A ThreadID getFetchingThread(FetchPriority &fetch_priority); 3511114SN/A 3521114SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3531114SN/A ThreadID roundRobin(); 3541114SN/A 3551114SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3561114SN/A ThreadID iqCount(); 3571114SN/A 3581114SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3591114SN/A ThreadID lsqCount(); 3601114SN/A 3619955SGeoffrey.Blake@arm.com /** Returns the appropriate thread to fetch using the branch count 3629955SGeoffrey.Blake@arm.com * policy. */ 3639955SGeoffrey.Blake@arm.com ThreadID branchCount(); 3649955SGeoffrey.Blake@arm.com 3659955SGeoffrey.Blake@arm.com /** Pipeline the next I-cache access to the current one. */ 3669955SGeoffrey.Blake@arm.com void pipelineIcacheAccesses(ThreadID tid); 3679955SGeoffrey.Blake@arm.com 3689955SGeoffrey.Blake@arm.com /** Profile the reasons of fetch stall. */ 3699955SGeoffrey.Blake@arm.com void profileStall(ThreadID tid); 3709955SGeoffrey.Blake@arm.com 3719955SGeoffrey.Blake@arm.com private: 3729955SGeoffrey.Blake@arm.com /** Pointer to the O3CPU. */ 3739955SGeoffrey.Blake@arm.com O3CPU *cpu; 3749955SGeoffrey.Blake@arm.com 3759955SGeoffrey.Blake@arm.com /** Time buffer interface. */ 3769955SGeoffrey.Blake@arm.com TimeBuffer<TimeStruct> *timeBuffer; 3779955SGeoffrey.Blake@arm.com 3789955SGeoffrey.Blake@arm.com /** Wire to get decode's information from backwards time buffer. */ 3799955SGeoffrey.Blake@arm.com typename TimeBuffer<TimeStruct>::wire fromDecode; 3809955SGeoffrey.Blake@arm.com 3819955SGeoffrey.Blake@arm.com /** Wire to get rename's information from backwards time buffer. */ 3829955SGeoffrey.Blake@arm.com typename TimeBuffer<TimeStruct>::wire fromRename; 3839955SGeoffrey.Blake@arm.com 3849955SGeoffrey.Blake@arm.com /** Wire to get iew's information from backwards time buffer. */ 3859955SGeoffrey.Blake@arm.com typename TimeBuffer<TimeStruct>::wire fromIEW; 3869955SGeoffrey.Blake@arm.com 3879955SGeoffrey.Blake@arm.com /** Wire to get commit's information from backwards time buffer. */ 3889955SGeoffrey.Blake@arm.com typename TimeBuffer<TimeStruct>::wire fromCommit; 3899955SGeoffrey.Blake@arm.com 3909955SGeoffrey.Blake@arm.com /** Internal fetch instruction queue. */ 3919955SGeoffrey.Blake@arm.com TimeBuffer<FetchStruct> *fetchQueue; 3929955SGeoffrey.Blake@arm.com 3939955SGeoffrey.Blake@arm.com //Might be annoying how this name is different than the queue. 3949955SGeoffrey.Blake@arm.com /** Wire used to write any information heading to decode. */ 3959955SGeoffrey.Blake@arm.com typename TimeBuffer<FetchStruct>::wire toDecode; 3969955SGeoffrey.Blake@arm.com 3979955SGeoffrey.Blake@arm.com /** BPredUnit. */ 3989955SGeoffrey.Blake@arm.com BPredUnit branchPred; 3999955SGeoffrey.Blake@arm.com 4009955SGeoffrey.Blake@arm.com TheISA::PCState pc[Impl::MaxThreads]; 4019955SGeoffrey.Blake@arm.com 4029955SGeoffrey.Blake@arm.com Addr fetchOffset[Impl::MaxThreads]; 4039955SGeoffrey.Blake@arm.com 4049955SGeoffrey.Blake@arm.com StaticInstPtr macroop[Impl::MaxThreads]; 4059955SGeoffrey.Blake@arm.com 4069955SGeoffrey.Blake@arm.com /** Can the fetch stage redirect from an interrupt on this instruction? */ 4079955SGeoffrey.Blake@arm.com bool delayedCommit[Impl::MaxThreads]; 4089955SGeoffrey.Blake@arm.com 4099955SGeoffrey.Blake@arm.com /** Memory request used to access cache. */ 4109955SGeoffrey.Blake@arm.com RequestPtr memReq[Impl::MaxThreads]; 4119955SGeoffrey.Blake@arm.com 4129955SGeoffrey.Blake@arm.com /** Variable that tracks if fetch has written to the time buffer this 4139955SGeoffrey.Blake@arm.com * cycle. Used to tell CPU if there is activity this cycle. 4149955SGeoffrey.Blake@arm.com */ 4159955SGeoffrey.Blake@arm.com bool wroteToTimeBuffer; 4169955SGeoffrey.Blake@arm.com 4179955SGeoffrey.Blake@arm.com /** Tracks how many instructions has been fetched this cycle. */ 4189955SGeoffrey.Blake@arm.com int numInst; 4199955SGeoffrey.Blake@arm.com 4209955SGeoffrey.Blake@arm.com /** Source of possible stalls. */ 4219955SGeoffrey.Blake@arm.com struct Stalls { 4229955SGeoffrey.Blake@arm.com bool decode; 4239955SGeoffrey.Blake@arm.com bool rename; 4249955SGeoffrey.Blake@arm.com bool iew; 4259955SGeoffrey.Blake@arm.com bool commit; 4269955SGeoffrey.Blake@arm.com }; 4279955SGeoffrey.Blake@arm.com 4289955SGeoffrey.Blake@arm.com /** Tracks which stages are telling fetch to stall. */ 4299955SGeoffrey.Blake@arm.com Stalls stalls[Impl::MaxThreads]; 4309955SGeoffrey.Blake@arm.com 4319955SGeoffrey.Blake@arm.com /** Decode to fetch delay, in ticks. */ 4329955SGeoffrey.Blake@arm.com unsigned decodeToFetchDelay; 4339955SGeoffrey.Blake@arm.com 4349955SGeoffrey.Blake@arm.com /** Rename to fetch delay, in ticks. */ 4359955SGeoffrey.Blake@arm.com unsigned renameToFetchDelay; 4369955SGeoffrey.Blake@arm.com 4379955SGeoffrey.Blake@arm.com /** IEW to fetch delay, in ticks. */ 4389955SGeoffrey.Blake@arm.com unsigned iewToFetchDelay; 4399955SGeoffrey.Blake@arm.com 4409955SGeoffrey.Blake@arm.com /** Commit to fetch delay, in ticks. */ 4419955SGeoffrey.Blake@arm.com unsigned commitToFetchDelay; 4429955SGeoffrey.Blake@arm.com 44310469Sandreas.hansson@arm.com /** The width of fetch in instructions. */ 4449955SGeoffrey.Blake@arm.com unsigned fetchWidth; 4459955SGeoffrey.Blake@arm.com 4469955SGeoffrey.Blake@arm.com /** Is the cache blocked? If so no threads can access it. */ 4479955SGeoffrey.Blake@arm.com bool cacheBlocked; 4489955SGeoffrey.Blake@arm.com 4499955SGeoffrey.Blake@arm.com /** The packet that is waiting to be retried. */ 4509955SGeoffrey.Blake@arm.com PacketPtr retryPkt; 4519955SGeoffrey.Blake@arm.com 4529955SGeoffrey.Blake@arm.com /** The thread that is waiting on the cache to tell fetch to retry. */ 4539955SGeoffrey.Blake@arm.com ThreadID retryTid; 4549955SGeoffrey.Blake@arm.com 4559955SGeoffrey.Blake@arm.com /** Cache block size. */ 4569955SGeoffrey.Blake@arm.com int cacheBlkSize; 4579955SGeoffrey.Blake@arm.com 4589955SGeoffrey.Blake@arm.com /** Mask to get a cache block's address. */ 4599955SGeoffrey.Blake@arm.com Addr cacheBlkMask; 4609955SGeoffrey.Blake@arm.com 4619955SGeoffrey.Blake@arm.com /** The cache line being fetched. */ 4629955SGeoffrey.Blake@arm.com uint8_t *cacheData[Impl::MaxThreads]; 4639955SGeoffrey.Blake@arm.com 4649955SGeoffrey.Blake@arm.com /** The PC of the cacheline that has been loaded. */ 4659955SGeoffrey.Blake@arm.com Addr cacheDataPC[Impl::MaxThreads]; 4669955SGeoffrey.Blake@arm.com 4679955SGeoffrey.Blake@arm.com /** Whether or not the cache data is valid. */ 4689955SGeoffrey.Blake@arm.com bool cacheDataValid[Impl::MaxThreads]; 4699955SGeoffrey.Blake@arm.com 4709955SGeoffrey.Blake@arm.com /** Size of instructions. */ 4719955SGeoffrey.Blake@arm.com int instSize; 4729955SGeoffrey.Blake@arm.com 4739955SGeoffrey.Blake@arm.com /** Icache stall statistics. */ 4749955SGeoffrey.Blake@arm.com Counter lastIcacheStall[Impl::MaxThreads]; 4759955SGeoffrey.Blake@arm.com 4769955SGeoffrey.Blake@arm.com /** List of Active Threads */ 4779955SGeoffrey.Blake@arm.com std::list<ThreadID> *activeThreads; 4789955SGeoffrey.Blake@arm.com 4799955SGeoffrey.Blake@arm.com /** Number of threads. */ 4809955SGeoffrey.Blake@arm.com ThreadID numThreads; 4819955SGeoffrey.Blake@arm.com 4829955SGeoffrey.Blake@arm.com /** Number of threads that are actively fetching. */ 4839955SGeoffrey.Blake@arm.com ThreadID numFetchingThreads; 4849955SGeoffrey.Blake@arm.com 4859955SGeoffrey.Blake@arm.com /** Thread ID being fetched. */ 4869955SGeoffrey.Blake@arm.com ThreadID threadFetched; 4879955SGeoffrey.Blake@arm.com 4889955SGeoffrey.Blake@arm.com /** Checks if there is an interrupt pending. If there is, fetch 4899955SGeoffrey.Blake@arm.com * must stop once it is not fetching PAL instructions. 4909955SGeoffrey.Blake@arm.com */ 4919955SGeoffrey.Blake@arm.com bool interruptPending; 4929955SGeoffrey.Blake@arm.com 4939955SGeoffrey.Blake@arm.com /** Is there a drain pending. */ 4949955SGeoffrey.Blake@arm.com bool drainPending; 4959955SGeoffrey.Blake@arm.com 4969955SGeoffrey.Blake@arm.com /** Records if fetch is switched out. */ 4979955SGeoffrey.Blake@arm.com bool switchedOut; 4989955SGeoffrey.Blake@arm.com 4999955SGeoffrey.Blake@arm.com /** Set to true if a pipelined I-cache request should be issued. */ 5009955SGeoffrey.Blake@arm.com bool issuePipelinedIfetch[Impl::MaxThreads]; 5019955SGeoffrey.Blake@arm.com 5029955SGeoffrey.Blake@arm.com /** Event used to delay fault generation of translation faults */ 5039955SGeoffrey.Blake@arm.com FinishTranslationEvent finishTranslationEvent; 5049955SGeoffrey.Blake@arm.com 5059955SGeoffrey.Blake@arm.com // @todo: Consider making these vectors and tracking on a per thread basis. 5069955SGeoffrey.Blake@arm.com /** Stat for total number of cycles stalled due to an icache miss. */ 5071114SN/A Stats::Scalar icacheStallCycles; 5081114SN/A /** Stat for total number of fetched instructions. */ 5091114SN/A Stats::Scalar fetchedInsts; 5101114SN/A /** Total number of fetched branches. */ 5111078SN/A Stats::Scalar fetchedBranches; 5121078SN/A /** Stat for total number of predicted branches. */ 5131078SN/A Stats::Scalar predictedBranches; 5141078SN/A /** Stat for total number of cycles spent fetching. */ 5151078SN/A Stats::Scalar fetchCycles; 5169955SGeoffrey.Blake@arm.com /** Stat for total number of cycles spent squashing. */ 5171078SN/A Stats::Scalar fetchSquashCycles; 5181078SN/A /** Stat for total number of cycles spent waiting for translation */ 5191092SN/A Stats::Scalar fetchTlbCycles; 5201078SN/A /** Stat for total number of cycles spent blocked due to other stages in 5211078SN/A * the pipeline. 5221092SN/A */ 5235761Ssaidi@eecs.umich.edu Stats::Scalar fetchIdleCycles; 5245761Ssaidi@eecs.umich.edu /** Total number of cycles spent blocked. */ 5251078SN/A Stats::Scalar fetchBlockedCycles; 5261114SN/A /** Total number of cycles spent in any other state. */ 5271114SN/A Stats::Scalar fetchMiscStallCycles; 5281079SN/A /** Total number of cycles spent in waiting for drains. */ 5291079SN/A Stats::Scalar fetchPendingDrainCycles; 5301079SN/A /** Total number of stall cycles caused by no active threads to run. */ 5311079SN/A Stats::Scalar fetchNoActiveThreadStallCycles; 5321079SN/A /** Total number of stall cycles caused by pending traps. */ 5331078SN/A Stats::Scalar fetchPendingTrapStallCycles; 5341078SN/A /** Total number of stall cycles caused by pending quiesce instructions. */ 5351114SN/A Stats::Scalar fetchPendingQuiesceStallCycles; 5361114SN/A /** Total number of stall cycles caused by I-cache wait retrys. */ 5371114SN/A Stats::Scalar fetchIcacheWaitRetryStallCycles; 5382566SN/A /** Stat for total number of fetched cache lines. */ 5395782Ssaidi@eecs.umich.edu Stats::Scalar fetchedCacheLines; 5401114SN/A /** Total number of outstanding icache accesses that were dropped 5415782Ssaidi@eecs.umich.edu * due to a squash. 5421114SN/A */ 5431114SN/A Stats::Scalar fetchIcacheSquashes; 5445484Snate@binkert.org /** Total number of outstanding tlb accesses that were dropped 5459955SGeoffrey.Blake@arm.com * due to a squash. 5469955SGeoffrey.Blake@arm.com */ 5479955SGeoffrey.Blake@arm.com Stats::Scalar fetchTlbSquashes; 5489955SGeoffrey.Blake@arm.com /** Distribution of number of instructions fetched each cycle. */ 5499955SGeoffrey.Blake@arm.com Stats::Distribution fetchNisnDist; 5509955SGeoffrey.Blake@arm.com /** Rate of how often fetch was idle. */ 5519955SGeoffrey.Blake@arm.com Stats::Formula idleRate; 5529955SGeoffrey.Blake@arm.com /** Number of branch fetches per cycle. */ 5531114SN/A Stats::Formula branchRate; 5541114SN/A /** Number of instruction fetched per cycle. */ 5551114SN/A Stats::Formula fetchRate; 5561114SN/A}; 5571114SN/A 5585782Ssaidi@eecs.umich.edu#endif //__CPU_O3_FETCH_HH__ 5595782Ssaidi@eecs.umich.edu