fetch.hh revision 9020
19665Sandreas.hansson@arm.com/* 29665Sandreas.hansson@arm.com * Copyright (c) 2010-2011 ARM Limited 39665Sandreas.hansson@arm.com * All rights reserved 49665Sandreas.hansson@arm.com * 59665Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69665Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79665Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89665Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99665Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109665Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119665Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129665Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 135353Svilas.sridharan@gmail.com * 143395Shsul@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 153395Shsul@eecs.umich.edu * All rights reserved. 163395Shsul@eecs.umich.edu * 173395Shsul@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 183395Shsul@eecs.umich.edu * modification, are permitted provided that the following conditions are 193395Shsul@eecs.umich.edu * met: redistributions of source code must retain the above copyright 203395Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 213395Shsul@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 223395Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 233395Shsul@eecs.umich.edu * documentation and/or other materials provided with the distribution; 243395Shsul@eecs.umich.edu * neither the name of the copyright holders nor the names of its 253395Shsul@eecs.umich.edu * contributors may be used to endorse or promote products derived from 263395Shsul@eecs.umich.edu * this software without specific prior written permission. 273395Shsul@eecs.umich.edu * 283395Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293395Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303395Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313395Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323395Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333395Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343395Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353395Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363395Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373395Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383395Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393395Shsul@eecs.umich.edu * 403395Shsul@eecs.umich.edu * Authors: Kevin Lim 418920Snilay@cs.wisc.edu * Korey Sewell 428920Snilay@cs.wisc.edu */ 438920Snilay@cs.wisc.edu 4411688Sandreas.hansson@arm.com#ifndef __CPU_O3_FETCH_HH__ 457025SBrad.Beckmann@amd.com#define __CPU_O3_FETCH_HH__ 4611688Sandreas.hansson@arm.com 4711688Sandreas.hansson@arm.com#include "arch/decoder.hh" 4811688Sandreas.hansson@arm.com#include "arch/predecoder.hh" 4910747SChris.Emmons@arm.com#include "arch/utility.hh" 509520SAndreas.Sandberg@ARM.com#include "base/statistics.hh" 519520SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 529520SAndreas.Sandberg@ARM.com#include "cpu/pc_event.hh" 539520SAndreas.Sandberg@ARM.com#include "cpu/timebuf.hh" 549665Sandreas.hansson@arm.com#include "cpu/translation.hh" 559665Sandreas.hansson@arm.com#include "mem/packet.hh" 569665Sandreas.hansson@arm.com#include "mem/port.hh" 579665Sandreas.hansson@arm.com#include "sim/eventq.hh" 5811238Sandreas.sandberg@arm.com 5911238Sandreas.sandberg@arm.comstruct DerivO3CPUParams; 6011238Sandreas.sandberg@arm.com 6111238Sandreas.sandberg@arm.com/** 6211688Sandreas.hansson@arm.com * DefaultFetch class handles both single threaded and SMT fetch. Its 6311688Sandreas.hansson@arm.com * width is specified by the parameters; each cycle it tries to fetch 6411688Sandreas.hansson@arm.com * that many instructions. It supports using a branch predictor to 6511688Sandreas.hansson@arm.com * predict direction and targets. 668920Snilay@cs.wisc.edu * It supports the idling functionality of the CPU by indicating to 679827Sakash.bagdia@arm.com * the CPU when it is active and inactive. 689827Sakash.bagdia@arm.com */ 699827Sakash.bagdia@arm.comtemplate <class Impl> 709827Sakash.bagdia@arm.comclass DefaultFetch 719790Sakash.bagdia@arm.com{ 729790Sakash.bagdia@arm.com public: 739790Sakash.bagdia@arm.com /** Typedefs from Impl. */ 749790Sakash.bagdia@arm.com typedef typename Impl::CPUPol CPUPol; 7511688Sandreas.hansson@arm.com typedef typename Impl::DynInst DynInst; 7611688Sandreas.hansson@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 7711688Sandreas.hansson@arm.com typedef typename Impl::O3CPU O3CPU; 7811688Sandreas.hansson@arm.com 7911688Sandreas.hansson@arm.com /** Typedefs from the CPU policy. */ 8011688Sandreas.hansson@arm.com typedef typename CPUPol::BPredUnit BPredUnit; 8111688Sandreas.hansson@arm.com typedef typename CPUPol::FetchStruct FetchStruct; 8211688Sandreas.hansson@arm.com typedef typename CPUPol::TimeStruct TimeStruct; 8311688Sandreas.hansson@arm.com 8411688Sandreas.hansson@arm.com /** Typedefs from ISA. */ 8511688Sandreas.hansson@arm.com typedef TheISA::MachInst MachInst; 8611688Sandreas.hansson@arm.com typedef TheISA::ExtMachInst ExtMachInst; 8711688Sandreas.hansson@arm.com 8811688Sandreas.hansson@arm.com class FetchTranslation : public BaseTLB::Translation 8911688Sandreas.hansson@arm.com { 9011688Sandreas.hansson@arm.com protected: 9111688Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 9211688Sandreas.hansson@arm.com 9311688Sandreas.hansson@arm.com public: 9411688Sandreas.hansson@arm.com FetchTranslation(DefaultFetch<Impl> *_fetch) 9511688Sandreas.hansson@arm.com : fetch(_fetch) 9611688Sandreas.hansson@arm.com {} 9711688Sandreas.hansson@arm.com 9811688Sandreas.hansson@arm.com void 9911688Sandreas.hansson@arm.com markDelayed() 10011688Sandreas.hansson@arm.com {} 10111688Sandreas.hansson@arm.com 10211688Sandreas.hansson@arm.com void 10311688Sandreas.hansson@arm.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 10411688Sandreas.hansson@arm.com BaseTLB::Mode mode) 10511688Sandreas.hansson@arm.com { 10611688Sandreas.hansson@arm.com assert(mode == BaseTLB::Execute); 10711688Sandreas.hansson@arm.com fetch->finishTranslation(fault, req); 10811688Sandreas.hansson@arm.com delete this; 10911688Sandreas.hansson@arm.com } 11011688Sandreas.hansson@arm.com }; 11111688Sandreas.hansson@arm.com 11211688Sandreas.hansson@arm.com private: 11311688Sandreas.hansson@arm.com /* Event to delay delivery of a fetch translation result in case of 11411688Sandreas.hansson@arm.com * a fault and the nop to carry the fault cannot be generated 11511688Sandreas.hansson@arm.com * immediately */ 11611688Sandreas.hansson@arm.com class FinishTranslationEvent : public Event 11711688Sandreas.hansson@arm.com { 11811688Sandreas.hansson@arm.com private: 11911688Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 12011688Sandreas.hansson@arm.com Fault fault; 12111688Sandreas.hansson@arm.com RequestPtr req; 12211688Sandreas.hansson@arm.com 12311688Sandreas.hansson@arm.com public: 12411688Sandreas.hansson@arm.com FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 12511688Sandreas.hansson@arm.com : fetch(_fetch) 12611688Sandreas.hansson@arm.com {} 12711688Sandreas.hansson@arm.com 12811688Sandreas.hansson@arm.com void setFault(Fault _fault) 12911688Sandreas.hansson@arm.com { 13011688Sandreas.hansson@arm.com fault = _fault; 13111688Sandreas.hansson@arm.com } 13211688Sandreas.hansson@arm.com 13311688Sandreas.hansson@arm.com void setReq(RequestPtr _req) 13411688Sandreas.hansson@arm.com { 13511688Sandreas.hansson@arm.com req = _req; 13611688Sandreas.hansson@arm.com } 13711688Sandreas.hansson@arm.com 13811688Sandreas.hansson@arm.com /** Process the delayed finish translation */ 13911688Sandreas.hansson@arm.com void process() 14011688Sandreas.hansson@arm.com { 14111688Sandreas.hansson@arm.com assert(fetch->numInst < fetch->fetchWidth); 1429789Sakash.bagdia@arm.com fetch->finishTranslation(fault, req); 1439789Sakash.bagdia@arm.com } 1449789Sakash.bagdia@arm.com 1459800Snilay@cs.wisc.edu const char *description() const 1469800Snilay@cs.wisc.edu { 1479800Snilay@cs.wisc.edu return "FullO3CPU FetchFinishTranslation"; 1489800Snilay@cs.wisc.edu } 1499800Snilay@cs.wisc.edu }; 15011251Sradhika.jagtap@ARM.com 15111251Sradhika.jagtap@ARM.com public: 15211251Sradhika.jagtap@ARM.com /** Overall fetch status. Used to determine if the CPU can 15311251Sradhika.jagtap@ARM.com * deschedule itsef due to a lack of activity. 15411251Sradhika.jagtap@ARM.com */ 15511251Sradhika.jagtap@ARM.com enum FetchStatus { 15611251Sradhika.jagtap@ARM.com Active, 15711251Sradhika.jagtap@ARM.com Inactive 15811251Sradhika.jagtap@ARM.com }; 15911251Sradhika.jagtap@ARM.com 16011251Sradhika.jagtap@ARM.com /** Individual thread status. */ 16111251Sradhika.jagtap@ARM.com enum ThreadStatus { 16211251Sradhika.jagtap@ARM.com Running, 1639800Snilay@cs.wisc.edu Idle, 16410037SARM gem5 Developers Squashing, 16510037SARM gem5 Developers Blocked, 16610037SARM gem5 Developers Fetching, 1679800Snilay@cs.wisc.edu TrapPending, 1689800Snilay@cs.wisc.edu QuiescePending, 16911626Smichael.lebeane@amd.com SwitchOut, 17011626Smichael.lebeane@amd.com ItlbWait, 17111626Smichael.lebeane@amd.com IcacheWaitResponse, 17211703Smichael.lebeane@amd.com IcacheWaitRetry, 17311703Smichael.lebeane@amd.com IcacheAccessComplete, 17411626Smichael.lebeane@amd.com NoGoodAddr 17511626Smichael.lebeane@amd.com }; 17611626Smichael.lebeane@amd.com 17711626Smichael.lebeane@amd.com /** Fetching Policy, Add new policies here.*/ 17811626Smichael.lebeane@amd.com enum FetchPriority { 17911626Smichael.lebeane@amd.com SingleThread, 18011626Smichael.lebeane@amd.com RoundRobin, 18111626Smichael.lebeane@amd.com Branch, 18211626Smichael.lebeane@amd.com IQ, 18311626Smichael.lebeane@amd.com LSQ 18411626Smichael.lebeane@amd.com }; 18511626Smichael.lebeane@amd.com 18611626Smichael.lebeane@amd.com private: 18711626Smichael.lebeane@amd.com /** Fetch status. */ 18811626Smichael.lebeane@amd.com FetchStatus _status; 18911626Smichael.lebeane@amd.com 19011626Smichael.lebeane@amd.com /** Per-thread status. */ 19111626Smichael.lebeane@amd.com ThreadStatus fetchStatus[Impl::MaxThreads]; 19211626Smichael.lebeane@amd.com 19311626Smichael.lebeane@amd.com /** Fetch policy. */ 19411626Smichael.lebeane@amd.com FetchPriority fetchPolicy; 19511626Smichael.lebeane@amd.com 19611626Smichael.lebeane@amd.com /** List that has the threads organized by priority. */ 19711626Smichael.lebeane@amd.com std::list<ThreadID> priorityList; 19811626Smichael.lebeane@amd.com 19911626Smichael.lebeane@amd.com public: 20011626Smichael.lebeane@amd.com /** DefaultFetch constructor. */ 20111626Smichael.lebeane@amd.com DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 20211626Smichael.lebeane@amd.com 20311626Smichael.lebeane@amd.com /** Returns the name of fetch. */ 2048920Snilay@cs.wisc.edu std::string name() const; 2058920Snilay@cs.wisc.edu 2068920Snilay@cs.wisc.edu /** Registers statistics. */ 2078920Snilay@cs.wisc.edu void regStats(); 2088920Snilay@cs.wisc.edu 2098920Snilay@cs.wisc.edu /** Sets the main backwards communication time buffer pointer. */ 21010159Sgedare@rtems.org void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 21110159Sgedare@rtems.org 2128920Snilay@cs.wisc.edu /** Sets pointer to list of active threads. */ 2138920Snilay@cs.wisc.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 2148920Snilay@cs.wisc.edu 2158920Snilay@cs.wisc.edu /** Sets pointer to time buffer used to communicate to the next stage. */ 2168920Snilay@cs.wisc.edu void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2178920Snilay@cs.wisc.edu 2188920Snilay@cs.wisc.edu /** Initialize stage. */ 2198920Snilay@cs.wisc.edu void initStage(); 2208920Snilay@cs.wisc.edu 22110757SCurtis.Dunham@arm.com /** Tells the fetch stage that the Icache is set. */ 22210757SCurtis.Dunham@arm.com void setIcache(); 22310757SCurtis.Dunham@arm.com 2246776SBrad.Beckmann@amd.com /** Handles retrying the fetch access. */ 2259800Snilay@cs.wisc.edu void recvRetry(); 2269800Snilay@cs.wisc.edu 2279800Snilay@cs.wisc.edu /** Processes cache completion event. */ 2289800Snilay@cs.wisc.edu void processCacheCompletion(PacketPtr pkt); 2299800Snilay@cs.wisc.edu 23010608Sdam.sunwoo@arm.com /** Begins the drain of the fetch stage. */ 23110608Sdam.sunwoo@arm.com bool drain(); 23210608Sdam.sunwoo@arm.com 23310608Sdam.sunwoo@arm.com /** Resumes execution after a drain. */ 23410608Sdam.sunwoo@arm.com void resume(); 2359800Snilay@cs.wisc.edu 2368920Snilay@cs.wisc.edu /** Tells fetch stage to prepare to be switched out. */ 2378920Snilay@cs.wisc.edu void switchOut(); 2388920Snilay@cs.wisc.edu 2398920Snilay@cs.wisc.edu /** Takes over from another CPU's thread. */ 2409357Sandreas.hansson@arm.com void takeOverFrom(); 2418920Snilay@cs.wisc.edu 2428920Snilay@cs.wisc.edu /** Checks if the fetch stage is switched out. */ 2438920Snilay@cs.wisc.edu bool isSwitchedOut() { return switchedOut; } 2448920Snilay@cs.wisc.edu 2458920Snilay@cs.wisc.edu /** Tells fetch to wake up from a quiesce instruction. */ 2468920Snilay@cs.wisc.edu void wakeFromQuiesce(); 2478920Snilay@cs.wisc.edu 2488920Snilay@cs.wisc.edu private: 2498920Snilay@cs.wisc.edu /** Changes the status of this stage to active, and indicates this 2508920Snilay@cs.wisc.edu * to the CPU. 2518920Snilay@cs.wisc.edu */ 2528920Snilay@cs.wisc.edu inline void switchToActive(); 2538920Snilay@cs.wisc.edu 2548920Snilay@cs.wisc.edu /** Changes the status of this stage to inactive, and indicates 2558920Snilay@cs.wisc.edu * this to the CPU. 2569736Sandreas@sandberg.pp.se */ 2578920Snilay@cs.wisc.edu inline void switchToInactive(); 2583395Shsul@eecs.umich.edu 2595361Srstrong@cs.ucsd.edu /** 2608920Snilay@cs.wisc.edu * Looks up in the branch predictor to see if the next PC should be 2618920Snilay@cs.wisc.edu * either next PC+=MachInst or a branch target. 2628920Snilay@cs.wisc.edu * @param next_PC Next PC variable passed in by reference. It is 2639151Satgutier@umich.edu * expected to be set to the current PC; it will be updated with what 2649151Satgutier@umich.edu * the next PC will be. 2659151Satgutier@umich.edu * @param next_NPC Used for ISAs which use delay slots. 2669151Satgutier@umich.edu * @return Whether or not a branch was predicted as taken. 2679151Satgutier@umich.edu */ 2689151Satgutier@umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2699562Ssaidi@eecs.umich.edu 2708920Snilay@cs.wisc.edu /** 2718920Snilay@cs.wisc.edu * Fetches the cache line that contains fetch_PC. Returns any 2728920Snilay@cs.wisc.edu * fault that happened. Puts the data into the class variable 2738920Snilay@cs.wisc.edu * cacheData. 2748920Snilay@cs.wisc.edu * @param vaddr The memory address that is being fetched from. 2758920Snilay@cs.wisc.edu * @param ret_fault The fault reference that will be set to the result of 2768920Snilay@cs.wisc.edu * the icache access. 2778920Snilay@cs.wisc.edu * @param tid Thread id. 2788920Snilay@cs.wisc.edu * @param pc The actual PC of the current instruction. 2798920Snilay@cs.wisc.edu * @return Any fault that occured. 2808920Snilay@cs.wisc.edu */ 2818920Snilay@cs.wisc.edu bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 2828920Snilay@cs.wisc.edu void finishTranslation(Fault fault, RequestPtr mem_req); 2838920Snilay@cs.wisc.edu 2848920Snilay@cs.wisc.edu 2858920Snilay@cs.wisc.edu /** Check if an interrupt is pending and that we need to handle 2868920Snilay@cs.wisc.edu */ 28710037SARM gem5 Developers bool 28810037SARM gem5 Developers checkInterrupt(Addr pc) 28910037SARM gem5 Developers { 29010037SARM gem5 Developers return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 29110037SARM gem5 Developers } 29210037SARM gem5 Developers 29310037SARM gem5 Developers /** Squashes a specific thread and resets the PC. */ 29410037SARM gem5 Developers inline void doSquash(const TheISA::PCState &newPC, 2958920Snilay@cs.wisc.edu const DynInstPtr squashInst, ThreadID tid); 2968920Snilay@cs.wisc.edu 2978920Snilay@cs.wisc.edu /** Squashes a specific thread and resets the PC. Also tells the CPU to 2988920Snilay@cs.wisc.edu * remove any instructions between fetch and decode that should be sqaushed. 2998920Snilay@cs.wisc.edu */ 3008920Snilay@cs.wisc.edu void squashFromDecode(const TheISA::PCState &newPC, 3018920Snilay@cs.wisc.edu const DynInstPtr squashInst, 3028920Snilay@cs.wisc.edu const InstSeqNum seq_num, ThreadID tid); 30310803Sbrandon.potter@amd.com 30410803Sbrandon.potter@amd.com /** Checks if a thread is stalled. */ 3058920Snilay@cs.wisc.edu bool checkStall(ThreadID tid) const; 3068920Snilay@cs.wisc.edu 3078920Snilay@cs.wisc.edu /** Updates overall fetch stage status; to be called at the end of each 3088920Snilay@cs.wisc.edu * cycle. */ 3098920Snilay@cs.wisc.edu FetchStatus updateFetchStatus(); 3108920Snilay@cs.wisc.edu 3118920Snilay@cs.wisc.edu public: 3128920Snilay@cs.wisc.edu /** Squashes a specific thread and resets the PC. Also tells the CPU to 31311688Sandreas.hansson@arm.com * remove any instructions that are not in the ROB. The source of this 31411688Sandreas.hansson@arm.com * squash should be the commit stage. 3158920Snilay@cs.wisc.edu */ 3168920Snilay@cs.wisc.edu void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3178920Snilay@cs.wisc.edu DynInstPtr squashInst, ThreadID tid); 3188920Snilay@cs.wisc.edu 3198920Snilay@cs.wisc.edu /** Ticks the fetch stage, processing all inputs signals and fetching 3208920Snilay@cs.wisc.edu * as many instructions as possible. 32110747SChris.Emmons@arm.com */ 32210747SChris.Emmons@arm.com void tick(); 32310747SChris.Emmons@arm.com 3248920Snilay@cs.wisc.edu /** Checks all input signals and updates the status as necessary. 3258920Snilay@cs.wisc.edu * @return: Returns if the status has changed due to input signals. 3268920Snilay@cs.wisc.edu */ 3278920Snilay@cs.wisc.edu bool checkSignalsAndUpdate(ThreadID tid); 3288920Snilay@cs.wisc.edu 3298920Snilay@cs.wisc.edu /** Does the actual fetching of instructions and passing them on to the 3308920Snilay@cs.wisc.edu * next stage. 3318920Snilay@cs.wisc.edu * @param status_change fetch() sets this variable if there was a status 33211238Sandreas.sandberg@arm.com * change (ie switching to IcacheMissStall). 33311238Sandreas.sandberg@arm.com */ 33411238Sandreas.sandberg@arm.com void fetch(bool &status_change); 3358920Snilay@cs.wisc.edu 33611238Sandreas.sandberg@arm.com /** Align a PC to the start of an I-cache block. */ 33711238Sandreas.sandberg@arm.com Addr icacheBlockAlignPC(Addr addr) 3389539Satgutier@umich.edu { 3399539Satgutier@umich.edu return (addr & ~(cacheBlkMask)); 3409539Satgutier@umich.edu } 3419935Sdam.sunwoo@arm.com 3429935Sdam.sunwoo@arm.com /** The decoder. */ 3439935Sdam.sunwoo@arm.com TheISA::Decoder decoder; 3449935Sdam.sunwoo@arm.com 3458920Snilay@cs.wisc.edu private: 3468920Snilay@cs.wisc.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3478920Snilay@cs.wisc.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3488920Snilay@cs.wisc.edu TheISA::PCState nextPC, bool trace); 3498920Snilay@cs.wisc.edu 3508920Snilay@cs.wisc.edu /** Returns the appropriate thread to fetch, given the fetch policy. */ 3518920Snilay@cs.wisc.edu ThreadID getFetchingThread(FetchPriority &fetch_priority); 3528920Snilay@cs.wisc.edu 3538920Snilay@cs.wisc.edu /** Returns the appropriate thread to fetch using a round robin policy. */ 3548920Snilay@cs.wisc.edu ThreadID roundRobin(); 3558920Snilay@cs.wisc.edu 3568920Snilay@cs.wisc.edu /** Returns the appropriate thread to fetch using the IQ count policy. */ 3578956Sjayneel@cs.wisc.edu ThreadID iqCount(); 3588956Sjayneel@cs.wisc.edu 3598956Sjayneel@cs.wisc.edu /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3608956Sjayneel@cs.wisc.edu ThreadID lsqCount(); 36110697SCurtis.Dunham@arm.com 36210697SCurtis.Dunham@arm.com /** Returns the appropriate thread to fetch using the branch count 36310594Sgabeblack@google.com * policy. */ 36410594Sgabeblack@google.com ThreadID branchCount(); 36510594Sgabeblack@google.com 36610594Sgabeblack@google.com /** Pipeline the next I-cache access to the current one. */ 36710594Sgabeblack@google.com void pipelineIcacheAccesses(ThreadID tid); 36810594Sgabeblack@google.com 36910594Sgabeblack@google.com /** Profile the reasons of fetch stall. */ 37010594Sgabeblack@google.com void profileStall(ThreadID tid); 371 372 private: 373 /** Pointer to the O3CPU. */ 374 O3CPU *cpu; 375 376 /** Time buffer interface. */ 377 TimeBuffer<TimeStruct> *timeBuffer; 378 379 /** Wire to get decode's information from backwards time buffer. */ 380 typename TimeBuffer<TimeStruct>::wire fromDecode; 381 382 /** Wire to get rename's information from backwards time buffer. */ 383 typename TimeBuffer<TimeStruct>::wire fromRename; 384 385 /** Wire to get iew's information from backwards time buffer. */ 386 typename TimeBuffer<TimeStruct>::wire fromIEW; 387 388 /** Wire to get commit's information from backwards time buffer. */ 389 typename TimeBuffer<TimeStruct>::wire fromCommit; 390 391 /** Internal fetch instruction queue. */ 392 TimeBuffer<FetchStruct> *fetchQueue; 393 394 //Might be annoying how this name is different than the queue. 395 /** Wire used to write any information heading to decode. */ 396 typename TimeBuffer<FetchStruct>::wire toDecode; 397 398 /** BPredUnit. */ 399 BPredUnit branchPred; 400 401 /** Predecoder. */ 402 TheISA::Predecoder predecoder; 403 404 TheISA::PCState pc[Impl::MaxThreads]; 405 406 Addr fetchOffset[Impl::MaxThreads]; 407 408 StaticInstPtr macroop[Impl::MaxThreads]; 409 410 /** Can the fetch stage redirect from an interrupt on this instruction? */ 411 bool delayedCommit[Impl::MaxThreads]; 412 413 /** Memory request used to access cache. */ 414 RequestPtr memReq[Impl::MaxThreads]; 415 416 /** Variable that tracks if fetch has written to the time buffer this 417 * cycle. Used to tell CPU if there is activity this cycle. 418 */ 419 bool wroteToTimeBuffer; 420 421 /** Tracks how many instructions has been fetched this cycle. */ 422 int numInst; 423 424 /** Source of possible stalls. */ 425 struct Stalls { 426 bool decode; 427 bool rename; 428 bool iew; 429 bool commit; 430 }; 431 432 /** Tracks which stages are telling fetch to stall. */ 433 Stalls stalls[Impl::MaxThreads]; 434 435 /** Decode to fetch delay, in ticks. */ 436 unsigned decodeToFetchDelay; 437 438 /** Rename to fetch delay, in ticks. */ 439 unsigned renameToFetchDelay; 440 441 /** IEW to fetch delay, in ticks. */ 442 unsigned iewToFetchDelay; 443 444 /** Commit to fetch delay, in ticks. */ 445 unsigned commitToFetchDelay; 446 447 /** The width of fetch in instructions. */ 448 unsigned fetchWidth; 449 450 /** Is the cache blocked? If so no threads can access it. */ 451 bool cacheBlocked; 452 453 /** The packet that is waiting to be retried. */ 454 PacketPtr retryPkt; 455 456 /** The thread that is waiting on the cache to tell fetch to retry. */ 457 ThreadID retryTid; 458 459 /** Cache block size. */ 460 int cacheBlkSize; 461 462 /** Mask to get a cache block's address. */ 463 Addr cacheBlkMask; 464 465 /** The cache line being fetched. */ 466 uint8_t *cacheData[Impl::MaxThreads]; 467 468 /** The PC of the cacheline that has been loaded. */ 469 Addr cacheDataPC[Impl::MaxThreads]; 470 471 /** Whether or not the cache data is valid. */ 472 bool cacheDataValid[Impl::MaxThreads]; 473 474 /** Size of instructions. */ 475 int instSize; 476 477 /** Icache stall statistics. */ 478 Counter lastIcacheStall[Impl::MaxThreads]; 479 480 /** List of Active Threads */ 481 std::list<ThreadID> *activeThreads; 482 483 /** Number of threads. */ 484 ThreadID numThreads; 485 486 /** Number of threads that are actively fetching. */ 487 ThreadID numFetchingThreads; 488 489 /** Thread ID being fetched. */ 490 ThreadID threadFetched; 491 492 /** Checks if there is an interrupt pending. If there is, fetch 493 * must stop once it is not fetching PAL instructions. 494 */ 495 bool interruptPending; 496 497 /** Is there a drain pending. */ 498 bool drainPending; 499 500 /** Records if fetch is switched out. */ 501 bool switchedOut; 502 503 /** Set to true if a pipelined I-cache request should be issued. */ 504 bool issuePipelinedIfetch[Impl::MaxThreads]; 505 506 /** Event used to delay fault generation of translation faults */ 507 FinishTranslationEvent finishTranslationEvent; 508 509 // @todo: Consider making these vectors and tracking on a per thread basis. 510 /** Stat for total number of cycles stalled due to an icache miss. */ 511 Stats::Scalar icacheStallCycles; 512 /** Stat for total number of fetched instructions. */ 513 Stats::Scalar fetchedInsts; 514 /** Total number of fetched branches. */ 515 Stats::Scalar fetchedBranches; 516 /** Stat for total number of predicted branches. */ 517 Stats::Scalar predictedBranches; 518 /** Stat for total number of cycles spent fetching. */ 519 Stats::Scalar fetchCycles; 520 /** Stat for total number of cycles spent squashing. */ 521 Stats::Scalar fetchSquashCycles; 522 /** Stat for total number of cycles spent waiting for translation */ 523 Stats::Scalar fetchTlbCycles; 524 /** Stat for total number of cycles spent blocked due to other stages in 525 * the pipeline. 526 */ 527 Stats::Scalar fetchIdleCycles; 528 /** Total number of cycles spent blocked. */ 529 Stats::Scalar fetchBlockedCycles; 530 /** Total number of cycles spent in any other state. */ 531 Stats::Scalar fetchMiscStallCycles; 532 /** Total number of cycles spent in waiting for drains. */ 533 Stats::Scalar fetchPendingDrainCycles; 534 /** Total number of stall cycles caused by no active threads to run. */ 535 Stats::Scalar fetchNoActiveThreadStallCycles; 536 /** Total number of stall cycles caused by pending traps. */ 537 Stats::Scalar fetchPendingTrapStallCycles; 538 /** Total number of stall cycles caused by pending quiesce instructions. */ 539 Stats::Scalar fetchPendingQuiesceStallCycles; 540 /** Total number of stall cycles caused by I-cache wait retrys. */ 541 Stats::Scalar fetchIcacheWaitRetryStallCycles; 542 /** Stat for total number of fetched cache lines. */ 543 Stats::Scalar fetchedCacheLines; 544 /** Total number of outstanding icache accesses that were dropped 545 * due to a squash. 546 */ 547 Stats::Scalar fetchIcacheSquashes; 548 /** Total number of outstanding tlb accesses that were dropped 549 * due to a squash. 550 */ 551 Stats::Scalar fetchTlbSquashes; 552 /** Distribution of number of instructions fetched each cycle. */ 553 Stats::Distribution fetchNisnDist; 554 /** Rate of how often fetch was idle. */ 555 Stats::Formula idleRate; 556 /** Number of branch fetches per cycle. */ 557 Stats::Formula branchRate; 558 /** Number of instruction fetched per cycle. */ 559 Stats::Formula fetchRate; 560}; 561 562#endif //__CPU_O3_FETCH_HH__ 563