fetch.hh revision 8138
11689SN/A/* 27849SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37849SAli.Saidi@ARM.com * All rights reserved 47849SAli.Saidi@ARM.com * 57849SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67849SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77849SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87849SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97849SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107849SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117849SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127849SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137849SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_FETCH_HH__ 452292SN/A#define __CPU_O3_FETCH_HH__ 461060SN/A 472669Sktlim@umich.edu#include "arch/utility.hh" 484182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 491461SN/A#include "base/statistics.hh" 507813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 521060SN/A#include "cpu/pc_event.hh" 537849SAli.Saidi@ARM.com#include "cpu/translation.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 552669Sktlim@umich.edu#include "mem/port.hh" 561461SN/A#include "sim/eventq.hh" 571060SN/A 585529Snate@binkert.orgclass DerivO3CPUParams; 595529Snate@binkert.org 601060SN/A/** 612329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 622329SN/A * width is specified by the parameters; each cycle it tries to fetch 632329SN/A * that many instructions. It supports using a branch predictor to 642329SN/A * predict direction and targets. 652348SN/A * It supports the idling functionality of the CPU by indicating to 662329SN/A * the CPU when it is active and inactive. 671060SN/A */ 681060SN/Atemplate <class Impl> 692292SN/Aclass DefaultFetch 701060SN/A{ 711060SN/A public: 721060SN/A /** Typedefs from Impl. */ 731061SN/A typedef typename Impl::CPUPol CPUPol; 741060SN/A typedef typename Impl::DynInst DynInst; 751061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 762733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 771060SN/A 782292SN/A /** Typedefs from the CPU policy. */ 791061SN/A typedef typename CPUPol::BPredUnit BPredUnit; 801061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 811061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 821060SN/A 831060SN/A /** Typedefs from ISA. */ 842107SN/A typedef TheISA::MachInst MachInst; 852292SN/A typedef TheISA::ExtMachInst ExtMachInst; 862632Sstever@eecs.umich.edu 872698Sktlim@umich.edu /** IcachePort class for DefaultFetch. Handles doing the 882698Sktlim@umich.edu * communication with the cache/memory. 892698Sktlim@umich.edu */ 902669Sktlim@umich.edu class IcachePort : public Port 912669Sktlim@umich.edu { 922669Sktlim@umich.edu protected: 932698Sktlim@umich.edu /** Pointer to fetch. */ 942669Sktlim@umich.edu DefaultFetch<Impl> *fetch; 952669Sktlim@umich.edu 962669Sktlim@umich.edu public: 972698Sktlim@umich.edu /** Default constructor. */ 985494Sstever@gmail.com IcachePort(DefaultFetch<Impl> *_fetch) 995606Snate@binkert.org : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch) 1002669Sktlim@umich.edu { } 1012669Sktlim@umich.edu 1023647Srdreslin@umich.edu bool snoopRangeSent; 1033647Srdreslin@umich.edu 1044302Sktlim@umich.edu virtual void setPeer(Port *port); 1054302Sktlim@umich.edu 1062669Sktlim@umich.edu protected: 1072698Sktlim@umich.edu /** Atomic version of receive. Panics. */ 1082669Sktlim@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1092669Sktlim@umich.edu 1102698Sktlim@umich.edu /** Functional version of receive. Panics. */ 1112669Sktlim@umich.edu virtual void recvFunctional(PacketPtr pkt); 1122669Sktlim@umich.edu 1132698Sktlim@umich.edu /** Receives status change. Other than range changing, panics. */ 1142669Sktlim@umich.edu virtual void recvStatusChange(Status status); 1152669Sktlim@umich.edu 1162698Sktlim@umich.edu /** Returns the address ranges of this device. */ 1172669Sktlim@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1184475Sstever@eecs.umich.edu bool &snoop) 1194475Sstever@eecs.umich.edu { resp.clear(); snoop = true; } 1202669Sktlim@umich.edu 1212698Sktlim@umich.edu /** Timing version of receive. Handles setting fetch to the 1222698Sktlim@umich.edu * proper status to start fetching. */ 1232669Sktlim@umich.edu virtual bool recvTiming(PacketPtr pkt); 1242669Sktlim@umich.edu 1252698Sktlim@umich.edu /** Handles doing a retry of a failed fetch. */ 1262669Sktlim@umich.edu virtual void recvRetry(); 1272669Sktlim@umich.edu }; 1281060SN/A 1297849SAli.Saidi@ARM.com class FetchTranslation : public BaseTLB::Translation 1307849SAli.Saidi@ARM.com { 1317849SAli.Saidi@ARM.com protected: 1327849SAli.Saidi@ARM.com DefaultFetch<Impl> *fetch; 1337849SAli.Saidi@ARM.com 1347849SAli.Saidi@ARM.com public: 1357849SAli.Saidi@ARM.com FetchTranslation(DefaultFetch<Impl> *_fetch) 1367849SAli.Saidi@ARM.com : fetch(_fetch) 1377849SAli.Saidi@ARM.com {} 1387849SAli.Saidi@ARM.com 1397849SAli.Saidi@ARM.com void 1407944SGiacomo.Gabrielli@arm.com markDelayed() 1417944SGiacomo.Gabrielli@arm.com {} 1427944SGiacomo.Gabrielli@arm.com 1437944SGiacomo.Gabrielli@arm.com void 1447849SAli.Saidi@ARM.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 1457849SAli.Saidi@ARM.com BaseTLB::Mode mode) 1467849SAli.Saidi@ARM.com { 1477849SAli.Saidi@ARM.com assert(mode == BaseTLB::Execute); 1487849SAli.Saidi@ARM.com fetch->finishTranslation(fault, req); 1497849SAli.Saidi@ARM.com delete this; 1507849SAli.Saidi@ARM.com } 1517849SAli.Saidi@ARM.com }; 1522935Sksewell@umich.edu 1531060SN/A public: 1542329SN/A /** Overall fetch status. Used to determine if the CPU can 1552329SN/A * deschedule itsef due to a lack of activity. 1562292SN/A */ 1572292SN/A enum FetchStatus { 1582292SN/A Active, 1592292SN/A Inactive 1602292SN/A }; 1612292SN/A 1622292SN/A /** Individual thread status. */ 1632292SN/A enum ThreadStatus { 1641060SN/A Running, 1651060SN/A Idle, 1661060SN/A Squashing, 1671060SN/A Blocked, 1682292SN/A Fetching, 1692292SN/A TrapPending, 1702292SN/A QuiescePending, 1712307SN/A SwitchOut, 1727849SAli.Saidi@ARM.com ItlbWait, 1732669Sktlim@umich.edu IcacheWaitResponse, 1742696Sktlim@umich.edu IcacheWaitRetry, 1752669Sktlim@umich.edu IcacheAccessComplete 1761060SN/A }; 1771060SN/A 1782292SN/A /** Fetching Policy, Add new policies here.*/ 1792292SN/A enum FetchPriority { 1802292SN/A SingleThread, 1812292SN/A RoundRobin, 1822292SN/A Branch, 1832292SN/A IQ, 1842292SN/A LSQ 1852292SN/A }; 1861060SN/A 1872292SN/A private: 1882292SN/A /** Fetch status. */ 1892292SN/A FetchStatus _status; 1902292SN/A 1912292SN/A /** Per-thread status. */ 1922292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1932292SN/A 1942292SN/A /** Fetch policy. */ 1952292SN/A FetchPriority fetchPolicy; 1962292SN/A 1972292SN/A /** List that has the threads organized by priority. */ 1986221Snate@binkert.org std::list<ThreadID> priorityList; 1991060SN/A 2001060SN/A public: 2012292SN/A /** DefaultFetch constructor. */ 2025529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2031684SN/A 2042292SN/A /** Returns the name of fetch. */ 2052292SN/A std::string name() const; 2061684SN/A 2072292SN/A /** Registers statistics. */ 2081062SN/A void regStats(); 2091062SN/A 2102871Sktlim@umich.edu /** Returns the icache port. */ 2112871Sktlim@umich.edu Port *getIcachePort() { return icachePort; } 2122871Sktlim@umich.edu 2132292SN/A /** Sets the main backwards communication time buffer pointer. */ 2141060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2151060SN/A 2162292SN/A /** Sets pointer to list of active threads. */ 2176221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 2182292SN/A 2192292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 2201060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2211060SN/A 2222292SN/A /** Initialize stage. */ 2232292SN/A void initStage(); 2242292SN/A 2254302Sktlim@umich.edu /** Tells the fetch stage that the Icache is set. */ 2264302Sktlim@umich.edu void setIcache(); 2274302Sktlim@umich.edu 2282292SN/A /** Processes cache completion event. */ 2292669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 2302292SN/A 2312843Sktlim@umich.edu /** Begins the drain of the fetch stage. */ 2322863Sktlim@umich.edu bool drain(); 2332843Sktlim@umich.edu 2342843Sktlim@umich.edu /** Resumes execution after a drain. */ 2352843Sktlim@umich.edu void resume(); 2362843Sktlim@umich.edu 2372843Sktlim@umich.edu /** Tells fetch stage to prepare to be switched out. */ 2382307SN/A void switchOut(); 2392307SN/A 2402348SN/A /** Takes over from another CPU's thread. */ 2412307SN/A void takeOverFrom(); 2422307SN/A 2432348SN/A /** Checks if the fetch stage is switched out. */ 2442307SN/A bool isSwitchedOut() { return switchedOut; } 2452307SN/A 2462348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2472292SN/A void wakeFromQuiesce(); 2481060SN/A 2491061SN/A private: 2502329SN/A /** Changes the status of this stage to active, and indicates this 2512329SN/A * to the CPU. 2522292SN/A */ 2532292SN/A inline void switchToActive(); 2542292SN/A 2552329SN/A /** Changes the status of this stage to inactive, and indicates 2562329SN/A * this to the CPU. 2572292SN/A */ 2582292SN/A inline void switchToInactive(); 2592292SN/A 2601061SN/A /** 2611061SN/A * Looks up in the branch predictor to see if the next PC should be 2621061SN/A * either next PC+=MachInst or a branch target. 2631763SN/A * @param next_PC Next PC variable passed in by reference. It is 2641061SN/A * expected to be set to the current PC; it will be updated with what 2651061SN/A * the next PC will be. 2662935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 2671061SN/A * @return Whether or not a branch was predicted as taken. 2681061SN/A */ 2697720Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2701062SN/A 2711062SN/A /** 2721062SN/A * Fetches the cache line that contains fetch_PC. Returns any 2731062SN/A * fault that happened. Puts the data into the class variable 2741062SN/A * cacheData. 2757764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 2762292SN/A * @param ret_fault The fault reference that will be set to the result of 2772292SN/A * the icache access. 2782292SN/A * @param tid Thread id. 2797764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 2801062SN/A * @return Any fault that occured. 2811062SN/A */ 2827849SAli.Saidi@ARM.com bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 2837849SAli.Saidi@ARM.com void finishTranslation(Fault fault, RequestPtr mem_req); 2841062SN/A 2857847Sminkyu.jeong@arm.com 2867847Sminkyu.jeong@arm.com /** Check if an interrupt is pending and that we need to handle 2877847Sminkyu.jeong@arm.com */ 2887847Sminkyu.jeong@arm.com bool 2897847Sminkyu.jeong@arm.com checkInterrupt(Addr pc) 2907847Sminkyu.jeong@arm.com { 2917847Sminkyu.jeong@arm.com return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 2927847Sminkyu.jeong@arm.com } 2937847Sminkyu.jeong@arm.com 2942292SN/A /** Squashes a specific thread and resets the PC. */ 2957720Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, ThreadID tid); 2961684SN/A 2972292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2982292SN/A * remove any instructions between fetch and decode that should be sqaushed. 2992292SN/A */ 3007720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 3016221Snate@binkert.org const InstSeqNum &seq_num, ThreadID tid); 3022292SN/A 3032292SN/A /** Checks if a thread is stalled. */ 3046221Snate@binkert.org bool checkStall(ThreadID tid) const; 3052292SN/A 3062292SN/A /** Updates overall fetch stage status; to be called at the end of each 3072292SN/A * cycle. */ 3082292SN/A FetchStatus updateFetchStatus(); 3091684SN/A 3101684SN/A public: 3112292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3122292SN/A * remove any instructions that are not in the ROB. The source of this 3132292SN/A * squash should be the commit stage. 3142292SN/A */ 3158138SAli.Saidi@ARM.com void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num, 3168138SAli.Saidi@ARM.com DynInstPtr &squashInst, ThreadID tid); 3171684SN/A 3182292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 3192292SN/A * as many instructions as possible. 3202292SN/A */ 3211684SN/A void tick(); 3221684SN/A 3232292SN/A /** Checks all input signals and updates the status as necessary. 3242292SN/A * @return: Returns if the status has changed due to input signals. 3252292SN/A */ 3266221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 3271684SN/A 3282292SN/A /** Does the actual fetching of instructions and passing them on to the 3292292SN/A * next stage. 3302292SN/A * @param status_change fetch() sets this variable if there was a status 3312292SN/A * change (ie switching to IcacheMissStall). 3322292SN/A */ 3332292SN/A void fetch(bool &status_change); 3342292SN/A 3352292SN/A /** Align a PC to the start of an I-cache block. */ 3361062SN/A Addr icacheBlockAlignPC(Addr addr) 3371062SN/A { 3381062SN/A return (addr & ~(cacheBlkMask)); 3391062SN/A } 3401061SN/A 3411060SN/A private: 3427764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3437764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3447764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 3457764Sgblack@eecs.umich.edu 3462698Sktlim@umich.edu /** Handles retrying the fetch access. */ 3472696Sktlim@umich.edu void recvRetry(); 3482696Sktlim@umich.edu 3492292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3506221Snate@binkert.org ThreadID getFetchingThread(FetchPriority &fetch_priority); 3512292SN/A 3522292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3536221Snate@binkert.org ThreadID roundRobin(); 3542292SN/A 3552292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3566221Snate@binkert.org ThreadID iqCount(); 3572292SN/A 3582292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3596221Snate@binkert.org ThreadID lsqCount(); 3602292SN/A 3616221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 3626221Snate@binkert.org * policy. */ 3636221Snate@binkert.org ThreadID branchCount(); 3642292SN/A 3652292SN/A private: 3662733Sktlim@umich.edu /** Pointer to the O3CPU. */ 3672733Sktlim@umich.edu O3CPU *cpu; 3681060SN/A 3691060SN/A /** Time buffer interface. */ 3701060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3711060SN/A 3721060SN/A /** Wire to get decode's information from backwards time buffer. */ 3731060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3741060SN/A 3751060SN/A /** Wire to get rename's information from backwards time buffer. */ 3761060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3771060SN/A 3781060SN/A /** Wire to get iew's information from backwards time buffer. */ 3791060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3801060SN/A 3811060SN/A /** Wire to get commit's information from backwards time buffer. */ 3821060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3831060SN/A 3841060SN/A /** Internal fetch instruction queue. */ 3851060SN/A TimeBuffer<FetchStruct> *fetchQueue; 3861060SN/A 3871060SN/A //Might be annoying how this name is different than the queue. 3881060SN/A /** Wire used to write any information heading to decode. */ 3891060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 3901060SN/A 3911060SN/A /** Icache interface. */ 3922669Sktlim@umich.edu IcachePort *icachePort; 3931060SN/A 3941061SN/A /** BPredUnit. */ 3951061SN/A BPredUnit branchPred; 3961061SN/A 3974182Sgblack@eecs.umich.edu /** Predecoder. */ 3984182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 3994182Sgblack@eecs.umich.edu 4007720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4012292SN/A 4027764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 4037764Sgblack@eecs.umich.edu 4047764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 4057764Sgblack@eecs.umich.edu 4062678Sktlim@umich.edu /** Memory request used to access cache. */ 4072678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 4082292SN/A 4092292SN/A /** Variable that tracks if fetch has written to the time buffer this 4102292SN/A * cycle. Used to tell CPU if there is activity this cycle. 4112292SN/A */ 4122292SN/A bool wroteToTimeBuffer; 4132292SN/A 4142292SN/A /** Tracks how many instructions has been fetched this cycle. */ 4152292SN/A int numInst; 4162292SN/A 4172292SN/A /** Source of possible stalls. */ 4182292SN/A struct Stalls { 4192292SN/A bool decode; 4202292SN/A bool rename; 4212292SN/A bool iew; 4222292SN/A bool commit; 4232292SN/A }; 4242292SN/A 4252292SN/A /** Tracks which stages are telling fetch to stall. */ 4262292SN/A Stalls stalls[Impl::MaxThreads]; 4271060SN/A 4281060SN/A /** Decode to fetch delay, in ticks. */ 4291060SN/A unsigned decodeToFetchDelay; 4301060SN/A 4311060SN/A /** Rename to fetch delay, in ticks. */ 4321060SN/A unsigned renameToFetchDelay; 4331060SN/A 4341060SN/A /** IEW to fetch delay, in ticks. */ 4351060SN/A unsigned iewToFetchDelay; 4361060SN/A 4371060SN/A /** Commit to fetch delay, in ticks. */ 4381060SN/A unsigned commitToFetchDelay; 4391060SN/A 4401060SN/A /** The width of fetch in instructions. */ 4411060SN/A unsigned fetchWidth; 4421060SN/A 4432696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 4442696Sktlim@umich.edu bool cacheBlocked; 4452696Sktlim@umich.edu 4462696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 4472696Sktlim@umich.edu PacketPtr retryPkt; 4482696Sktlim@umich.edu 4492696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 4506221Snate@binkert.org ThreadID retryTid; 4512696Sktlim@umich.edu 4521060SN/A /** Cache block size. */ 4531062SN/A int cacheBlkSize; 4541060SN/A 4551060SN/A /** Mask to get a cache block's address. */ 4561062SN/A Addr cacheBlkMask; 4571060SN/A 4581062SN/A /** The cache line being fetched. */ 4592292SN/A uint8_t *cacheData[Impl::MaxThreads]; 4601060SN/A 4612893Sktlim@umich.edu /** The PC of the cacheline that has been loaded. */ 4622893Sktlim@umich.edu Addr cacheDataPC[Impl::MaxThreads]; 4632893Sktlim@umich.edu 4642906Sktlim@umich.edu /** Whether or not the cache data is valid. */ 4652906Sktlim@umich.edu bool cacheDataValid[Impl::MaxThreads]; 4662906Sktlim@umich.edu 4671060SN/A /** Size of instructions. */ 4681060SN/A int instSize; 4691060SN/A 4701060SN/A /** Icache stall statistics. */ 4712292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 4721062SN/A 4732292SN/A /** List of Active Threads */ 4746221Snate@binkert.org std::list<ThreadID> *activeThreads; 4752292SN/A 4762292SN/A /** Number of threads. */ 4776221Snate@binkert.org ThreadID numThreads; 4782292SN/A 4792292SN/A /** Number of threads that are actively fetching. */ 4806221Snate@binkert.org ThreadID numFetchingThreads; 4812292SN/A 4822292SN/A /** Thread ID being fetched. */ 4836221Snate@binkert.org ThreadID threadFetched; 4842292SN/A 4852348SN/A /** Checks if there is an interrupt pending. If there is, fetch 4862348SN/A * must stop once it is not fetching PAL instructions. 4872348SN/A */ 4882292SN/A bool interruptPending; 4892292SN/A 4902843Sktlim@umich.edu /** Is there a drain pending. */ 4912843Sktlim@umich.edu bool drainPending; 4922843Sktlim@umich.edu 4932348SN/A /** Records if fetch is switched out. */ 4942307SN/A bool switchedOut; 4952307SN/A 4962292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 4972292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 4985999Snate@binkert.org Stats::Scalar icacheStallCycles; 4992292SN/A /** Stat for total number of fetched instructions. */ 5005999Snate@binkert.org Stats::Scalar fetchedInsts; 5012727Sktlim@umich.edu /** Total number of fetched branches. */ 5025999Snate@binkert.org Stats::Scalar fetchedBranches; 5032292SN/A /** Stat for total number of predicted branches. */ 5045999Snate@binkert.org Stats::Scalar predictedBranches; 5052292SN/A /** Stat for total number of cycles spent fetching. */ 5065999Snate@binkert.org Stats::Scalar fetchCycles; 5072292SN/A /** Stat for total number of cycles spent squashing. */ 5085999Snate@binkert.org Stats::Scalar fetchSquashCycles; 5097849SAli.Saidi@ARM.com /** Stat for total number of cycles spent waiting for translation */ 5107849SAli.Saidi@ARM.com Stats::Scalar fetchTlbCycles; 5112292SN/A /** Stat for total number of cycles spent blocked due to other stages in 5122292SN/A * the pipeline. 5132292SN/A */ 5145999Snate@binkert.org Stats::Scalar fetchIdleCycles; 5152348SN/A /** Total number of cycles spent blocked. */ 5165999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 5172348SN/A /** Total number of cycles spent in any other state. */ 5185999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 5192292SN/A /** Stat for total number of fetched cache lines. */ 5205999Snate@binkert.org Stats::Scalar fetchedCacheLines; 5212348SN/A /** Total number of outstanding icache accesses that were dropped 5222348SN/A * due to a squash. 5232348SN/A */ 5245999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 5258064SAli.Saidi@ARM.com /** Total number of outstanding tlb accesses that were dropped 5268064SAli.Saidi@ARM.com * due to a squash. 5278064SAli.Saidi@ARM.com */ 5288064SAli.Saidi@ARM.com Stats::Scalar fetchTlbSquashes; 5292292SN/A /** Distribution of number of instructions fetched each cycle. */ 5305999Snate@binkert.org Stats::Distribution fetchNisnDist; 5312348SN/A /** Rate of how often fetch was idle. */ 5322292SN/A Stats::Formula idleRate; 5332348SN/A /** Number of branch fetches per cycle. */ 5342292SN/A Stats::Formula branchRate; 5352348SN/A /** Number of instruction fetched per cycle. */ 5362292SN/A Stats::Formula fetchRate; 5371060SN/A}; 5381060SN/A 5392292SN/A#endif //__CPU_O3_FETCH_HH__ 540