fetch.hh revision 7764
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_FETCH_HH__ 332292SN/A#define __CPU_O3_FETCH_HH__ 341060SN/A 352669Sktlim@umich.edu#include "arch/utility.hh" 364182Sgblack@eecs.umich.edu#include "arch/predecoder.hh" 371461SN/A#include "base/statistics.hh" 381060SN/A#include "base/timebuf.hh" 396658Snate@binkert.org#include "config/the_isa.hh" 401060SN/A#include "cpu/pc_event.hh" 413348Sbinkertn@umich.edu#include "mem/packet.hh" 422669Sktlim@umich.edu#include "mem/port.hh" 431461SN/A#include "sim/eventq.hh" 441060SN/A 455529Snate@binkert.orgclass DerivO3CPUParams; 465529Snate@binkert.org 471060SN/A/** 482329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 492329SN/A * width is specified by the parameters; each cycle it tries to fetch 502329SN/A * that many instructions. It supports using a branch predictor to 512329SN/A * predict direction and targets. 522348SN/A * It supports the idling functionality of the CPU by indicating to 532329SN/A * the CPU when it is active and inactive. 541060SN/A */ 551060SN/Atemplate <class Impl> 562292SN/Aclass DefaultFetch 571060SN/A{ 581060SN/A public: 591060SN/A /** Typedefs from Impl. */ 601061SN/A typedef typename Impl::CPUPol CPUPol; 611060SN/A typedef typename Impl::DynInst DynInst; 621061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 632733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 641060SN/A 652292SN/A /** Typedefs from the CPU policy. */ 661061SN/A typedef typename CPUPol::BPredUnit BPredUnit; 671061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 681061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 691060SN/A 701060SN/A /** Typedefs from ISA. */ 712107SN/A typedef TheISA::MachInst MachInst; 722292SN/A typedef TheISA::ExtMachInst ExtMachInst; 732632Sstever@eecs.umich.edu 742698Sktlim@umich.edu /** IcachePort class for DefaultFetch. Handles doing the 752698Sktlim@umich.edu * communication with the cache/memory. 762698Sktlim@umich.edu */ 772669Sktlim@umich.edu class IcachePort : public Port 782669Sktlim@umich.edu { 792669Sktlim@umich.edu protected: 802698Sktlim@umich.edu /** Pointer to fetch. */ 812669Sktlim@umich.edu DefaultFetch<Impl> *fetch; 822669Sktlim@umich.edu 832669Sktlim@umich.edu public: 842698Sktlim@umich.edu /** Default constructor. */ 855494Sstever@gmail.com IcachePort(DefaultFetch<Impl> *_fetch) 865606Snate@binkert.org : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch) 872669Sktlim@umich.edu { } 882669Sktlim@umich.edu 893647Srdreslin@umich.edu bool snoopRangeSent; 903647Srdreslin@umich.edu 914302Sktlim@umich.edu virtual void setPeer(Port *port); 924302Sktlim@umich.edu 932669Sktlim@umich.edu protected: 942698Sktlim@umich.edu /** Atomic version of receive. Panics. */ 952669Sktlim@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 962669Sktlim@umich.edu 972698Sktlim@umich.edu /** Functional version of receive. Panics. */ 982669Sktlim@umich.edu virtual void recvFunctional(PacketPtr pkt); 992669Sktlim@umich.edu 1002698Sktlim@umich.edu /** Receives status change. Other than range changing, panics. */ 1012669Sktlim@umich.edu virtual void recvStatusChange(Status status); 1022669Sktlim@umich.edu 1032698Sktlim@umich.edu /** Returns the address ranges of this device. */ 1042669Sktlim@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1054475Sstever@eecs.umich.edu bool &snoop) 1064475Sstever@eecs.umich.edu { resp.clear(); snoop = true; } 1072669Sktlim@umich.edu 1082698Sktlim@umich.edu /** Timing version of receive. Handles setting fetch to the 1092698Sktlim@umich.edu * proper status to start fetching. */ 1102669Sktlim@umich.edu virtual bool recvTiming(PacketPtr pkt); 1112669Sktlim@umich.edu 1122698Sktlim@umich.edu /** Handles doing a retry of a failed fetch. */ 1132669Sktlim@umich.edu virtual void recvRetry(); 1142669Sktlim@umich.edu }; 1151060SN/A 1162935Sksewell@umich.edu 1171060SN/A public: 1182329SN/A /** Overall fetch status. Used to determine if the CPU can 1192329SN/A * deschedule itsef due to a lack of activity. 1202292SN/A */ 1212292SN/A enum FetchStatus { 1222292SN/A Active, 1232292SN/A Inactive 1242292SN/A }; 1252292SN/A 1262292SN/A /** Individual thread status. */ 1272292SN/A enum ThreadStatus { 1281060SN/A Running, 1291060SN/A Idle, 1301060SN/A Squashing, 1311060SN/A Blocked, 1322292SN/A Fetching, 1332292SN/A TrapPending, 1342292SN/A QuiescePending, 1352307SN/A SwitchOut, 1362669Sktlim@umich.edu IcacheWaitResponse, 1372696Sktlim@umich.edu IcacheWaitRetry, 1382669Sktlim@umich.edu IcacheAccessComplete 1391060SN/A }; 1401060SN/A 1412292SN/A /** Fetching Policy, Add new policies here.*/ 1422292SN/A enum FetchPriority { 1432292SN/A SingleThread, 1442292SN/A RoundRobin, 1452292SN/A Branch, 1462292SN/A IQ, 1472292SN/A LSQ 1482292SN/A }; 1491060SN/A 1502292SN/A private: 1512292SN/A /** Fetch status. */ 1522292SN/A FetchStatus _status; 1532292SN/A 1542292SN/A /** Per-thread status. */ 1552292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1562292SN/A 1572292SN/A /** Fetch policy. */ 1582292SN/A FetchPriority fetchPolicy; 1592292SN/A 1602292SN/A /** List that has the threads organized by priority. */ 1616221Snate@binkert.org std::list<ThreadID> priorityList; 1621060SN/A 1631060SN/A public: 1642292SN/A /** DefaultFetch constructor. */ 1655529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 1661684SN/A 1672292SN/A /** Returns the name of fetch. */ 1682292SN/A std::string name() const; 1691684SN/A 1702292SN/A /** Registers statistics. */ 1711062SN/A void regStats(); 1721062SN/A 1732871Sktlim@umich.edu /** Returns the icache port. */ 1742871Sktlim@umich.edu Port *getIcachePort() { return icachePort; } 1752871Sktlim@umich.edu 1762292SN/A /** Sets the main backwards communication time buffer pointer. */ 1771060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 1781060SN/A 1792292SN/A /** Sets pointer to list of active threads. */ 1806221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1812292SN/A 1822292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 1831060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1841060SN/A 1852292SN/A /** Initialize stage. */ 1862292SN/A void initStage(); 1872292SN/A 1884302Sktlim@umich.edu /** Tells the fetch stage that the Icache is set. */ 1894302Sktlim@umich.edu void setIcache(); 1904302Sktlim@umich.edu 1912292SN/A /** Processes cache completion event. */ 1922669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 1932292SN/A 1942843Sktlim@umich.edu /** Begins the drain of the fetch stage. */ 1952863Sktlim@umich.edu bool drain(); 1962843Sktlim@umich.edu 1972843Sktlim@umich.edu /** Resumes execution after a drain. */ 1982843Sktlim@umich.edu void resume(); 1992843Sktlim@umich.edu 2002843Sktlim@umich.edu /** Tells fetch stage to prepare to be switched out. */ 2012307SN/A void switchOut(); 2022307SN/A 2032348SN/A /** Takes over from another CPU's thread. */ 2042307SN/A void takeOverFrom(); 2052307SN/A 2062348SN/A /** Checks if the fetch stage is switched out. */ 2072307SN/A bool isSwitchedOut() { return switchedOut; } 2082307SN/A 2092348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2102292SN/A void wakeFromQuiesce(); 2111060SN/A 2121061SN/A private: 2132329SN/A /** Changes the status of this stage to active, and indicates this 2142329SN/A * to the CPU. 2152292SN/A */ 2162292SN/A inline void switchToActive(); 2172292SN/A 2182329SN/A /** Changes the status of this stage to inactive, and indicates 2192329SN/A * this to the CPU. 2202292SN/A */ 2212292SN/A inline void switchToInactive(); 2222292SN/A 2231061SN/A /** 2241061SN/A * Looks up in the branch predictor to see if the next PC should be 2251061SN/A * either next PC+=MachInst or a branch target. 2261763SN/A * @param next_PC Next PC variable passed in by reference. It is 2271061SN/A * expected to be set to the current PC; it will be updated with what 2281061SN/A * the next PC will be. 2292935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 2301061SN/A * @return Whether or not a branch was predicted as taken. 2311061SN/A */ 2327720Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2331062SN/A 2341062SN/A /** 2351062SN/A * Fetches the cache line that contains fetch_PC. Returns any 2361062SN/A * fault that happened. Puts the data into the class variable 2371062SN/A * cacheData. 2387764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 2392292SN/A * @param ret_fault The fault reference that will be set to the result of 2402292SN/A * the icache access. 2412292SN/A * @param tid Thread id. 2427764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 2431062SN/A * @return Any fault that occured. 2441062SN/A */ 2457764Sgblack@eecs.umich.edu bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc); 2461062SN/A 2472292SN/A /** Squashes a specific thread and resets the PC. */ 2487720Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, ThreadID tid); 2491684SN/A 2502292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2512292SN/A * remove any instructions between fetch and decode that should be sqaushed. 2522292SN/A */ 2537720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 2546221Snate@binkert.org const InstSeqNum &seq_num, ThreadID tid); 2552292SN/A 2562292SN/A /** Checks if a thread is stalled. */ 2576221Snate@binkert.org bool checkStall(ThreadID tid) const; 2582292SN/A 2592292SN/A /** Updates overall fetch stage status; to be called at the end of each 2602292SN/A * cycle. */ 2612292SN/A FetchStatus updateFetchStatus(); 2621684SN/A 2631684SN/A public: 2642292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2652292SN/A * remove any instructions that are not in the ROB. The source of this 2662292SN/A * squash should be the commit stage. 2672292SN/A */ 2687720Sgblack@eecs.umich.edu void squash(const TheISA::PCState &newPC, 2696221Snate@binkert.org const InstSeqNum &seq_num, ThreadID tid); 2701684SN/A 2712292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 2722292SN/A * as many instructions as possible. 2732292SN/A */ 2741684SN/A void tick(); 2751684SN/A 2762292SN/A /** Checks all input signals and updates the status as necessary. 2772292SN/A * @return: Returns if the status has changed due to input signals. 2782292SN/A */ 2796221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 2801684SN/A 2812292SN/A /** Does the actual fetching of instructions and passing them on to the 2822292SN/A * next stage. 2832292SN/A * @param status_change fetch() sets this variable if there was a status 2842292SN/A * change (ie switching to IcacheMissStall). 2852292SN/A */ 2862292SN/A void fetch(bool &status_change); 2872292SN/A 2882292SN/A /** Align a PC to the start of an I-cache block. */ 2891062SN/A Addr icacheBlockAlignPC(Addr addr) 2901062SN/A { 2911062SN/A return (addr & ~(cacheBlkMask)); 2921062SN/A } 2931061SN/A 2941060SN/A private: 2957764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 2967764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 2977764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 2987764Sgblack@eecs.umich.edu 2992698Sktlim@umich.edu /** Handles retrying the fetch access. */ 3002696Sktlim@umich.edu void recvRetry(); 3012696Sktlim@umich.edu 3022292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3036221Snate@binkert.org ThreadID getFetchingThread(FetchPriority &fetch_priority); 3042292SN/A 3052292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3066221Snate@binkert.org ThreadID roundRobin(); 3072292SN/A 3082292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3096221Snate@binkert.org ThreadID iqCount(); 3102292SN/A 3112292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3126221Snate@binkert.org ThreadID lsqCount(); 3132292SN/A 3146221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 3156221Snate@binkert.org * policy. */ 3166221Snate@binkert.org ThreadID branchCount(); 3172292SN/A 3182292SN/A private: 3192733Sktlim@umich.edu /** Pointer to the O3CPU. */ 3202733Sktlim@umich.edu O3CPU *cpu; 3211060SN/A 3221060SN/A /** Time buffer interface. */ 3231060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3241060SN/A 3251060SN/A /** Wire to get decode's information from backwards time buffer. */ 3261060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3271060SN/A 3281060SN/A /** Wire to get rename's information from backwards time buffer. */ 3291060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3301060SN/A 3311060SN/A /** Wire to get iew's information from backwards time buffer. */ 3321060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3331060SN/A 3341060SN/A /** Wire to get commit's information from backwards time buffer. */ 3351060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3361060SN/A 3371060SN/A /** Internal fetch instruction queue. */ 3381060SN/A TimeBuffer<FetchStruct> *fetchQueue; 3391060SN/A 3401060SN/A //Might be annoying how this name is different than the queue. 3411060SN/A /** Wire used to write any information heading to decode. */ 3421060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 3431060SN/A 3441060SN/A /** Icache interface. */ 3452669Sktlim@umich.edu IcachePort *icachePort; 3461060SN/A 3471061SN/A /** BPredUnit. */ 3481061SN/A BPredUnit branchPred; 3491061SN/A 3504182Sgblack@eecs.umich.edu /** Predecoder. */ 3514182Sgblack@eecs.umich.edu TheISA::Predecoder predecoder; 3524182Sgblack@eecs.umich.edu 3537720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 3542292SN/A 3557764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 3567764Sgblack@eecs.umich.edu 3577764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 3587764Sgblack@eecs.umich.edu 3592678Sktlim@umich.edu /** Memory request used to access cache. */ 3602678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 3612292SN/A 3622292SN/A /** Variable that tracks if fetch has written to the time buffer this 3632292SN/A * cycle. Used to tell CPU if there is activity this cycle. 3642292SN/A */ 3652292SN/A bool wroteToTimeBuffer; 3662292SN/A 3672292SN/A /** Tracks how many instructions has been fetched this cycle. */ 3682292SN/A int numInst; 3692292SN/A 3702292SN/A /** Source of possible stalls. */ 3712292SN/A struct Stalls { 3722292SN/A bool decode; 3732292SN/A bool rename; 3742292SN/A bool iew; 3752292SN/A bool commit; 3762292SN/A }; 3772292SN/A 3782292SN/A /** Tracks which stages are telling fetch to stall. */ 3792292SN/A Stalls stalls[Impl::MaxThreads]; 3801060SN/A 3811060SN/A /** Decode to fetch delay, in ticks. */ 3821060SN/A unsigned decodeToFetchDelay; 3831060SN/A 3841060SN/A /** Rename to fetch delay, in ticks. */ 3851060SN/A unsigned renameToFetchDelay; 3861060SN/A 3871060SN/A /** IEW to fetch delay, in ticks. */ 3881060SN/A unsigned iewToFetchDelay; 3891060SN/A 3901060SN/A /** Commit to fetch delay, in ticks. */ 3911060SN/A unsigned commitToFetchDelay; 3921060SN/A 3931060SN/A /** The width of fetch in instructions. */ 3941060SN/A unsigned fetchWidth; 3951060SN/A 3962696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 3972696Sktlim@umich.edu bool cacheBlocked; 3982696Sktlim@umich.edu 3992696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 4002696Sktlim@umich.edu PacketPtr retryPkt; 4012696Sktlim@umich.edu 4022696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 4036221Snate@binkert.org ThreadID retryTid; 4042696Sktlim@umich.edu 4051060SN/A /** Cache block size. */ 4061062SN/A int cacheBlkSize; 4071060SN/A 4081060SN/A /** Mask to get a cache block's address. */ 4091062SN/A Addr cacheBlkMask; 4101060SN/A 4111062SN/A /** The cache line being fetched. */ 4122292SN/A uint8_t *cacheData[Impl::MaxThreads]; 4131060SN/A 4142893Sktlim@umich.edu /** The PC of the cacheline that has been loaded. */ 4152893Sktlim@umich.edu Addr cacheDataPC[Impl::MaxThreads]; 4162893Sktlim@umich.edu 4172906Sktlim@umich.edu /** Whether or not the cache data is valid. */ 4182906Sktlim@umich.edu bool cacheDataValid[Impl::MaxThreads]; 4192906Sktlim@umich.edu 4201060SN/A /** Size of instructions. */ 4211060SN/A int instSize; 4221060SN/A 4231060SN/A /** Icache stall statistics. */ 4242292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 4251062SN/A 4262292SN/A /** List of Active Threads */ 4276221Snate@binkert.org std::list<ThreadID> *activeThreads; 4282292SN/A 4292292SN/A /** Number of threads. */ 4306221Snate@binkert.org ThreadID numThreads; 4312292SN/A 4322292SN/A /** Number of threads that are actively fetching. */ 4336221Snate@binkert.org ThreadID numFetchingThreads; 4342292SN/A 4352292SN/A /** Thread ID being fetched. */ 4366221Snate@binkert.org ThreadID threadFetched; 4372292SN/A 4382348SN/A /** Checks if there is an interrupt pending. If there is, fetch 4392348SN/A * must stop once it is not fetching PAL instructions. 4402348SN/A */ 4412292SN/A bool interruptPending; 4422292SN/A 4432843Sktlim@umich.edu /** Is there a drain pending. */ 4442843Sktlim@umich.edu bool drainPending; 4452843Sktlim@umich.edu 4462348SN/A /** Records if fetch is switched out. */ 4472307SN/A bool switchedOut; 4482307SN/A 4492292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 4502292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 4515999Snate@binkert.org Stats::Scalar icacheStallCycles; 4522292SN/A /** Stat for total number of fetched instructions. */ 4535999Snate@binkert.org Stats::Scalar fetchedInsts; 4542727Sktlim@umich.edu /** Total number of fetched branches. */ 4555999Snate@binkert.org Stats::Scalar fetchedBranches; 4562292SN/A /** Stat for total number of predicted branches. */ 4575999Snate@binkert.org Stats::Scalar predictedBranches; 4582292SN/A /** Stat for total number of cycles spent fetching. */ 4595999Snate@binkert.org Stats::Scalar fetchCycles; 4602292SN/A /** Stat for total number of cycles spent squashing. */ 4615999Snate@binkert.org Stats::Scalar fetchSquashCycles; 4622292SN/A /** Stat for total number of cycles spent blocked due to other stages in 4632292SN/A * the pipeline. 4642292SN/A */ 4655999Snate@binkert.org Stats::Scalar fetchIdleCycles; 4662348SN/A /** Total number of cycles spent blocked. */ 4675999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 4682348SN/A /** Total number of cycles spent in any other state. */ 4695999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 4702292SN/A /** Stat for total number of fetched cache lines. */ 4715999Snate@binkert.org Stats::Scalar fetchedCacheLines; 4722348SN/A /** Total number of outstanding icache accesses that were dropped 4732348SN/A * due to a squash. 4742348SN/A */ 4755999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 4762292SN/A /** Distribution of number of instructions fetched each cycle. */ 4775999Snate@binkert.org Stats::Distribution fetchNisnDist; 4782348SN/A /** Rate of how often fetch was idle. */ 4792292SN/A Stats::Formula idleRate; 4802348SN/A /** Number of branch fetches per cycle. */ 4812292SN/A Stats::Formula branchRate; 4822348SN/A /** Number of instruction fetched per cycle. */ 4832292SN/A Stats::Formula fetchRate; 4841060SN/A}; 4851060SN/A 4862292SN/A#endif //__CPU_O3_FETCH_HH__ 487