fetch.hh revision 7720
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37783SGiacomo.Gabrielli@arm.com * All rights reserved. 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67783SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77783SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87783SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97783SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107783SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117783SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127783SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137783SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 142316SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A * 281689SN/A * Authors: Kevin Lim 291689SN/A * Korey Sewell 301689SN/A */ 311689SN/A 321689SN/A#ifndef __CPU_O3_FETCH_HH__ 331689SN/A#define __CPU_O3_FETCH_HH__ 341689SN/A 351689SN/A#include "arch/utility.hh" 361689SN/A#include "arch/predecoder.hh" 371689SN/A#include "base/statistics.hh" 381689SN/A#include "base/timebuf.hh" 392665Ssaidi@eecs.umich.edu#include "config/the_isa.hh" 402665Ssaidi@eecs.umich.edu#include "cpu/pc_event.hh" 412965Sksewell@umich.edu#include "mem/packet.hh" 421689SN/A#include "mem/port.hh" 431689SN/A#include "sim/eventq.hh" 442292SN/A 452329SN/Aclass DerivO3CPUParams; 462292SN/A 473577Sgblack@eecs.umich.edu/** 488229Snate@binkert.org * DefaultFetch class handles both single threaded and SMT fetch. Its 495953Ssaidi@eecs.umich.edu * width is specified by the parameters; each cycle it tries to fetch 506221Snate@binkert.org * that many instructions. It supports using a branch predictor to 516658Snate@binkert.org * predict direction and targets. 526221Snate@binkert.org * It supports the idling functionality of the CPU by indicating to 531717SN/A * the CPU when it is active and inactive. 542292SN/A */ 558229Snate@binkert.orgtemplate <class Impl> 568229Snate@binkert.orgclass DefaultFetch 578232Snate@binkert.org{ 588232Snate@binkert.org public: 598232Snate@binkert.org /** Typedefs from Impl. */ 608232Snate@binkert.org typedef typename Impl::CPUPol CPUPol; 616221Snate@binkert.org typedef typename Impl::DynInst DynInst; 628230Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 632292SN/A typedef typename Impl::O3CPU O3CPU; 642790Sktlim@umich.edu 652790Sktlim@umich.edu /** Typedefs from the CPU policy. */ 662790Sktlim@umich.edu typedef typename CPUPol::BPredUnit BPredUnit; 672790Sktlim@umich.edu typedef typename CPUPol::FetchStruct FetchStruct; 686221Snate@binkert.org typedef typename CPUPol::TimeStruct TimeStruct; 695529Snate@binkert.org 701061SN/A /** Typedefs from ISA. */ 712292SN/A typedef TheISA::MachInst MachInst; 726221Snate@binkert.org typedef TheISA::ExtMachInst ExtMachInst; 735606Snate@binkert.org 741060SN/A /** IcachePort class for DefaultFetch. Handles doing the 755769Snate@binkert.org * communication with the cache/memory. 761060SN/A */ 771060SN/A class IcachePort : public Port 781061SN/A { 791060SN/A protected: 802292SN/A /** Pointer to fetch. */ 811062SN/A DefaultFetch<Impl> *fetch; 822316SN/A 832316SN/A public: 842292SN/A /** Default constructor. */ 852292SN/A IcachePort(DefaultFetch<Impl> *_fetch) 862292SN/A : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch) 872292SN/A { } 882292SN/A 895336Shines@cs.fsu.edu bool snoopRangeSent; 902292SN/A 914873Sstever@eecs.umich.edu virtual void setPeer(Port *port); 922292SN/A 932292SN/A protected: 942292SN/A /** Atomic version of receive. Panics. */ 955529Snate@binkert.org virtual Tick recvAtomic(PacketPtr pkt); 964329Sktlim@umich.edu 974329Sktlim@umich.edu /** Functional version of receive. Panics. */ 982292SN/A virtual void recvFunctional(PacketPtr pkt); 992292SN/A 1002292SN/A /** Receives status change. Other than range changing, panics. */ 1012292SN/A virtual void recvStatusChange(Status status); 1022292SN/A 1032292SN/A /** Returns the address ranges of this device. */ 1045529Snate@binkert.org virtual void getDeviceAddressRanges(AddrRangeList &resp, 1052843Sktlim@umich.edu bool &snoop) 1062316SN/A { resp.clear(); snoop = true; } 1072874Sktlim@umich.edu 1082292SN/A /** Timing version of receive. Handles setting fetch to the 1092292SN/A * proper status to start fetching. */ 1102292SN/A virtual bool recvTiming(PacketPtr pkt); 1112980Sgblack@eecs.umich.edu 1122292SN/A /** Handles doing a retry of a failed fetch. */ 1132292SN/A virtual void recvRetry(); 1142292SN/A }; 1152292SN/A 1162292SN/A 1172292SN/A public: 1182292SN/A /** Overall fetch status. Used to determine if the CPU can 1192292SN/A * deschedule itsef due to a lack of activity. 1202292SN/A */ 1214329Sktlim@umich.edu enum FetchStatus { 1222292SN/A Active, 1232292SN/A Inactive 1242292SN/A }; 1252292SN/A 1266221Snate@binkert.org /** Individual thread status. */ 1272292SN/A enum ThreadStatus { 1282292SN/A Running, 1292292SN/A Idle, 1304329Sktlim@umich.edu Squashing, 1312292SN/A Blocked, 1322292SN/A Fetching, 1332292SN/A TrapPending, 1344329Sktlim@umich.edu QuiescePending, 1352292SN/A SwitchOut, 1362292SN/A IcacheWaitResponse, 1372292SN/A IcacheWaitRetry, 1382292SN/A IcacheAccessComplete 1392292SN/A }; 1406221Snate@binkert.org 1416221Snate@binkert.org /** Fetching Policy, Add new policies here.*/ 1426221Snate@binkert.org enum FetchPriority { 1436221Snate@binkert.org SingleThread, 1446221Snate@binkert.org RoundRobin, 1456221Snate@binkert.org Branch, 1466221Snate@binkert.org IQ, 1476221Snate@binkert.org LSQ 1487720Sgblack@eecs.umich.edu }; 1497855SAli.Saidi@ARM.com 1502292SN/A private: 1513640Sktlim@umich.edu /** Fetch status. */ 1523640Sktlim@umich.edu FetchStatus _status; 1533640Sktlim@umich.edu 1542292SN/A /** Per-thread status. */ 1552292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1562292SN/A 1572292SN/A /** Fetch policy. */ 1582292SN/A FetchPriority fetchPolicy; 1592292SN/A 1602292SN/A /** List that has the threads organized by priority. */ 1612292SN/A std::list<ThreadID> priorityList; 1622292SN/A 1632292SN/A public: 1642292SN/A /** DefaultFetch constructor. */ 1652292SN/A DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 1662132SN/A 1672301SN/A /** Returns the name of fetch. */ 1681062SN/A std::string name() const; 1691062SN/A 1701062SN/A /** Registers statistics. */ 1711062SN/A void regStats(); 1721062SN/A 1731062SN/A /** Returns the icache port. */ 1741062SN/A Port *getIcachePort() { return icachePort; } 1751062SN/A 1761062SN/A /** Sets the main backwards communication time buffer pointer. */ 1771062SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 1781062SN/A 1791062SN/A /** Sets pointer to list of active threads. */ 1801062SN/A void setActiveThreads(std::list<ThreadID> *at_ptr); 1811062SN/A 1821062SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 1831062SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1841062SN/A 1851062SN/A /** Initialize stage. */ 1861062SN/A void initStage(); 1871062SN/A 1881062SN/A /** Tells the fetch stage that the Icache is set. */ 1892292SN/A void setIcache(); 1901062SN/A 1911062SN/A /** Processes cache completion event. */ 1921062SN/A void processCacheCompletion(PacketPtr pkt); 1931062SN/A 1941062SN/A /** Begins the drain of the fetch stage. */ 1952301SN/A bool drain(); 1962316SN/A 1976221Snate@binkert.org /** Resumes execution after a drain. */ 1982301SN/A void resume(); 1992301SN/A 2002301SN/A /** Tells fetch stage to prepare to be switched out. */ 2012301SN/A void switchOut(); 2022301SN/A 2032316SN/A /** Takes over from another CPU's thread. */ 2046221Snate@binkert.org void takeOverFrom(); 2052301SN/A 2062301SN/A /** Checks if the fetch stage is switched out. */ 2072301SN/A bool isSwitchedOut() { return switchedOut; } 2082301SN/A 2092301SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2102316SN/A void wakeFromQuiesce(); 2116221Snate@binkert.org 2122301SN/A private: 2132301SN/A /** Changes the status of this stage to active, and indicates this 2142301SN/A * to the CPU. 2152301SN/A */ 2162301SN/A inline void switchToActive(); 2172316SN/A 2186221Snate@binkert.org /** Changes the status of this stage to inactive, and indicates 2192301SN/A * this to the CPU. 2202301SN/A */ 2212301SN/A inline void switchToInactive(); 2222301SN/A 2232301SN/A /** 2242316SN/A * Looks up in the branch predictor to see if the next PC should be 2256221Snate@binkert.org * either next PC+=MachInst or a branch target. 2262301SN/A * @param next_PC Next PC variable passed in by reference. It is 2272301SN/A * expected to be set to the current PC; it will be updated with what 2282301SN/A * the next PC will be. 2292301SN/A * @param next_NPC Used for ISAs which use delay slots. 2302301SN/A * @return Whether or not a branch was predicted as taken. 2312316SN/A */ 2326221Snate@binkert.org bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2332301SN/A 2342301SN/A /** 2352301SN/A * Fetches the cache line that contains fetch_PC. Returns any 2362301SN/A * fault that happened. Puts the data into the class variable 2372301SN/A * cacheData. 2387897Shestness@cs.utexas.edu * @param fetch_PC The PC address that is being fetched from. 2397897Shestness@cs.utexas.edu * @param ret_fault The fault reference that will be set to the result of 2407897Shestness@cs.utexas.edu * the icache access. 2417897Shestness@cs.utexas.edu * @param tid Thread id. 2427897Shestness@cs.utexas.edu * @return Any fault that occured. 2437897Shestness@cs.utexas.edu */ 2447897Shestness@cs.utexas.edu bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid); 2457897Shestness@cs.utexas.edu 2467897Shestness@cs.utexas.edu /** Squashes a specific thread and resets the PC. */ 2477897Shestness@cs.utexas.edu inline void doSquash(const TheISA::PCState &newPC, ThreadID tid); 2487897Shestness@cs.utexas.edu 2497897Shestness@cs.utexas.edu /** Squashes a specific thread and resets the PC. Also tells the CPU to 2507897Shestness@cs.utexas.edu * remove any instructions between fetch and decode that should be sqaushed. 2517897Shestness@cs.utexas.edu */ 2527897Shestness@cs.utexas.edu void squashFromDecode(const TheISA::PCState &newPC, 2537897Shestness@cs.utexas.edu const InstSeqNum &seq_num, ThreadID tid); 2547897Shestness@cs.utexas.edu 2557897Shestness@cs.utexas.edu /** Checks if a thread is stalled. */ 2567897Shestness@cs.utexas.edu bool checkStall(ThreadID tid) const; 2577897Shestness@cs.utexas.edu 2587897Shestness@cs.utexas.edu /** Updates overall fetch stage status; to be called at the end of each 2592316SN/A * cycle. */ 2606221Snate@binkert.org FetchStatus updateFetchStatus(); 2612301SN/A 2622301SN/A public: 2632301SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2642301SN/A * remove any instructions that are not in the ROB. The source of this 2652301SN/A * squash should be the commit stage. 2662316SN/A */ 2672301SN/A void squash(const TheISA::PCState &newPC, 2682301SN/A const InstSeqNum &seq_num, ThreadID tid); 2692301SN/A 2701062SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 2711062SN/A * as many instructions as possible. 2721062SN/A */ 2731062SN/A void tick(); 2742980Sgblack@eecs.umich.edu 2752292SN/A /** Checks all input signals and updates the status as necessary. 2762292SN/A * @return: Returns if the status has changed due to input signals. 2772292SN/A */ 2782292SN/A bool checkSignalsAndUpdate(ThreadID tid); 2792292SN/A 2802292SN/A /** Does the actual fetching of instructions and passing them on to the 2812292SN/A * next stage. 2821060SN/A * @param status_change fetch() sets this variable if there was a status 2831060SN/A * change (ie switching to IcacheMissStall). 2841060SN/A */ 2851060SN/A void fetch(bool &status_change); 2861060SN/A 2871060SN/A /** Align a PC to the start of an I-cache block. */ 2881060SN/A Addr icacheBlockAlignPC(Addr addr) 2891060SN/A { 2901060SN/A return (addr & ~(cacheBlkMask)); 2911060SN/A } 2921061SN/A 2931060SN/A private: 2942292SN/A /** Handles retrying the fetch access. */ 2952292SN/A void recvRetry(); 2962292SN/A 2972292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 2982292SN/A ThreadID getFetchingThread(FetchPriority &fetch_priority); 2992292SN/A 3002292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3012292SN/A ThreadID roundRobin(); 3022292SN/A 3032292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3042292SN/A ThreadID iqCount(); 3051060SN/A 3061060SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3071060SN/A ThreadID lsqCount(); 3081060SN/A 3091060SN/A /** Returns the appropriate thread to fetch using the branch count 3101060SN/A * policy. */ 3111060SN/A ThreadID branchCount(); 3121061SN/A 3131060SN/A private: 3142292SN/A /** Pointer to the O3CPU. */ 3151060SN/A O3CPU *cpu; 3161060SN/A 3171060SN/A /** Time buffer interface. */ 3181060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3191060SN/A 3201060SN/A /** Wire to get decode's information from backwards time buffer. */ 3211060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3221061SN/A 3231060SN/A /** Wire to get rename's information from backwards time buffer. */ 3242292SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3252292SN/A 3262292SN/A /** Wire to get iew's information from backwards time buffer. */ 3272292SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3282292SN/A 3292292SN/A /** Wire to get commit's information from backwards time buffer. */ 3302292SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3316221Snate@binkert.org 3322292SN/A /** Internal fetch instruction queue. */ 3332292SN/A TimeBuffer<FetchStruct> *fetchQueue; 3342292SN/A 3352292SN/A //Might be annoying how this name is different than the queue. 3362292SN/A /** Wire used to write any information heading to decode. */ 3372292SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 3382292SN/A 3392292SN/A /** Icache interface. */ 3406221Snate@binkert.org IcachePort *icachePort; 3416221Snate@binkert.org 3422292SN/A /** BPredUnit. */ 3432292SN/A BPredUnit branchPred; 3442292SN/A 3452292SN/A /** Predecoder. */ 3462292SN/A TheISA::Predecoder predecoder; 3471060SN/A 3481060SN/A TheISA::PCState pc[Impl::MaxThreads]; 3491060SN/A 3501060SN/A /** Memory request used to access cache. */ 3511061SN/A RequestPtr memReq[Impl::MaxThreads]; 3521060SN/A 3532292SN/A /** Variable that tracks if fetch has written to the time buffer this 3541060SN/A * cycle. Used to tell CPU if there is activity this cycle. 3552292SN/A */ 3562292SN/A bool wroteToTimeBuffer; 3571060SN/A 3582292SN/A /** Tracks how many instructions has been fetched this cycle. */ 3596221Snate@binkert.org int numInst; 3606221Snate@binkert.org 3616221Snate@binkert.org /** Source of possible stalls. */ 3626221Snate@binkert.org struct Stalls { 3631060SN/A bool decode; 3641060SN/A bool rename; 3654329Sktlim@umich.edu bool iew; 3664329Sktlim@umich.edu bool commit; 3674329Sktlim@umich.edu }; 3684329Sktlim@umich.edu 3692292SN/A /** Tracks which stages are telling fetch to stall. */ 3705100Ssaidi@eecs.umich.edu Stalls stalls[Impl::MaxThreads]; 3711060SN/A 3721060SN/A /** Decode to fetch delay, in ticks. */ 3731061SN/A unsigned decodeToFetchDelay; 3742863Sktlim@umich.edu 3752843Sktlim@umich.edu /** Rename to fetch delay, in ticks. */ 3761060SN/A unsigned renameToFetchDelay; 3772843Sktlim@umich.edu 3782863Sktlim@umich.edu /** IEW to fetch delay, in ticks. */ 3792863Sktlim@umich.edu unsigned iewToFetchDelay; 3802316SN/A 3812316SN/A /** Commit to fetch delay, in ticks. */ 3822316SN/A unsigned commitToFetchDelay; 3832316SN/A 3842843Sktlim@umich.edu /** The width of fetch in instructions. */ 3852316SN/A unsigned fetchWidth; 3862316SN/A 3872843Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 3882307SN/A bool cacheBlocked; 3892307SN/A 3902307SN/A /** The packet that is waiting to be retried. */ 3912307SN/A PacketPtr retryPkt; 3922307SN/A 3932843Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 3942843Sktlim@umich.edu ThreadID retryTid; 3952864Sktlim@umich.edu 3962843Sktlim@umich.edu /** Cache block size. */ 3972843Sktlim@umich.edu int cacheBlkSize; 3982843Sktlim@umich.edu 3992843Sktlim@umich.edu /** Mask to get a cache block's address. */ 4002307SN/A Addr cacheBlkMask; 4012307SN/A 4022316SN/A /** The cache line being fetched. */ 4032307SN/A uint8_t *cacheData[Impl::MaxThreads]; 4042307SN/A 4056221Snate@binkert.org /** The PC of the cacheline that has been loaded. */ 4066221Snate@binkert.org Addr cacheDataPC[Impl::MaxThreads]; 4076221Snate@binkert.org 4086221Snate@binkert.org /** Whether or not the cache data is valid. */ 4096221Snate@binkert.org bool cacheDataValid[Impl::MaxThreads]; 4102307SN/A 4112307SN/A /** Size of instructions. */ 4122307SN/A int instSize; 4132307SN/A 4142307SN/A /** Icache stall statistics. */ 4152307SN/A Counter lastIcacheStall[Impl::MaxThreads]; 4162307SN/A 4172292SN/A /** List of Active Threads */ 4182132SN/A std::list<ThreadID> *activeThreads; 4192316SN/A 4206221Snate@binkert.org /** Number of threads. */ 4216221Snate@binkert.org ThreadID numThreads; 4223867Sbinkertn@umich.edu 4233867Sbinkertn@umich.edu /** Number of threads that are actively fetching. */ 4246221Snate@binkert.org ThreadID numFetchingThreads; 4253867Sbinkertn@umich.edu 4262316SN/A /** Thread ID being fetched. */ 4272316SN/A ThreadID threadFetched; 4282316SN/A 4292316SN/A /** Checks if there is an interrupt pending. If there is, fetch 4302316SN/A * must stop once it is not fetching PAL instructions. 4312316SN/A */ 4322316SN/A bool interruptPending; 4332292SN/A 4342292SN/A /** Is there a drain pending. */ 4352292SN/A bool drainPending; 4362292SN/A 4372733Sktlim@umich.edu /** Records if fetch is switched out. */ 4382292SN/A bool switchedOut; 4392292SN/A 4402733Sktlim@umich.edu // @todo: Consider making these vectors and tracking on a per thread basis. 4412292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 4422292SN/A Stats::Scalar icacheStallCycles; 4432292SN/A /** Stat for total number of fetched instructions. */ 4442292SN/A Stats::Scalar fetchedInsts; 4452292SN/A /** Total number of fetched branches. */ 4462292SN/A Stats::Scalar fetchedBranches; 4472292SN/A /** Stat for total number of predicted branches. */ 4482292SN/A Stats::Scalar predictedBranches; 4492292SN/A /** Stat for total number of cycles spent fetching. */ 4502292SN/A Stats::Scalar fetchCycles; 4512292SN/A /** Stat for total number of cycles spent squashing. */ 4526221Snate@binkert.org Stats::Scalar fetchSquashCycles; 4536221Snate@binkert.org /** Stat for total number of cycles spent blocked due to other stages in 4542292SN/A * the pipeline. 4553867Sbinkertn@umich.edu */ 4566221Snate@binkert.org Stats::Scalar fetchIdleCycles; 4572292SN/A /** Total number of cycles spent blocked. */ 4582292SN/A Stats::Scalar fetchBlockedCycles; 4592292SN/A /** Total number of cycles spent in any other state. */ 4602292SN/A Stats::Scalar fetchMiscStallCycles; 4612292SN/A /** Stat for total number of fetched cache lines. */ 4622292SN/A Stats::Scalar fetchedCacheLines; 4632702Sktlim@umich.edu /** Total number of outstanding icache accesses that were dropped 4642292SN/A * due to a squash. 4652292SN/A */ 4662292SN/A Stats::Scalar fetchIcacheSquashes; 4672292SN/A /** Distribution of number of instructions fetched each cycle. */ 4682292SN/A Stats::Distribution fetchNisnDist; 4692292SN/A /** Rate of how often fetch was idle. */ 4702292SN/A Stats::Formula idleRate; 4712292SN/A /** Number of branch fetches per cycle. */ 4722292SN/A Stats::Formula branchRate; 4732292SN/A /** Number of instruction fetched per cycle. */ 4742292SN/A Stats::Formula fetchRate; 4752292SN/A}; 4766221Snate@binkert.org 4776221Snate@binkert.org#endif //__CPU_O3_FETCH_HH__ 4782292SN/A