fetch.hh revision 6221
12381SN/A/* 212652Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 38949Sandreas.hansson@arm.com * All rights reserved. 48949Sandreas.hansson@arm.com * 58949Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68949Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78949Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88949Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98949Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108949Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118949Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128949Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138949Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142592SN/A * this software without specific prior written permission. 1510975Sdavid.hashe@amd.com * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272381SN/A * 282381SN/A * Authors: Kevin Lim 292381SN/A * Korey Sewell 302381SN/A */ 312381SN/A 322381SN/A#ifndef __CPU_O3_FETCH_HH__ 332381SN/A#define __CPU_O3_FETCH_HH__ 342381SN/A 352381SN/A#include "arch/utility.hh" 362381SN/A#include "arch/predecoder.hh" 372381SN/A#include "base/statistics.hh" 382381SN/A#include "base/timebuf.hh" 392381SN/A#include "cpu/pc_event.hh" 402665Ssaidi@eecs.umich.edu#include "mem/packet.hh" 412665Ssaidi@eecs.umich.edu#include "mem/port.hh" 422665Ssaidi@eecs.umich.edu#include "sim/eventq.hh" 432665Ssaidi@eecs.umich.edu 449031Sandreas.hansson@arm.comclass DerivO3CPUParams; 4512349Snikos.nikoleris@arm.com 462381SN/A/** 472381SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 482381SN/A * width is specified by the parameters; each cycle it tries to fetch 492381SN/A * that many instructions. It supports using a branch predictor to 502662Sstever@eecs.umich.edu * predict direction and targets. 512381SN/A * It supports the idling functionality of the CPU by indicating to 522381SN/A * the CPU when it is active and inactive. 532381SN/A */ 542381SN/Atemplate <class Impl> 552381SN/Aclass DefaultFetch 568229Snate@binkert.org{ 573348Sbinkertn@umich.edu public: 583348Sbinkertn@umich.edu /** Typedefs from Impl. */ 593348Sbinkertn@umich.edu typedef typename Impl::CPUPol CPUPol; 605735Snate@binkert.org typedef typename Impl::DynInst DynInst; 614024Sbinkertn@umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 625735Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 6312334Sgabeblack@google.com 645314Sstever@gmail.com /** Typedefs from the CPU policy. */ 656216Snate@binkert.org typedef typename CPUPol::BPredUnit BPredUnit; 662392SN/A typedef typename CPUPol::FetchStruct FetchStruct; 674167Sbinkertn@umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 682394SN/A 698737Skoansin.tan@gmail.com /** Typedefs from ISA. */ 703349Sbinkertn@umich.edu typedef TheISA::MachInst MachInst; 712394SN/A typedef TheISA::ExtMachInst ExtMachInst; 722812Srdreslin@umich.edu 7312351Snikos.nikoleris@arm.com /** IcachePort class for DefaultFetch. Handles doing the 742812Srdreslin@umich.edu * communication with the cache/memory. 754022Sstever@eecs.umich.edu */ 764022Sstever@eecs.umich.edu class IcachePort : public Port 775735Snate@binkert.org { 785735Snate@binkert.org protected: 794022Sstever@eecs.umich.edu /** Pointer to fetch. */ 805735Snate@binkert.org DefaultFetch<Impl> *fetch; 815735Snate@binkert.org 825735Snate@binkert.org public: 834022Sstever@eecs.umich.edu /** Default constructor. */ 844022Sstever@eecs.umich.edu IcachePort(DefaultFetch<Impl> *_fetch) 854022Sstever@eecs.umich.edu : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch) 864022Sstever@eecs.umich.edu { } 874473Sstever@eecs.umich.edu 885319Sstever@gmail.com bool snoopRangeSent; 894022Sstever@eecs.umich.edu 904022Sstever@eecs.umich.edu virtual void setPeer(Port *port); 9111199Sandreas.hansson@arm.com 9211199Sandreas.hansson@arm.com protected: 9312344Snikos.nikoleris@arm.com /** Atomic version of receive. Panics. */ 9410883Sali.jafri@arm.com virtual Tick recvAtomic(PacketPtr pkt); 954022Sstever@eecs.umich.edu 964022Sstever@eecs.umich.edu /** Functional version of receive. Panics. */ 974022Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 984022Sstever@eecs.umich.edu 9910886Sandreas.hansson@arm.com /** Receives status change. Other than range changing, panics. */ 1004022Sstever@eecs.umich.edu virtual void recvStatusChange(Status status); 1017465Ssteve.reinhardt@amd.com 1024628Sstever@eecs.umich.edu /** Returns the address ranges of this device. */ 1037465Ssteve.reinhardt@amd.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 1047465Ssteve.reinhardt@amd.com bool &snoop) 1054022Sstever@eecs.umich.edu { resp.clear(); snoop = true; } 1064022Sstever@eecs.umich.edu 10710885Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 10810885Sandreas.hansson@arm.com * proper status to start fetching. */ 1094626Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1104626Sstever@eecs.umich.edu 1117669Ssteve.reinhardt@amd.com /** Handles doing a retry of a failed fetch. */ 1124626Sstever@eecs.umich.edu virtual void recvRetry(); 1134040Ssaidi@eecs.umich.edu }; 1144040Ssaidi@eecs.umich.edu 1155650Sgblack@eecs.umich.edu 1165650Sgblack@eecs.umich.edu public: 11711256Santhony.gutierrez@amd.com /** Overall fetch status. Used to determine if the CPU can 11811256Santhony.gutierrez@amd.com * deschedule itsef due to a lack of activity. 11912347Snikos.nikoleris@arm.com */ 12012347Snikos.nikoleris@arm.com enum FetchStatus { 12112347Snikos.nikoleris@arm.com Active, 12212347Snikos.nikoleris@arm.com Inactive 1234870Sstever@eecs.umich.edu }; 1244870Sstever@eecs.umich.edu 1254870Sstever@eecs.umich.edu /** Individual thread status. */ 1264870Sstever@eecs.umich.edu enum ThreadStatus { 1274870Sstever@eecs.umich.edu Running, 1284870Sstever@eecs.umich.edu Idle, 1298436SBrad.Beckmann@amd.com Squashing, 1308436SBrad.Beckmann@amd.com Blocked, 1315314Sstever@gmail.com Fetching, 1325314Sstever@gmail.com TrapPending, 1338184Ssomayeh@cs.wisc.edu QuiescePending, 13410886Sandreas.hansson@arm.com SwitchOut, 13510886Sandreas.hansson@arm.com IcacheWaitResponse, 1364022Sstever@eecs.umich.edu IcacheWaitRetry, 1374022Sstever@eecs.umich.edu IcacheAccessComplete 1384022Sstever@eecs.umich.edu }; 1394022Sstever@eecs.umich.edu 1405735Snate@binkert.org /** Fetching Policy, Add new policies here.*/ 1415735Snate@binkert.org enum FetchPriority { 1425735Snate@binkert.org SingleThread, 1434022Sstever@eecs.umich.edu RoundRobin, 1444022Sstever@eecs.umich.edu Branch, 1454626Sstever@eecs.umich.edu IQ, 1464626Sstever@eecs.umich.edu LSQ 1477465Ssteve.reinhardt@amd.com }; 1484022Sstever@eecs.umich.edu 14912347Snikos.nikoleris@arm.com private: 15011284Sandreas.hansson@arm.com /** Fetch status. */ 1514626Sstever@eecs.umich.edu FetchStatus _status; 1524626Sstever@eecs.umich.edu 1534626Sstever@eecs.umich.edu /** Per-thread status. */ 15411199Sandreas.hansson@arm.com ThreadStatus fetchStatus[Impl::MaxThreads]; 1554022Sstever@eecs.umich.edu 1564022Sstever@eecs.umich.edu /** Fetch policy. */ 1576076Sgblack@eecs.umich.edu FetchPriority fetchPolicy; 1584626Sstever@eecs.umich.edu 1594870Sstever@eecs.umich.edu /** List that has the threads organized by priority. */ 1605314Sstever@gmail.com std::list<ThreadID> priorityList; 1618184Ssomayeh@cs.wisc.edu 16211600Sandreas.hansson@arm.com public: 1634022Sstever@eecs.umich.edu /** DefaultFetch constructor. */ 1644022Sstever@eecs.umich.edu DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 1654022Sstever@eecs.umich.edu 1665735Snate@binkert.org /** Returns the name of fetch. */ 1675735Snate@binkert.org std::string name() const; 1685735Snate@binkert.org 1695735Snate@binkert.org /** Registers statistics. */ 1705735Snate@binkert.org void regStats(); 1715735Snate@binkert.org 1725735Snate@binkert.org /** Returns the icache port. */ 1734022Sstever@eecs.umich.edu Port *getIcachePort() { return icachePort; } 1745735Snate@binkert.org 1755735Snate@binkert.org /** Sets the main backwards communication time buffer pointer. */ 1764022Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 1775735Snate@binkert.org 1784022Sstever@eecs.umich.edu /** Sets pointer to list of active threads. */ 1794022Sstever@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 1804022Sstever@eecs.umich.edu 1815735Snate@binkert.org /** Sets pointer to time buffer used to communicate to the next stage. */ 1824022Sstever@eecs.umich.edu void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1834022Sstever@eecs.umich.edu 1844022Sstever@eecs.umich.edu /** Initialize stage. */ 1854022Sstever@eecs.umich.edu void initStage(); 1864022Sstever@eecs.umich.edu 1874022Sstever@eecs.umich.edu /** Tells the fetch stage that the Icache is set. */ 1885735Snate@binkert.org void setIcache(); 1895735Snate@binkert.org 1905735Snate@binkert.org /** Processes cache completion event. */ 1914022Sstever@eecs.umich.edu void processCacheCompletion(PacketPtr pkt); 1924022Sstever@eecs.umich.edu 1934022Sstever@eecs.umich.edu /** Begins the drain of the fetch stage. */ 1944022Sstever@eecs.umich.edu bool drain(); 1954022Sstever@eecs.umich.edu 19610583SCurtis.Dunham@arm.com /** Resumes execution after a drain. */ 19710583SCurtis.Dunham@arm.com void resume(); 19810583SCurtis.Dunham@arm.com 19910583SCurtis.Dunham@arm.com /** Tells fetch stage to prepare to be switched out. */ 20010583SCurtis.Dunham@arm.com void switchOut(); 20111284Sandreas.hansson@arm.com 20210583SCurtis.Dunham@arm.com /** Takes over from another CPU's thread. */ 20310583SCurtis.Dunham@arm.com void takeOverFrom(); 20411199Sandreas.hansson@arm.com 20512347Snikos.nikoleris@arm.com /** Checks if the fetch stage is switched out. */ 20611600Sandreas.hansson@arm.com bool isSwitchedOut() { return switchedOut; } 20711199Sandreas.hansson@arm.com 20811199Sandreas.hansson@arm.com /** Tells fetch to wake up from a quiesce instruction. */ 20911199Sandreas.hansson@arm.com void wakeFromQuiesce(); 21011199Sandreas.hansson@arm.com 21111199Sandreas.hansson@arm.com private: 21211199Sandreas.hansson@arm.com /** Changes the status of this stage to active, and indicates this 21310570Sandreas.hansson@arm.com * to the CPU. 21410570Sandreas.hansson@arm.com */ 21510570Sandreas.hansson@arm.com inline void switchToActive(); 21610570Sandreas.hansson@arm.com 21710570Sandreas.hansson@arm.com /** Changes the status of this stage to inactive, and indicates 21810570Sandreas.hansson@arm.com * this to the CPU. 2194022Sstever@eecs.umich.edu */ 2206102Sgblack@eecs.umich.edu inline void switchToInactive(); 22110343SCurtis.Dunham@arm.com 22210343SCurtis.Dunham@arm.com /** 22310343SCurtis.Dunham@arm.com * Looks up in the branch predictor to see if the next PC should be 22410343SCurtis.Dunham@arm.com * either next PC+=MachInst or a branch target. 2254870Sstever@eecs.umich.edu * @param next_PC Next PC variable passed in by reference. It is 2265314Sstever@gmail.com * expected to be set to the current PC; it will be updated with what 2278184Ssomayeh@cs.wisc.edu * the next PC will be. 2284022Sstever@eecs.umich.edu * @param next_NPC Used for ISAs which use delay slots. 22911294Sandreas.hansson@arm.com * @return Whether or not a branch was predicted as taken. 2305735Snate@binkert.org */ 2315735Snate@binkert.org bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC, Addr &next_MicroPC); 2324022Sstever@eecs.umich.edu 2334022Sstever@eecs.umich.edu /** 2344022Sstever@eecs.umich.edu * Fetches the cache line that contains fetch_PC. Returns any 2355735Snate@binkert.org * fault that happened. Puts the data into the class variable 2365735Snate@binkert.org * cacheData. 2374022Sstever@eecs.umich.edu * @param fetch_PC The PC address that is being fetched from. 2384022Sstever@eecs.umich.edu * @param ret_fault The fault reference that will be set to the result of 2395735Snate@binkert.org * the icache access. 2405735Snate@binkert.org * @param tid Thread id. 2415735Snate@binkert.org * @return Any fault that occured. 2424022Sstever@eecs.umich.edu */ 2435735Snate@binkert.org bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid); 2445735Snate@binkert.org 2454022Sstever@eecs.umich.edu /** Squashes a specific thread and resets the PC. */ 2464022Sstever@eecs.umich.edu inline void doSquash(const Addr &new_PC, const Addr &new_NPC, 2472381SN/A const Addr &new_MicroPC, ThreadID tid); 2482662Sstever@eecs.umich.edu 2492662Sstever@eecs.umich.edu /** Squashes a specific thread and resets the PC. Also tells the CPU to 2502662Sstever@eecs.umich.edu * remove any instructions between fetch and decode that should be sqaushed. 2512662Sstever@eecs.umich.edu */ 2522662Sstever@eecs.umich.edu void squashFromDecode(const Addr &new_PC, const Addr &new_NPC, 2532381SN/A const Addr &new_MicroPC, 2549044SAli.Saidi@ARM.com const InstSeqNum &seq_num, ThreadID tid); 2552381SN/A 2562813Srdreslin@umich.edu /** Checks if a thread is stalled. */ 2575735Snate@binkert.org bool checkStall(ThreadID tid) const; 2585735Snate@binkert.org 2594022Sstever@eecs.umich.edu /** Updates overall fetch stage status; to be called at the end of each 2605735Snate@binkert.org * cycle. */ 2615735Snate@binkert.org FetchStatus updateFetchStatus(); 26210938Sandreas.hansson@arm.com 26310938Sandreas.hansson@arm.com public: 26412349Snikos.nikoleris@arm.com /** Squashes a specific thread and resets the PC. Also tells the CPU to 26510938Sandreas.hansson@arm.com * remove any instructions that are not in the ROB. The source of this 26611284Sandreas.hansson@arm.com * squash should be the commit stage. 26711284Sandreas.hansson@arm.com */ 26811284Sandreas.hansson@arm.com void squash(const Addr &new_PC, const Addr &new_NPC, 26911284Sandreas.hansson@arm.com const Addr &new_MicroPC, 27010938Sandreas.hansson@arm.com const InstSeqNum &seq_num, ThreadID tid); 27110938Sandreas.hansson@arm.com 27210938Sandreas.hansson@arm.com /** Ticks the fetch stage, processing all inputs signals and fetching 27311284Sandreas.hansson@arm.com * as many instructions as possible. 27411284Sandreas.hansson@arm.com */ 27511284Sandreas.hansson@arm.com void tick(); 27611284Sandreas.hansson@arm.com 27711284Sandreas.hansson@arm.com /** Checks all input signals and updates the status as necessary. 27811284Sandreas.hansson@arm.com * @return: Returns if the status has changed due to input signals. 27911284Sandreas.hansson@arm.com */ 28011284Sandreas.hansson@arm.com bool checkSignalsAndUpdate(ThreadID tid); 28111284Sandreas.hansson@arm.com 28210938Sandreas.hansson@arm.com /** Does the actual fetching of instructions and passing them on to the 28312346Snikos.nikoleris@arm.com * next stage. 28412346Snikos.nikoleris@arm.com * @param status_change fetch() sets this variable if there was a status 28512346Snikos.nikoleris@arm.com * change (ie switching to IcacheMissStall). 28612346Snikos.nikoleris@arm.com */ 28712349Snikos.nikoleris@arm.com void fetch(bool &status_change); 28812349Snikos.nikoleris@arm.com 28912349Snikos.nikoleris@arm.com /** Align a PC to the start of an I-cache block. */ 29012349Snikos.nikoleris@arm.com Addr icacheBlockAlignPC(Addr addr) 29111057Sandreas.hansson@arm.com { 29211057Sandreas.hansson@arm.com addr = TheISA::realPCToFetchPC(addr); 29311057Sandreas.hansson@arm.com return (addr & ~(cacheBlkMask)); 29411057Sandreas.hansson@arm.com } 29510938Sandreas.hansson@arm.com 29610938Sandreas.hansson@arm.com private: 29710938Sandreas.hansson@arm.com /** Handles retrying the fetch access. */ 29810938Sandreas.hansson@arm.com void recvRetry(); 29910938Sandreas.hansson@arm.com 30010938Sandreas.hansson@arm.com /** Returns the appropriate thread to fetch, given the fetch policy. */ 30110938Sandreas.hansson@arm.com ThreadID getFetchingThread(FetchPriority &fetch_priority); 30210938Sandreas.hansson@arm.com 30310938Sandreas.hansson@arm.com /** Returns the appropriate thread to fetch using a round robin policy. */ 30410938Sandreas.hansson@arm.com ThreadID roundRobin(); 30510938Sandreas.hansson@arm.com 30610938Sandreas.hansson@arm.com /** Returns the appropriate thread to fetch using the IQ count policy. */ 30710938Sandreas.hansson@arm.com ThreadID iqCount(); 30810938Sandreas.hansson@arm.com 30910938Sandreas.hansson@arm.com /** Returns the appropriate thread to fetch using the LSQ count policy. */ 31010938Sandreas.hansson@arm.com ThreadID lsqCount(); 3115735Snate@binkert.org 3125735Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 3135735Snate@binkert.org * policy. */ 3145735Snate@binkert.org ThreadID branchCount(); 3154022Sstever@eecs.umich.edu 3164022Sstever@eecs.umich.edu private: 3175735Snate@binkert.org /** Pointer to the O3CPU. */ 3184870Sstever@eecs.umich.edu O3CPU *cpu; 3194870Sstever@eecs.umich.edu 32012351Snikos.nikoleris@arm.com /** Time buffer interface. */ 32112351Snikos.nikoleris@arm.com TimeBuffer<TimeStruct> *timeBuffer; 3225735Snate@binkert.org 32312749Sgiacomo.travaglini@arm.com /** Wire to get decode's information from backwards time buffer. */ 3244870Sstever@eecs.umich.edu typename TimeBuffer<TimeStruct>::wire fromDecode; 3252566SN/A 3265735Snate@binkert.org /** Wire to get rename's information from backwards time buffer. */ 32712633Sodanrc@yahoo.com.br typename TimeBuffer<TimeStruct>::wire fromRename; 32812633Sodanrc@yahoo.com.br 3295735Snate@binkert.org /** Wire to get iew's information from backwards time buffer. */ 33012633Sodanrc@yahoo.com.br typename TimeBuffer<TimeStruct>::wire fromIEW; 3315735Snate@binkert.org 3322566SN/A /** Wire to get commit's information from backwards time buffer. */ 3332566SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3342566SN/A 3355735Snate@binkert.org /** Internal fetch instruction queue. */ 3365735Snate@binkert.org TimeBuffer<FetchStruct> *fetchQueue; 3372381SN/A 3382381SN/A //Might be annoying how this name is different than the queue. 33910028SGiacomo.Gabrielli@arm.com /** Wire used to write any information heading to decode. */ 34010028SGiacomo.Gabrielli@arm.com typename TimeBuffer<FetchStruct>::wire toDecode; 34110028SGiacomo.Gabrielli@arm.com 3425735Snate@binkert.org /** Icache interface. */ 3436227Snate@binkert.org IcachePort *icachePort; 3442381SN/A 3455735Snate@binkert.org /** BPredUnit. */ 34610723Sandreas.hansson@arm.com BPredUnit branchPred; 3478668Sgeoffrey.blake@arm.com 34810723Sandreas.hansson@arm.com /** Predecoder. */ 3498668Sgeoffrey.blake@arm.com TheISA::Predecoder predecoder; 3502641Sstever@eecs.umich.edu 3512811Srdreslin@umich.edu /** Per-thread fetch PC. */ 3529547Sandreas.hansson@arm.com Addr PC[Impl::MaxThreads]; 35310694SMarco.Balboni@ARM.com 35410405Sandreas.hansson@arm.com /** Per-thread fetch micro PC. */ 35510405Sandreas.hansson@arm.com Addr microPC[Impl::MaxThreads]; 35610405Sandreas.hansson@arm.com 35710405Sandreas.hansson@arm.com /** Per-thread next PC. */ 3589547Sandreas.hansson@arm.com Addr nextPC[Impl::MaxThreads]; 35910694SMarco.Balboni@ARM.com 3603218Sgblack@eecs.umich.edu /** Memory request used to access cache. */ 3619547Sandreas.hansson@arm.com RequestPtr memReq[Impl::MaxThreads]; 36211127Sandreas.hansson@arm.com 36311127Sandreas.hansson@arm.com /** Variable that tracks if fetch has written to the time buffer this 36411127Sandreas.hansson@arm.com * cycle. Used to tell CPU if there is activity this cycle. 36511127Sandreas.hansson@arm.com */ 36611127Sandreas.hansson@arm.com bool wroteToTimeBuffer; 36711127Sandreas.hansson@arm.com 36811127Sandreas.hansson@arm.com /** Tracks how many instructions has been fetched this cycle. */ 36911127Sandreas.hansson@arm.com int numInst; 37010694SMarco.Balboni@ARM.com 37110694SMarco.Balboni@ARM.com /** Source of possible stalls. */ 37210694SMarco.Balboni@ARM.com struct Stalls { 37310694SMarco.Balboni@ARM.com bool decode; 37410405Sandreas.hansson@arm.com bool rename; 37510405Sandreas.hansson@arm.com bool iew; 3769547Sandreas.hansson@arm.com bool commit; 37710694SMarco.Balboni@ARM.com }; 3783218Sgblack@eecs.umich.edu 3795735Snate@binkert.org /** Tracks which stages are telling fetch to stall. */ 3805735Snate@binkert.org Stalls stalls[Impl::MaxThreads]; 3819542Sandreas.hansson@arm.com 3829542Sandreas.hansson@arm.com /** Decode to fetch delay, in ticks. */ 3839542Sandreas.hansson@arm.com unsigned decodeToFetchDelay; 3849542Sandreas.hansson@arm.com 3859542Sandreas.hansson@arm.com /** Rename to fetch delay, in ticks. */ 3869542Sandreas.hansson@arm.com unsigned renameToFetchDelay; 3879542Sandreas.hansson@arm.com 3889542Sandreas.hansson@arm.com /** IEW to fetch delay, in ticks. */ 3899542Sandreas.hansson@arm.com unsigned iewToFetchDelay; 3909542Sandreas.hansson@arm.com 3919542Sandreas.hansson@arm.com /** Commit to fetch delay, in ticks. */ 3929542Sandreas.hansson@arm.com unsigned commitToFetchDelay; 3939542Sandreas.hansson@arm.com 3949542Sandreas.hansson@arm.com /** The width of fetch in instructions. */ 3955735Snate@binkert.org unsigned fetchWidth; 3965735Snate@binkert.org 3975735Snate@binkert.org /** Is the cache blocked? If so no threads can access it. */ 3989542Sandreas.hansson@arm.com bool cacheBlocked; 3999542Sandreas.hansson@arm.com 4002641Sstever@eecs.umich.edu /** The packet that is waiting to be retried. */ 4012641Sstever@eecs.umich.edu PacketPtr retryPkt; 4022641Sstever@eecs.umich.edu 4035315Sstever@gmail.com /** The thread that is waiting on the cache to tell fetch to retry. */ 4045315Sstever@gmail.com ThreadID retryTid; 4055315Sstever@gmail.com 4065315Sstever@gmail.com /** Cache block size. */ 4079044SAli.Saidi@ARM.com int cacheBlkSize; 4085735Snate@binkert.org 4095735Snate@binkert.org /** Mask to get a cache block's address. */ 4105735Snate@binkert.org Addr cacheBlkMask; 4115735Snate@binkert.org 4125735Snate@binkert.org /** The cache line being fetched. */ 4135735Snate@binkert.org uint8_t *cacheData[Impl::MaxThreads]; 4145735Snate@binkert.org 4155314Sstever@gmail.com /** The PC of the cacheline that has been loaded. */ 4165314Sstever@gmail.com Addr cacheDataPC[Impl::MaxThreads]; 4175314Sstever@gmail.com 4185735Snate@binkert.org /** Whether or not the cache data is valid. */ 4195314Sstever@gmail.com bool cacheDataValid[Impl::MaxThreads]; 4205314Sstever@gmail.com 4215314Sstever@gmail.com /** Size of instructions. */ 4225314Sstever@gmail.com int instSize; 4235314Sstever@gmail.com 4245314Sstever@gmail.com /** Icache stall statistics. */ 4255314Sstever@gmail.com Counter lastIcacheStall[Impl::MaxThreads]; 4265314Sstever@gmail.com 4275314Sstever@gmail.com /** List of Active Threads */ 4285314Sstever@gmail.com std::list<ThreadID> *activeThreads; 4295314Sstever@gmail.com 4305314Sstever@gmail.com /** Number of threads. */ 4315314Sstever@gmail.com ThreadID numThreads; 4325314Sstever@gmail.com 4335735Snate@binkert.org /** Number of threads that are actively fetching. */ 4345735Snate@binkert.org ThreadID numFetchingThreads; 4355735Snate@binkert.org 4365314Sstever@gmail.com /** Thread ID being fetched. */ 4375315Sstever@gmail.com ThreadID threadFetched; 4385735Snate@binkert.org 4395735Snate@binkert.org /** Checks if there is an interrupt pending. If there is, fetch 4405315Sstever@gmail.com * must stop once it is not fetching PAL instructions. 4415735Snate@binkert.org */ 4425735Snate@binkert.org bool interruptPending; 4435314Sstever@gmail.com 4445314Sstever@gmail.com /** Is there a drain pending. */ 4455735Snate@binkert.org bool drainPending; 4465735Snate@binkert.org 4475735Snate@binkert.org /** Records if fetch is switched out. */ 4485735Snate@binkert.org bool switchedOut; 4495314Sstever@gmail.com 4505735Snate@binkert.org // @todo: Consider making these vectors and tracking on a per thread basis. 4515735Snate@binkert.org /** Stat for total number of cycles stalled due to an icache miss. */ 4525735Snate@binkert.org Stats::Scalar icacheStallCycles; 4535315Sstever@gmail.com /** Stat for total number of fetched instructions. */ 4545735Snate@binkert.org Stats::Scalar fetchedInsts; 4555735Snate@binkert.org /** Total number of fetched branches. */ 4565314Sstever@gmail.com Stats::Scalar fetchedBranches; 4575735Snate@binkert.org /** Stat for total number of predicted branches. */ 4585735Snate@binkert.org Stats::Scalar predictedBranches; 4595735Snate@binkert.org /** Stat for total number of cycles spent fetching. */ 4605735Snate@binkert.org Stats::Scalar fetchCycles; 4615735Snate@binkert.org /** Stat for total number of cycles spent squashing. */ 4625314Sstever@gmail.com Stats::Scalar fetchSquashCycles; 4635314Sstever@gmail.com /** Stat for total number of cycles spent blocked due to other stages in 4645314Sstever@gmail.com * the pipeline. 4655735Snate@binkert.org */ 4665735Snate@binkert.org Stats::Scalar fetchIdleCycles; 4675735Snate@binkert.org /** Total number of cycles spent blocked. */ 4685735Snate@binkert.org Stats::Scalar fetchBlockedCycles; 4699542Sandreas.hansson@arm.com /** Total number of cycles spent in any other state. */ 4705735Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 4715735Snate@binkert.org /** Stat for total number of fetched cache lines. */ 4725735Snate@binkert.org Stats::Scalar fetchedCacheLines; 4732662Sstever@eecs.umich.edu /** Total number of outstanding icache accesses that were dropped 4742641Sstever@eecs.umich.edu * due to a squash. 4759542Sandreas.hansson@arm.com */ 4769542Sandreas.hansson@arm.com Stats::Scalar fetchIcacheSquashes; 4779542Sandreas.hansson@arm.com /** Distribution of number of instructions fetched each cycle. */ 4789542Sandreas.hansson@arm.com Stats::Distribution fetchNisnDist; 4799542Sandreas.hansson@arm.com /** Rate of how often fetch was idle. */ 4809542Sandreas.hansson@arm.com Stats::Formula idleRate; 4819542Sandreas.hansson@arm.com /** Number of branch fetches per cycle. */ 4829542Sandreas.hansson@arm.com Stats::Formula branchRate; 4839542Sandreas.hansson@arm.com /** Number of instruction fetched per cycle. */ 4849542Sandreas.hansson@arm.com Stats::Formula fetchRate; 4859542Sandreas.hansson@arm.com}; 4869542Sandreas.hansson@arm.com 4879542Sandreas.hansson@arm.com#endif //__CPU_O3_FETCH_HH__ 4889542Sandreas.hansson@arm.com