fetch.hh revision 2698
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#ifndef __CPU_O3_FETCH_HH__ 322292SN/A#define __CPU_O3_FETCH_HH__ 331060SN/A 342669Sktlim@umich.edu#include "arch/utility.hh" 351461SN/A#include "base/statistics.hh" 361060SN/A#include "base/timebuf.hh" 371060SN/A#include "cpu/pc_event.hh" 382669Sktlim@umich.edu#include "mem/packet.hh" 392669Sktlim@umich.edu#include "mem/port.hh" 401461SN/A#include "sim/eventq.hh" 411060SN/A 422307SN/Aclass Sampler; 432307SN/A 441060SN/A/** 452329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 462329SN/A * width is specified by the parameters; each cycle it tries to fetch 472329SN/A * that many instructions. It supports using a branch predictor to 482329SN/A * predict direction and targets. 492348SN/A * It supports the idling functionality of the CPU by indicating to 502329SN/A * the CPU when it is active and inactive. 511060SN/A */ 521060SN/Atemplate <class Impl> 532292SN/Aclass DefaultFetch 541060SN/A{ 551060SN/A public: 561060SN/A /** Typedefs from Impl. */ 571061SN/A typedef typename Impl::CPUPol CPUPol; 581060SN/A typedef typename Impl::DynInst DynInst; 591061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 601060SN/A typedef typename Impl::FullCPU FullCPU; 611060SN/A typedef typename Impl::Params Params; 621060SN/A 632292SN/A /** Typedefs from the CPU policy. */ 641061SN/A typedef typename CPUPol::BPredUnit BPredUnit; 651061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 661061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 671060SN/A 681060SN/A /** Typedefs from ISA. */ 692107SN/A typedef TheISA::MachInst MachInst; 702292SN/A typedef TheISA::ExtMachInst ExtMachInst; 712632Sstever@eecs.umich.edu 722698Sktlim@umich.edu /** IcachePort class for DefaultFetch. Handles doing the 732698Sktlim@umich.edu * communication with the cache/memory. 742698Sktlim@umich.edu */ 752669Sktlim@umich.edu class IcachePort : public Port 762669Sktlim@umich.edu { 772669Sktlim@umich.edu protected: 782698Sktlim@umich.edu /** Pointer to fetch. */ 792669Sktlim@umich.edu DefaultFetch<Impl> *fetch; 802669Sktlim@umich.edu 812669Sktlim@umich.edu public: 822698Sktlim@umich.edu /** Default constructor. */ 832669Sktlim@umich.edu IcachePort(DefaultFetch<Impl> *_fetch) 842669Sktlim@umich.edu : Port(_fetch->name() + "-iport"), fetch(_fetch) 852669Sktlim@umich.edu { } 862669Sktlim@umich.edu 872669Sktlim@umich.edu protected: 882698Sktlim@umich.edu /** Atomic version of receive. Panics. */ 892669Sktlim@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 902669Sktlim@umich.edu 912698Sktlim@umich.edu /** Functional version of receive. Panics. */ 922669Sktlim@umich.edu virtual void recvFunctional(PacketPtr pkt); 932669Sktlim@umich.edu 942698Sktlim@umich.edu /** Receives status change. Other than range changing, panics. */ 952669Sktlim@umich.edu virtual void recvStatusChange(Status status); 962669Sktlim@umich.edu 972698Sktlim@umich.edu /** Returns the address ranges of this device. */ 982669Sktlim@umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 992669Sktlim@umich.edu AddrRangeList &snoop) 1002669Sktlim@umich.edu { resp.clear(); snoop.clear(); } 1012669Sktlim@umich.edu 1022698Sktlim@umich.edu /** Timing version of receive. Handles setting fetch to the 1032698Sktlim@umich.edu * proper status to start fetching. */ 1042669Sktlim@umich.edu virtual bool recvTiming(PacketPtr pkt); 1052669Sktlim@umich.edu 1062698Sktlim@umich.edu /** Handles doing a retry of a failed fetch. */ 1072669Sktlim@umich.edu virtual void recvRetry(); 1082669Sktlim@umich.edu }; 1091060SN/A 1101060SN/A public: 1112329SN/A /** Overall fetch status. Used to determine if the CPU can 1122329SN/A * deschedule itsef due to a lack of activity. 1132292SN/A */ 1142292SN/A enum FetchStatus { 1152292SN/A Active, 1162292SN/A Inactive 1172292SN/A }; 1182292SN/A 1192292SN/A /** Individual thread status. */ 1202292SN/A enum ThreadStatus { 1211060SN/A Running, 1221060SN/A Idle, 1231060SN/A Squashing, 1241060SN/A Blocked, 1252292SN/A Fetching, 1262292SN/A TrapPending, 1272292SN/A QuiescePending, 1282307SN/A SwitchOut, 1292669Sktlim@umich.edu IcacheWaitResponse, 1302696Sktlim@umich.edu IcacheWaitRetry, 1312669Sktlim@umich.edu IcacheAccessComplete 1321060SN/A }; 1331060SN/A 1342292SN/A /** Fetching Policy, Add new policies here.*/ 1352292SN/A enum FetchPriority { 1362292SN/A SingleThread, 1372292SN/A RoundRobin, 1382292SN/A Branch, 1392292SN/A IQ, 1402292SN/A LSQ 1412292SN/A }; 1421060SN/A 1432292SN/A private: 1442292SN/A /** Fetch status. */ 1452292SN/A FetchStatus _status; 1462292SN/A 1472292SN/A /** Per-thread status. */ 1482292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1492292SN/A 1502292SN/A /** Fetch policy. */ 1512292SN/A FetchPriority fetchPolicy; 1522292SN/A 1532292SN/A /** List that has the threads organized by priority. */ 1542292SN/A std::list<unsigned> priorityList; 1551060SN/A 1561060SN/A public: 1572292SN/A /** DefaultFetch constructor. */ 1582292SN/A DefaultFetch(Params *params); 1591684SN/A 1602292SN/A /** Returns the name of fetch. */ 1612292SN/A std::string name() const; 1621684SN/A 1632292SN/A /** Registers statistics. */ 1641062SN/A void regStats(); 1651062SN/A 1662292SN/A /** Sets CPU pointer. */ 1671060SN/A void setCPU(FullCPU *cpu_ptr); 1681060SN/A 1692292SN/A /** Sets the main backwards communication time buffer pointer. */ 1701060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 1711060SN/A 1722292SN/A /** Sets pointer to list of active threads. */ 1732292SN/A void setActiveThreads(std::list<unsigned> *at_ptr); 1742292SN/A 1752292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 1761060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1771060SN/A 1782292SN/A /** Initialize stage. */ 1792292SN/A void initStage(); 1802292SN/A 1812292SN/A /** Processes cache completion event. */ 1822669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 1832292SN/A 1842348SN/A /** Begins the switch out of the fetch stage. */ 1852307SN/A void switchOut(); 1862307SN/A 1872348SN/A /** Completes the switch out of the fetch stage. */ 1882316SN/A void doSwitchOut(); 1892316SN/A 1902348SN/A /** Takes over from another CPU's thread. */ 1912307SN/A void takeOverFrom(); 1922307SN/A 1932348SN/A /** Checks if the fetch stage is switched out. */ 1942307SN/A bool isSwitchedOut() { return switchedOut; } 1952307SN/A 1962348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 1972292SN/A void wakeFromQuiesce(); 1981060SN/A 1991061SN/A private: 2002329SN/A /** Changes the status of this stage to active, and indicates this 2012329SN/A * to the CPU. 2022292SN/A */ 2032292SN/A inline void switchToActive(); 2042292SN/A 2052329SN/A /** Changes the status of this stage to inactive, and indicates 2062329SN/A * this to the CPU. 2072292SN/A */ 2082292SN/A inline void switchToInactive(); 2092292SN/A 2101061SN/A /** 2111061SN/A * Looks up in the branch predictor to see if the next PC should be 2121061SN/A * either next PC+=MachInst or a branch target. 2131763SN/A * @param next_PC Next PC variable passed in by reference. It is 2141061SN/A * expected to be set to the current PC; it will be updated with what 2151061SN/A * the next PC will be. 2161061SN/A * @return Whether or not a branch was predicted as taken. 2171061SN/A */ 2181062SN/A bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC); 2191062SN/A 2201062SN/A /** 2211062SN/A * Fetches the cache line that contains fetch_PC. Returns any 2221062SN/A * fault that happened. Puts the data into the class variable 2231062SN/A * cacheData. 2241763SN/A * @param fetch_PC The PC address that is being fetched from. 2252292SN/A * @param ret_fault The fault reference that will be set to the result of 2262292SN/A * the icache access. 2272292SN/A * @param tid Thread id. 2281062SN/A * @return Any fault that occured. 2291062SN/A */ 2302292SN/A bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid); 2311062SN/A 2322292SN/A /** Squashes a specific thread and resets the PC. */ 2332292SN/A inline void doSquash(const Addr &new_PC, unsigned tid); 2341684SN/A 2352292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2362292SN/A * remove any instructions between fetch and decode that should be sqaushed. 2372292SN/A */ 2382292SN/A void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num, 2392292SN/A unsigned tid); 2402292SN/A 2412292SN/A /** Checks if a thread is stalled. */ 2422292SN/A bool checkStall(unsigned tid) const; 2432292SN/A 2442292SN/A /** Updates overall fetch stage status; to be called at the end of each 2452292SN/A * cycle. */ 2462292SN/A FetchStatus updateFetchStatus(); 2471684SN/A 2481684SN/A public: 2492292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 2502292SN/A * remove any instructions that are not in the ROB. The source of this 2512292SN/A * squash should be the commit stage. 2522292SN/A */ 2532292SN/A void squash(const Addr &new_PC, unsigned tid); 2541684SN/A 2552292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 2562292SN/A * as many instructions as possible. 2572292SN/A */ 2581684SN/A void tick(); 2591684SN/A 2602292SN/A /** Checks all input signals and updates the status as necessary. 2612292SN/A * @return: Returns if the status has changed due to input signals. 2622292SN/A */ 2632292SN/A bool checkSignalsAndUpdate(unsigned tid); 2641684SN/A 2652292SN/A /** Does the actual fetching of instructions and passing them on to the 2662292SN/A * next stage. 2672292SN/A * @param status_change fetch() sets this variable if there was a status 2682292SN/A * change (ie switching to IcacheMissStall). 2692292SN/A */ 2702292SN/A void fetch(bool &status_change); 2712292SN/A 2722292SN/A /** Align a PC to the start of an I-cache block. */ 2731062SN/A Addr icacheBlockAlignPC(Addr addr) 2741062SN/A { 2752107SN/A addr = TheISA::realPCToFetchPC(addr); 2761062SN/A return (addr & ~(cacheBlkMask)); 2771062SN/A } 2781061SN/A 2791060SN/A private: 2802698Sktlim@umich.edu /** Handles retrying the fetch access. */ 2812696Sktlim@umich.edu void recvRetry(); 2822696Sktlim@umich.edu 2832292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 2842292SN/A int getFetchingThread(FetchPriority &fetch_priority); 2852292SN/A 2862292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 2872292SN/A int roundRobin(); 2882292SN/A 2892292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 2902292SN/A int iqCount(); 2912292SN/A 2922292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 2932292SN/A int lsqCount(); 2942292SN/A 2952292SN/A /** Returns the appropriate thread to fetch using the branch count policy. */ 2962292SN/A int branchCount(); 2972292SN/A 2982292SN/A private: 2991060SN/A /** Pointer to the FullCPU. */ 3001060SN/A FullCPU *cpu; 3011060SN/A 3021060SN/A /** Time buffer interface. */ 3031060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3041060SN/A 3051060SN/A /** Wire to get decode's information from backwards time buffer. */ 3061060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3071060SN/A 3081060SN/A /** Wire to get rename's information from backwards time buffer. */ 3091060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3101060SN/A 3111060SN/A /** Wire to get iew's information from backwards time buffer. */ 3121060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3131060SN/A 3141060SN/A /** Wire to get commit's information from backwards time buffer. */ 3151060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3161060SN/A 3171060SN/A /** Internal fetch instruction queue. */ 3181060SN/A TimeBuffer<FetchStruct> *fetchQueue; 3191060SN/A 3201060SN/A //Might be annoying how this name is different than the queue. 3211060SN/A /** Wire used to write any information heading to decode. */ 3221060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 3231060SN/A 3242669Sktlim@umich.edu MemObject *mem; 3252669Sktlim@umich.edu 3261060SN/A /** Icache interface. */ 3272669Sktlim@umich.edu IcachePort *icachePort; 3281060SN/A 3291061SN/A /** BPredUnit. */ 3301061SN/A BPredUnit branchPred; 3311061SN/A 3322348SN/A /** Per-thread fetch PC. */ 3332292SN/A Addr PC[Impl::MaxThreads]; 3342292SN/A 3352348SN/A /** Per-thread next PC. */ 3362292SN/A Addr nextPC[Impl::MaxThreads]; 3372292SN/A 3382678Sktlim@umich.edu /** Memory request used to access cache. */ 3392678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 3402292SN/A 3412292SN/A /** Variable that tracks if fetch has written to the time buffer this 3422292SN/A * cycle. Used to tell CPU if there is activity this cycle. 3432292SN/A */ 3442292SN/A bool wroteToTimeBuffer; 3452292SN/A 3462292SN/A /** Tracks how many instructions has been fetched this cycle. */ 3472292SN/A int numInst; 3482292SN/A 3492292SN/A /** Source of possible stalls. */ 3502292SN/A struct Stalls { 3512292SN/A bool decode; 3522292SN/A bool rename; 3532292SN/A bool iew; 3542292SN/A bool commit; 3552292SN/A }; 3562292SN/A 3572292SN/A /** Tracks which stages are telling fetch to stall. */ 3582292SN/A Stalls stalls[Impl::MaxThreads]; 3591060SN/A 3601060SN/A /** Decode to fetch delay, in ticks. */ 3611060SN/A unsigned decodeToFetchDelay; 3621060SN/A 3631060SN/A /** Rename to fetch delay, in ticks. */ 3641060SN/A unsigned renameToFetchDelay; 3651060SN/A 3661060SN/A /** IEW to fetch delay, in ticks. */ 3671060SN/A unsigned iewToFetchDelay; 3681060SN/A 3691060SN/A /** Commit to fetch delay, in ticks. */ 3701060SN/A unsigned commitToFetchDelay; 3711060SN/A 3721060SN/A /** The width of fetch in instructions. */ 3731060SN/A unsigned fetchWidth; 3741060SN/A 3752696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 3762696Sktlim@umich.edu bool cacheBlocked; 3772696Sktlim@umich.edu 3782696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 3792696Sktlim@umich.edu PacketPtr retryPkt; 3802696Sktlim@umich.edu 3812696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 3822696Sktlim@umich.edu int retryTid; 3832696Sktlim@umich.edu 3841060SN/A /** Cache block size. */ 3851062SN/A int cacheBlkSize; 3861060SN/A 3871060SN/A /** Mask to get a cache block's address. */ 3881062SN/A Addr cacheBlkMask; 3891060SN/A 3901062SN/A /** The cache line being fetched. */ 3912292SN/A uint8_t *cacheData[Impl::MaxThreads]; 3921060SN/A 3931060SN/A /** Size of instructions. */ 3941060SN/A int instSize; 3951060SN/A 3961060SN/A /** Icache stall statistics. */ 3972292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 3981062SN/A 3992292SN/A /** List of Active Threads */ 4002292SN/A std::list<unsigned> *activeThreads; 4012292SN/A 4022292SN/A /** Number of threads. */ 4032292SN/A unsigned numThreads; 4042292SN/A 4052292SN/A /** Number of threads that are actively fetching. */ 4062292SN/A unsigned numFetchingThreads; 4072292SN/A 4082292SN/A /** Thread ID being fetched. */ 4092292SN/A int threadFetched; 4102292SN/A 4112348SN/A /** Checks if there is an interrupt pending. If there is, fetch 4122348SN/A * must stop once it is not fetching PAL instructions. 4132348SN/A */ 4142292SN/A bool interruptPending; 4152292SN/A 4162348SN/A /** Records if fetch is switched out. */ 4172307SN/A bool switchedOut; 4182307SN/A 4192292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 4202292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 4211062SN/A Stats::Scalar<> icacheStallCycles; 4222292SN/A /** Stat for total number of fetched instructions. */ 4231062SN/A Stats::Scalar<> fetchedInsts; 4242301SN/A Stats::Scalar<> fetchedBranches; 4252292SN/A /** Stat for total number of predicted branches. */ 4261062SN/A Stats::Scalar<> predictedBranches; 4272292SN/A /** Stat for total number of cycles spent fetching. */ 4281062SN/A Stats::Scalar<> fetchCycles; 4292292SN/A /** Stat for total number of cycles spent squashing. */ 4301062SN/A Stats::Scalar<> fetchSquashCycles; 4312292SN/A /** Stat for total number of cycles spent blocked due to other stages in 4322292SN/A * the pipeline. 4332292SN/A */ 4342292SN/A Stats::Scalar<> fetchIdleCycles; 4352348SN/A /** Total number of cycles spent blocked. */ 4361062SN/A Stats::Scalar<> fetchBlockedCycles; 4372348SN/A /** Total number of cycles spent in any other state. */ 4382307SN/A Stats::Scalar<> fetchMiscStallCycles; 4392292SN/A /** Stat for total number of fetched cache lines. */ 4401062SN/A Stats::Scalar<> fetchedCacheLines; 4412348SN/A /** Total number of outstanding icache accesses that were dropped 4422348SN/A * due to a squash. 4432348SN/A */ 4442301SN/A Stats::Scalar<> fetchIcacheSquashes; 4452292SN/A /** Distribution of number of instructions fetched each cycle. */ 4462292SN/A Stats::Distribution<> fetchNisnDist; 4472348SN/A /** Rate of how often fetch was idle. */ 4482292SN/A Stats::Formula idleRate; 4492348SN/A /** Number of branch fetches per cycle. */ 4502292SN/A Stats::Formula branchRate; 4512348SN/A /** Number of instruction fetched per cycle. */ 4522292SN/A Stats::Formula fetchRate; 4531060SN/A}; 4541060SN/A 4552292SN/A#endif //__CPU_O3_FETCH_HH__ 456