fetch.hh revision 2665
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311684SN/A// Todo: SMT fetch, 321684SN/A// Add a way to get a stage's current status. 331060SN/A 341755SN/A#ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__ 351755SN/A#define __CPU_O3_CPU_SIMPLE_FETCH_HH__ 361060SN/A 371461SN/A#include "base/statistics.hh" 381060SN/A#include "base/timebuf.hh" 391060SN/A#include "cpu/pc_event.hh" 401060SN/A#include "mem/mem_interface.hh" 411461SN/A#include "sim/eventq.hh" 421060SN/A 431060SN/A/** 441060SN/A * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch 451060SN/A * will stall if there's an Icache miss, but otherwise assumes a one cycle 461061SN/A * Icache hit. 471060SN/A */ 481060SN/A 491060SN/Atemplate <class Impl> 501060SN/Aclass SimpleFetch 511060SN/A{ 521060SN/A public: 531060SN/A /** Typedefs from Impl. */ 541061SN/A typedef typename Impl::CPUPol CPUPol; 551060SN/A typedef typename Impl::DynInst DynInst; 561061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 571060SN/A typedef typename Impl::FullCPU FullCPU; 581060SN/A typedef typename Impl::Params Params; 591060SN/A 601061SN/A typedef typename CPUPol::BPredUnit BPredUnit; 611061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 621061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 631060SN/A 641060SN/A /** Typedefs from ISA. */ 652107SN/A typedef TheISA::MachInst MachInst; 661060SN/A 671060SN/A public: 681060SN/A enum Status { 691060SN/A Running, 701060SN/A Idle, 711060SN/A Squashing, 721060SN/A Blocked, 731060SN/A IcacheMissStall, 741060SN/A IcacheMissComplete 751060SN/A }; 761060SN/A 771060SN/A // May eventually need statuses on a per thread basis. 781060SN/A Status _status; 791060SN/A 801060SN/A bool stalled; 811060SN/A 821060SN/A public: 831684SN/A class CacheCompletionEvent : public Event 841684SN/A { 851684SN/A private: 861684SN/A SimpleFetch *fetch; 871684SN/A 881684SN/A public: 891684SN/A CacheCompletionEvent(SimpleFetch *_fetch); 901684SN/A 911684SN/A virtual void process(); 921684SN/A virtual const char *description(); 931684SN/A }; 941684SN/A 951684SN/A public: 961060SN/A /** SimpleFetch constructor. */ 971060SN/A SimpleFetch(Params ¶ms); 981060SN/A 991062SN/A void regStats(); 1001062SN/A 1011060SN/A void setCPU(FullCPU *cpu_ptr); 1021060SN/A 1031060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 1041060SN/A 1051060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1061060SN/A 1071060SN/A void processCacheCompletion(); 1081060SN/A 1091061SN/A private: 1101061SN/A /** 1111061SN/A * Looks up in the branch predictor to see if the next PC should be 1121061SN/A * either next PC+=MachInst or a branch target. 1131763SN/A * @param next_PC Next PC variable passed in by reference. It is 1141061SN/A * expected to be set to the current PC; it will be updated with what 1151061SN/A * the next PC will be. 1161061SN/A * @return Whether or not a branch was predicted as taken. 1171061SN/A */ 1181062SN/A bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC); 1191062SN/A 1201062SN/A /** 1211062SN/A * Fetches the cache line that contains fetch_PC. Returns any 1221062SN/A * fault that happened. Puts the data into the class variable 1231062SN/A * cacheData. 1241763SN/A * @param fetch_PC The PC address that is being fetched from. 1251062SN/A * @return Any fault that occured. 1261062SN/A */ 1272132SN/A Fault fetchCacheLine(Addr fetch_PC); 1281062SN/A 1291684SN/A inline void doSquash(const Addr &new_PC); 1301684SN/A 1311684SN/A void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num); 1321684SN/A 1331684SN/A public: 1341684SN/A // Figure out PC vs next PC and how it should be updated 1351684SN/A void squash(const Addr &new_PC); 1361684SN/A 1371684SN/A void tick(); 1381684SN/A 1391684SN/A void fetch(); 1401684SN/A 1411062SN/A // Align an address (typically a PC) to the start of an I-cache block. 1421062SN/A // We fold in the PISA 64- to 32-bit conversion here as well. 1431062SN/A Addr icacheBlockAlignPC(Addr addr) 1441062SN/A { 1452107SN/A addr = TheISA::realPCToFetchPC(addr); 1461062SN/A return (addr & ~(cacheBlkMask)); 1471062SN/A } 1481061SN/A 1491060SN/A private: 1501060SN/A /** Pointer to the FullCPU. */ 1511060SN/A FullCPU *cpu; 1521060SN/A 1531060SN/A /** Time buffer interface. */ 1541060SN/A TimeBuffer<TimeStruct> *timeBuffer; 1551060SN/A 1561060SN/A /** Wire to get decode's information from backwards time buffer. */ 1571060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 1581060SN/A 1591060SN/A /** Wire to get rename's information from backwards time buffer. */ 1601060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 1611060SN/A 1621060SN/A /** Wire to get iew's information from backwards time buffer. */ 1631060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 1641060SN/A 1651060SN/A /** Wire to get commit's information from backwards time buffer. */ 1661060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 1671060SN/A 1681060SN/A /** Internal fetch instruction queue. */ 1691060SN/A TimeBuffer<FetchStruct> *fetchQueue; 1701060SN/A 1711060SN/A //Might be annoying how this name is different than the queue. 1721060SN/A /** Wire used to write any information heading to decode. */ 1731060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 1741060SN/A 1751060SN/A /** Icache interface. */ 1761060SN/A MemInterface *icacheInterface; 1771060SN/A 1781061SN/A /** BPredUnit. */ 1791061SN/A BPredUnit branchPred; 1801061SN/A 1811060SN/A /** Memory request used to access cache. */ 1821060SN/A MemReqPtr memReq; 1831060SN/A 1841060SN/A /** Decode to fetch delay, in ticks. */ 1851060SN/A unsigned decodeToFetchDelay; 1861060SN/A 1871060SN/A /** Rename to fetch delay, in ticks. */ 1881060SN/A unsigned renameToFetchDelay; 1891060SN/A 1901060SN/A /** IEW to fetch delay, in ticks. */ 1911060SN/A unsigned iewToFetchDelay; 1921060SN/A 1931060SN/A /** Commit to fetch delay, in ticks. */ 1941060SN/A unsigned commitToFetchDelay; 1951060SN/A 1961060SN/A /** The width of fetch in instructions. */ 1971060SN/A unsigned fetchWidth; 1981060SN/A 1991060SN/A /** Cache block size. */ 2001062SN/A int cacheBlkSize; 2011060SN/A 2021060SN/A /** Mask to get a cache block's address. */ 2031062SN/A Addr cacheBlkMask; 2041060SN/A 2051062SN/A /** The cache line being fetched. */ 2061062SN/A uint8_t *cacheData; 2071060SN/A 2081060SN/A /** Size of instructions. */ 2091060SN/A int instSize; 2101060SN/A 2111060SN/A /** Icache stall statistics. */ 2121062SN/A Counter lastIcacheStall; 2131062SN/A 2141062SN/A Stats::Scalar<> icacheStallCycles; 2151062SN/A Stats::Scalar<> fetchedInsts; 2161062SN/A Stats::Scalar<> predictedBranches; 2171062SN/A Stats::Scalar<> fetchCycles; 2181062SN/A Stats::Scalar<> fetchSquashCycles; 2191062SN/A Stats::Scalar<> fetchBlockedCycles; 2201062SN/A Stats::Scalar<> fetchedCacheLines; 2211062SN/A 2221062SN/A Stats::Distribution<> fetch_nisn_dist; 2231060SN/A}; 2241060SN/A 2251755SN/A#endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__ 226