fetch.hh revision 10329
11689SN/A/* 210329Smitch.hayenga@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited 37849SAli.Saidi@ARM.com * All rights reserved 47849SAli.Saidi@ARM.com * 57849SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67849SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77849SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87849SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97849SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107849SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117849SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127849SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137849SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_FETCH_HH__ 452292SN/A#define __CPU_O3_FETCH_HH__ 461060SN/A 479020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 482669Sktlim@umich.edu#include "arch/utility.hh" 491461SN/A#include "base/statistics.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 511060SN/A#include "cpu/pc_event.hh" 529480Snilay@cs.wisc.edu#include "cpu/pred/bpred_unit.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 547849SAli.Saidi@ARM.com#include "cpu/translation.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 562669Sktlim@umich.edu#include "mem/port.hh" 571461SN/A#include "sim/eventq.hh" 5810023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 591060SN/A 608737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 615529Snate@binkert.org 621060SN/A/** 632329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 642329SN/A * width is specified by the parameters; each cycle it tries to fetch 652329SN/A * that many instructions. It supports using a branch predictor to 662329SN/A * predict direction and targets. 672348SN/A * It supports the idling functionality of the CPU by indicating to 682329SN/A * the CPU when it is active and inactive. 691060SN/A */ 701060SN/Atemplate <class Impl> 712292SN/Aclass DefaultFetch 721060SN/A{ 731060SN/A public: 741060SN/A /** Typedefs from Impl. */ 751061SN/A typedef typename Impl::CPUPol CPUPol; 761060SN/A typedef typename Impl::DynInst DynInst; 771061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 782733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 791060SN/A 802292SN/A /** Typedefs from the CPU policy. */ 811061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 821061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 831060SN/A 841060SN/A /** Typedefs from ISA. */ 852107SN/A typedef TheISA::MachInst MachInst; 862292SN/A typedef TheISA::ExtMachInst ExtMachInst; 872632Sstever@eecs.umich.edu 887849SAli.Saidi@ARM.com class FetchTranslation : public BaseTLB::Translation 897849SAli.Saidi@ARM.com { 907849SAli.Saidi@ARM.com protected: 917849SAli.Saidi@ARM.com DefaultFetch<Impl> *fetch; 927849SAli.Saidi@ARM.com 937849SAli.Saidi@ARM.com public: 947849SAli.Saidi@ARM.com FetchTranslation(DefaultFetch<Impl> *_fetch) 957849SAli.Saidi@ARM.com : fetch(_fetch) 967849SAli.Saidi@ARM.com {} 977849SAli.Saidi@ARM.com 987849SAli.Saidi@ARM.com void 997944SGiacomo.Gabrielli@arm.com markDelayed() 1007944SGiacomo.Gabrielli@arm.com {} 1017944SGiacomo.Gabrielli@arm.com 1027944SGiacomo.Gabrielli@arm.com void 1037849SAli.Saidi@ARM.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 1047849SAli.Saidi@ARM.com BaseTLB::Mode mode) 1057849SAli.Saidi@ARM.com { 1067849SAli.Saidi@ARM.com assert(mode == BaseTLB::Execute); 1077849SAli.Saidi@ARM.com fetch->finishTranslation(fault, req); 1087849SAli.Saidi@ARM.com delete this; 1097849SAli.Saidi@ARM.com } 1107849SAli.Saidi@ARM.com }; 1112935Sksewell@umich.edu 1128462Sgeoffrey.blake@arm.com private: 1138462Sgeoffrey.blake@arm.com /* Event to delay delivery of a fetch translation result in case of 1148462Sgeoffrey.blake@arm.com * a fault and the nop to carry the fault cannot be generated 1158462Sgeoffrey.blake@arm.com * immediately */ 1168462Sgeoffrey.blake@arm.com class FinishTranslationEvent : public Event 1178462Sgeoffrey.blake@arm.com { 1188462Sgeoffrey.blake@arm.com private: 1198462Sgeoffrey.blake@arm.com DefaultFetch<Impl> *fetch; 1208462Sgeoffrey.blake@arm.com Fault fault; 1218462Sgeoffrey.blake@arm.com RequestPtr req; 1228462Sgeoffrey.blake@arm.com 1238462Sgeoffrey.blake@arm.com public: 1248462Sgeoffrey.blake@arm.com FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 1258462Sgeoffrey.blake@arm.com : fetch(_fetch) 1268462Sgeoffrey.blake@arm.com {} 1278462Sgeoffrey.blake@arm.com 1288462Sgeoffrey.blake@arm.com void setFault(Fault _fault) 1298462Sgeoffrey.blake@arm.com { 1308462Sgeoffrey.blake@arm.com fault = _fault; 1318462Sgeoffrey.blake@arm.com } 1328462Sgeoffrey.blake@arm.com 1338462Sgeoffrey.blake@arm.com void setReq(RequestPtr _req) 1348462Sgeoffrey.blake@arm.com { 1358462Sgeoffrey.blake@arm.com req = _req; 1368462Sgeoffrey.blake@arm.com } 1378462Sgeoffrey.blake@arm.com 1388462Sgeoffrey.blake@arm.com /** Process the delayed finish translation */ 1398462Sgeoffrey.blake@arm.com void process() 1408462Sgeoffrey.blake@arm.com { 1418462Sgeoffrey.blake@arm.com assert(fetch->numInst < fetch->fetchWidth); 1428462Sgeoffrey.blake@arm.com fetch->finishTranslation(fault, req); 1438462Sgeoffrey.blake@arm.com } 1448462Sgeoffrey.blake@arm.com 1458462Sgeoffrey.blake@arm.com const char *description() const 1468462Sgeoffrey.blake@arm.com { 1478462Sgeoffrey.blake@arm.com return "FullO3CPU FetchFinishTranslation"; 1488462Sgeoffrey.blake@arm.com } 1498462Sgeoffrey.blake@arm.com }; 1508462Sgeoffrey.blake@arm.com 1511060SN/A public: 1522329SN/A /** Overall fetch status. Used to determine if the CPU can 1532329SN/A * deschedule itsef due to a lack of activity. 1542292SN/A */ 1552292SN/A enum FetchStatus { 1562292SN/A Active, 1572292SN/A Inactive 1582292SN/A }; 1592292SN/A 1602292SN/A /** Individual thread status. */ 1612292SN/A enum ThreadStatus { 1621060SN/A Running, 1631060SN/A Idle, 1641060SN/A Squashing, 1651060SN/A Blocked, 1662292SN/A Fetching, 1672292SN/A TrapPending, 1682292SN/A QuiescePending, 1697849SAli.Saidi@ARM.com ItlbWait, 1702669Sktlim@umich.edu IcacheWaitResponse, 1712696Sktlim@umich.edu IcacheWaitRetry, 1728460SAli.Saidi@ARM.com IcacheAccessComplete, 1738460SAli.Saidi@ARM.com NoGoodAddr 1741060SN/A }; 1751060SN/A 1762292SN/A /** Fetching Policy, Add new policies here.*/ 1772292SN/A enum FetchPriority { 1782292SN/A SingleThread, 1792292SN/A RoundRobin, 1802292SN/A Branch, 1812292SN/A IQ, 1822292SN/A LSQ 1832292SN/A }; 1841060SN/A 1852292SN/A private: 1862292SN/A /** Fetch status. */ 1872292SN/A FetchStatus _status; 1882292SN/A 1892292SN/A /** Per-thread status. */ 1902292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 1912292SN/A 1922292SN/A /** Fetch policy. */ 1932292SN/A FetchPriority fetchPolicy; 1942292SN/A 1952292SN/A /** List that has the threads organized by priority. */ 1966221Snate@binkert.org std::list<ThreadID> priorityList; 1971060SN/A 19810023Smatt.horsnell@ARM.com /** Probe points. */ 19910023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppFetch; 20010023Smatt.horsnell@ARM.com 2011060SN/A public: 2022292SN/A /** DefaultFetch constructor. */ 2035529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2041684SN/A 2052292SN/A /** Returns the name of fetch. */ 2062292SN/A std::string name() const; 2071684SN/A 2082292SN/A /** Registers statistics. */ 2091062SN/A void regStats(); 2101062SN/A 21110023Smatt.horsnell@ARM.com /** Registers probes. */ 21210023Smatt.horsnell@ARM.com void regProbePoints(); 21310023Smatt.horsnell@ARM.com 2142292SN/A /** Sets the main backwards communication time buffer pointer. */ 2151060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2161060SN/A 2172292SN/A /** Sets pointer to list of active threads. */ 2186221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 2192292SN/A 2202292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 2211060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2221060SN/A 2232292SN/A /** Initialize stage. */ 2249427SAndreas.Sandberg@ARM.com void startupStage(); 2252292SN/A 2268707Sandreas.hansson@arm.com /** Handles retrying the fetch access. */ 2278707Sandreas.hansson@arm.com void recvRetry(); 2288707Sandreas.hansson@arm.com 2292292SN/A /** Processes cache completion event. */ 2302669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 2312292SN/A 2329444SAndreas.Sandberg@ARM.com /** Resume after a drain. */ 2339444SAndreas.Sandberg@ARM.com void drainResume(); 2342843Sktlim@umich.edu 2359444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 2369444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2372843Sktlim@umich.edu 2389444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 2399444SAndreas.Sandberg@ARM.com bool isDrained() const; 2402307SN/A 2412348SN/A /** Takes over from another CPU's thread. */ 2422307SN/A void takeOverFrom(); 2432307SN/A 2449444SAndreas.Sandberg@ARM.com /** 2459444SAndreas.Sandberg@ARM.com * Stall the fetch stage after reaching a safe drain point. 2469444SAndreas.Sandberg@ARM.com * 2479444SAndreas.Sandberg@ARM.com * The CPU uses this method to stop fetching instructions from a 2489444SAndreas.Sandberg@ARM.com * thread that has been drained. The drain stall is different from 2499444SAndreas.Sandberg@ARM.com * all other stalls in that it is signaled instantly from the 2509444SAndreas.Sandberg@ARM.com * commit stage (without the normal communication delay) when it 2519444SAndreas.Sandberg@ARM.com * has reached a safe point to drain from. 2529444SAndreas.Sandberg@ARM.com */ 2539444SAndreas.Sandberg@ARM.com void drainStall(ThreadID tid); 2542307SN/A 2552348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2562292SN/A void wakeFromQuiesce(); 2571060SN/A 2581061SN/A private: 2599444SAndreas.Sandberg@ARM.com /** Reset this pipeline stage */ 2609444SAndreas.Sandberg@ARM.com void resetStage(); 2619444SAndreas.Sandberg@ARM.com 2622329SN/A /** Changes the status of this stage to active, and indicates this 2632329SN/A * to the CPU. 2642292SN/A */ 2652292SN/A inline void switchToActive(); 2662292SN/A 2672329SN/A /** Changes the status of this stage to inactive, and indicates 2682329SN/A * this to the CPU. 2692292SN/A */ 2702292SN/A inline void switchToInactive(); 2712292SN/A 2721061SN/A /** 2731061SN/A * Looks up in the branch predictor to see if the next PC should be 2741061SN/A * either next PC+=MachInst or a branch target. 2751763SN/A * @param next_PC Next PC variable passed in by reference. It is 2761061SN/A * expected to be set to the current PC; it will be updated with what 2771061SN/A * the next PC will be. 2782935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 2791061SN/A * @return Whether or not a branch was predicted as taken. 2801061SN/A */ 2817720Sgblack@eecs.umich.edu bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc); 2821062SN/A 2831062SN/A /** 2849982Satgutier@umich.edu * Fetches the cache line that contains the fetch PC. Returns any 2851062SN/A * fault that happened. Puts the data into the class variable 2869982Satgutier@umich.edu * fetchBuffer, which may not hold the entire fetched cache line. 2877764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 2882292SN/A * @param ret_fault The fault reference that will be set to the result of 2892292SN/A * the icache access. 2902292SN/A * @param tid Thread id. 2917764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 2921062SN/A * @return Any fault that occured. 2931062SN/A */ 2947849SAli.Saidi@ARM.com bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 2957849SAli.Saidi@ARM.com void finishTranslation(Fault fault, RequestPtr mem_req); 2961062SN/A 2977847Sminkyu.jeong@arm.com 2987847Sminkyu.jeong@arm.com /** Check if an interrupt is pending and that we need to handle 2997847Sminkyu.jeong@arm.com */ 3007847Sminkyu.jeong@arm.com bool 3017847Sminkyu.jeong@arm.com checkInterrupt(Addr pc) 3027847Sminkyu.jeong@arm.com { 3037847Sminkyu.jeong@arm.com return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 3047847Sminkyu.jeong@arm.com } 3057847Sminkyu.jeong@arm.com 3062292SN/A /** Squashes a specific thread and resets the PC. */ 3078503Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, 3088503Sgblack@eecs.umich.edu const DynInstPtr squashInst, ThreadID tid); 3091684SN/A 3102292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3112292SN/A * remove any instructions between fetch and decode that should be sqaushed. 3122292SN/A */ 3137720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 3148503Sgblack@eecs.umich.edu const DynInstPtr squashInst, 3158503Sgblack@eecs.umich.edu const InstSeqNum seq_num, ThreadID tid); 3162292SN/A 3172292SN/A /** Checks if a thread is stalled. */ 3186221Snate@binkert.org bool checkStall(ThreadID tid) const; 3192292SN/A 3202292SN/A /** Updates overall fetch stage status; to be called at the end of each 3212292SN/A * cycle. */ 3222292SN/A FetchStatus updateFetchStatus(); 3231684SN/A 3241684SN/A public: 3252292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3262292SN/A * remove any instructions that are not in the ROB. The source of this 3272292SN/A * squash should be the commit stage. 3282292SN/A */ 3298503Sgblack@eecs.umich.edu void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3308503Sgblack@eecs.umich.edu DynInstPtr squashInst, ThreadID tid); 3311684SN/A 3322292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 3332292SN/A * as many instructions as possible. 3342292SN/A */ 3351684SN/A void tick(); 3361684SN/A 3372292SN/A /** Checks all input signals and updates the status as necessary. 3382292SN/A * @return: Returns if the status has changed due to input signals. 3392292SN/A */ 3406221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 3411684SN/A 3422292SN/A /** Does the actual fetching of instructions and passing them on to the 3432292SN/A * next stage. 3442292SN/A * @param status_change fetch() sets this variable if there was a status 3452292SN/A * change (ie switching to IcacheMissStall). 3462292SN/A */ 3472292SN/A void fetch(bool &status_change); 3482292SN/A 3499982Satgutier@umich.edu /** Align a PC to the start of a fetch buffer block. */ 3509982Satgutier@umich.edu Addr fetchBufferAlignPC(Addr addr) 3511062SN/A { 3529982Satgutier@umich.edu return (addr & ~(fetchBufferMask)); 3531062SN/A } 3541061SN/A 3558541Sgblack@eecs.umich.edu /** The decoder. */ 3569023Sgblack@eecs.umich.edu TheISA::Decoder *decoder[Impl::MaxThreads]; 3578541Sgblack@eecs.umich.edu 3581060SN/A private: 3597764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3607764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3617764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 3627764Sgblack@eecs.umich.edu 3632292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 3646221Snate@binkert.org ThreadID getFetchingThread(FetchPriority &fetch_priority); 3652292SN/A 3662292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3676221Snate@binkert.org ThreadID roundRobin(); 3682292SN/A 3692292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3706221Snate@binkert.org ThreadID iqCount(); 3712292SN/A 3722292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 3736221Snate@binkert.org ThreadID lsqCount(); 3742292SN/A 3756221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 3766221Snate@binkert.org * policy. */ 3776221Snate@binkert.org ThreadID branchCount(); 3782292SN/A 3798462Sgeoffrey.blake@arm.com /** Pipeline the next I-cache access to the current one. */ 3808462Sgeoffrey.blake@arm.com void pipelineIcacheAccesses(ThreadID tid); 3818462Sgeoffrey.blake@arm.com 3828462Sgeoffrey.blake@arm.com /** Profile the reasons of fetch stall. */ 3838462Sgeoffrey.blake@arm.com void profileStall(ThreadID tid); 3848462Sgeoffrey.blake@arm.com 3852292SN/A private: 3862733Sktlim@umich.edu /** Pointer to the O3CPU. */ 3872733Sktlim@umich.edu O3CPU *cpu; 3881060SN/A 3891060SN/A /** Time buffer interface. */ 3901060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3911060SN/A 3921060SN/A /** Wire to get decode's information from backwards time buffer. */ 3931060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 3941060SN/A 3951060SN/A /** Wire to get rename's information from backwards time buffer. */ 3961060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 3971060SN/A 3981060SN/A /** Wire to get iew's information from backwards time buffer. */ 3991060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 4001060SN/A 4011060SN/A /** Wire to get commit's information from backwards time buffer. */ 4021060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 4031060SN/A 4041060SN/A //Might be annoying how this name is different than the queue. 4051060SN/A /** Wire used to write any information heading to decode. */ 4061060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 4071060SN/A 4081061SN/A /** BPredUnit. */ 4099480Snilay@cs.wisc.edu BPredUnit *branchPred; 4101061SN/A 4117720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4122292SN/A 4137764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 4147764Sgblack@eecs.umich.edu 4157764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 4167764Sgblack@eecs.umich.edu 4178314Sgeoffrey.blake@arm.com /** Can the fetch stage redirect from an interrupt on this instruction? */ 4188314Sgeoffrey.blake@arm.com bool delayedCommit[Impl::MaxThreads]; 4198314Sgeoffrey.blake@arm.com 4202678Sktlim@umich.edu /** Memory request used to access cache. */ 4212678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 4222292SN/A 4232292SN/A /** Variable that tracks if fetch has written to the time buffer this 4242292SN/A * cycle. Used to tell CPU if there is activity this cycle. 4252292SN/A */ 4262292SN/A bool wroteToTimeBuffer; 4272292SN/A 4282292SN/A /** Tracks how many instructions has been fetched this cycle. */ 4292292SN/A int numInst; 4302292SN/A 4312292SN/A /** Source of possible stalls. */ 4322292SN/A struct Stalls { 4332292SN/A bool decode; 4349444SAndreas.Sandberg@ARM.com bool drain; 4352292SN/A }; 4362292SN/A 4372292SN/A /** Tracks which stages are telling fetch to stall. */ 4382292SN/A Stalls stalls[Impl::MaxThreads]; 4391060SN/A 4409184Sandreas.hansson@arm.com /** Decode to fetch delay. */ 4419184Sandreas.hansson@arm.com Cycles decodeToFetchDelay; 4421060SN/A 4439184Sandreas.hansson@arm.com /** Rename to fetch delay. */ 4449184Sandreas.hansson@arm.com Cycles renameToFetchDelay; 4451060SN/A 4469184Sandreas.hansson@arm.com /** IEW to fetch delay. */ 4479184Sandreas.hansson@arm.com Cycles iewToFetchDelay; 4481060SN/A 4499184Sandreas.hansson@arm.com /** Commit to fetch delay. */ 4509184Sandreas.hansson@arm.com Cycles commitToFetchDelay; 4511060SN/A 4521060SN/A /** The width of fetch in instructions. */ 4531060SN/A unsigned fetchWidth; 4541060SN/A 45510329Smitch.hayenga@arm.com /** The width of decode in instructions. */ 45610329Smitch.hayenga@arm.com unsigned decodeWidth; 45710329Smitch.hayenga@arm.com 4582696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 4592696Sktlim@umich.edu bool cacheBlocked; 4602696Sktlim@umich.edu 4612696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 4622696Sktlim@umich.edu PacketPtr retryPkt; 4632696Sktlim@umich.edu 4642696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 4656221Snate@binkert.org ThreadID retryTid; 4662696Sktlim@umich.edu 4671060SN/A /** Cache block size. */ 4689814Sandreas.hansson@arm.com unsigned int cacheBlkSize; 4691060SN/A 4709982Satgutier@umich.edu /** The size of the fetch buffer in bytes. The fetch buffer 4719982Satgutier@umich.edu * itself may be smaller than a cache line. 4729982Satgutier@umich.edu */ 4739982Satgutier@umich.edu unsigned fetchBufferSize; 4741060SN/A 4759982Satgutier@umich.edu /** Mask to align a fetch address to a fetch buffer boundary. */ 4769982Satgutier@umich.edu Addr fetchBufferMask; 4771060SN/A 4789982Satgutier@umich.edu /** The fetch data that is being fetched and buffered. */ 4799982Satgutier@umich.edu uint8_t *fetchBuffer[Impl::MaxThreads]; 4802893Sktlim@umich.edu 4819982Satgutier@umich.edu /** The PC of the first instruction loaded into the fetch buffer. */ 4829982Satgutier@umich.edu Addr fetchBufferPC[Impl::MaxThreads]; 4839982Satgutier@umich.edu 48410329Smitch.hayenga@arm.com /** The size of the fetch queue in micro-ops */ 48510329Smitch.hayenga@arm.com unsigned fetchQueueSize; 48610329Smitch.hayenga@arm.com 48710329Smitch.hayenga@arm.com /** Queue of fetched instructions */ 48810329Smitch.hayenga@arm.com std::deque<DynInstPtr> fetchQueue; 48910329Smitch.hayenga@arm.com 4909982Satgutier@umich.edu /** Whether or not the fetch buffer data is valid. */ 4919982Satgutier@umich.edu bool fetchBufferValid[Impl::MaxThreads]; 4922906Sktlim@umich.edu 4931060SN/A /** Size of instructions. */ 4941060SN/A int instSize; 4951060SN/A 4961060SN/A /** Icache stall statistics. */ 4972292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 4981062SN/A 4992292SN/A /** List of Active Threads */ 5006221Snate@binkert.org std::list<ThreadID> *activeThreads; 5012292SN/A 5022292SN/A /** Number of threads. */ 5036221Snate@binkert.org ThreadID numThreads; 5042292SN/A 5052292SN/A /** Number of threads that are actively fetching. */ 5066221Snate@binkert.org ThreadID numFetchingThreads; 5072292SN/A 5082292SN/A /** Thread ID being fetched. */ 5096221Snate@binkert.org ThreadID threadFetched; 5102292SN/A 5112348SN/A /** Checks if there is an interrupt pending. If there is, fetch 5122348SN/A * must stop once it is not fetching PAL instructions. 5132348SN/A */ 5142292SN/A bool interruptPending; 5152292SN/A 5168462Sgeoffrey.blake@arm.com /** Set to true if a pipelined I-cache request should be issued. */ 5178462Sgeoffrey.blake@arm.com bool issuePipelinedIfetch[Impl::MaxThreads]; 5188462Sgeoffrey.blake@arm.com 5198462Sgeoffrey.blake@arm.com /** Event used to delay fault generation of translation faults */ 5208462Sgeoffrey.blake@arm.com FinishTranslationEvent finishTranslationEvent; 5218462Sgeoffrey.blake@arm.com 5222292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 5232292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 5245999Snate@binkert.org Stats::Scalar icacheStallCycles; 5252292SN/A /** Stat for total number of fetched instructions. */ 5265999Snate@binkert.org Stats::Scalar fetchedInsts; 5272727Sktlim@umich.edu /** Total number of fetched branches. */ 5285999Snate@binkert.org Stats::Scalar fetchedBranches; 5292292SN/A /** Stat for total number of predicted branches. */ 5305999Snate@binkert.org Stats::Scalar predictedBranches; 5312292SN/A /** Stat for total number of cycles spent fetching. */ 5325999Snate@binkert.org Stats::Scalar fetchCycles; 5332292SN/A /** Stat for total number of cycles spent squashing. */ 5345999Snate@binkert.org Stats::Scalar fetchSquashCycles; 5357849SAli.Saidi@ARM.com /** Stat for total number of cycles spent waiting for translation */ 5367849SAli.Saidi@ARM.com Stats::Scalar fetchTlbCycles; 5372292SN/A /** Stat for total number of cycles spent blocked due to other stages in 5382292SN/A * the pipeline. 5392292SN/A */ 5405999Snate@binkert.org Stats::Scalar fetchIdleCycles; 5412348SN/A /** Total number of cycles spent blocked. */ 5425999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 5432348SN/A /** Total number of cycles spent in any other state. */ 5445999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 5458462Sgeoffrey.blake@arm.com /** Total number of cycles spent in waiting for drains. */ 5468462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingDrainCycles; 5478462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by no active threads to run. */ 5488462Sgeoffrey.blake@arm.com Stats::Scalar fetchNoActiveThreadStallCycles; 5498462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending traps. */ 5508462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingTrapStallCycles; 5518462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending quiesce instructions. */ 5528462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingQuiesceStallCycles; 5538462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by I-cache wait retrys. */ 5548462Sgeoffrey.blake@arm.com Stats::Scalar fetchIcacheWaitRetryStallCycles; 5552292SN/A /** Stat for total number of fetched cache lines. */ 5565999Snate@binkert.org Stats::Scalar fetchedCacheLines; 5572348SN/A /** Total number of outstanding icache accesses that were dropped 5582348SN/A * due to a squash. 5592348SN/A */ 5605999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 5618064SAli.Saidi@ARM.com /** Total number of outstanding tlb accesses that were dropped 5628064SAli.Saidi@ARM.com * due to a squash. 5638064SAli.Saidi@ARM.com */ 5648064SAli.Saidi@ARM.com Stats::Scalar fetchTlbSquashes; 5652292SN/A /** Distribution of number of instructions fetched each cycle. */ 5665999Snate@binkert.org Stats::Distribution fetchNisnDist; 5672348SN/A /** Rate of how often fetch was idle. */ 5682292SN/A Stats::Formula idleRate; 5692348SN/A /** Number of branch fetches per cycle. */ 5702292SN/A Stats::Formula branchRate; 5712348SN/A /** Number of instruction fetched per cycle. */ 5722292SN/A Stats::Formula fetchRate; 5731060SN/A}; 5741060SN/A 5752292SN/A#endif //__CPU_O3_FETCH_HH__ 576