dyn_inst_impl.hh revision 9046 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/full_system.hh"
46
47template <class Impl>
48BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
49                                   StaticInstPtr macroop,
50                                   TheISA::PCState pc, TheISA::PCState predPC,
51                                   InstSeqNum seq_num, O3CPU *cpu)
52    : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
53{
54    initVars();
55}
56
57template <class Impl>
58BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
59                                   StaticInstPtr _macroop)
60    : BaseDynInst<Impl>(_staticInst, _macroop)
61{
62    initVars();
63}
64
65template <class Impl>
66void
67BaseO3DynInst<Impl>::initVars()
68{
69    // Make sure to have the renamed register entries set to the same
70    // as the normal register entries.  It will allow the IQ to work
71    // without any modifications.
72    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
73        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
74    }
75
76    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
77        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
78    }
79
80    this->_readySrcRegIdx.reset();
81
82    _numDestMiscRegs = 0;
83
84#if TRACING_ON
85    fetchTick = 0;
86    decodeTick = 0;
87    renameTick = 0;
88    dispatchTick = 0;
89    issueTick = 0;
90    completeTick = 0;
91#endif
92}
93
94template <class Impl>
95Fault
96BaseO3DynInst<Impl>::execute()
97{
98    // @todo: Pretty convoluted way to avoid squashing from happening
99    // when using the TC during an instruction's execution
100    // (specifically for instructions that have side-effects that use
101    // the TC).  Fix this.
102    bool in_syscall = this->thread->inSyscall;
103    this->thread->inSyscall = true;
104
105    this->fault = this->staticInst->execute(this, this->traceData);
106
107    this->thread->inSyscall = in_syscall;
108
109    return this->fault;
110}
111
112template <class Impl>
113Fault
114BaseO3DynInst<Impl>::initiateAcc()
115{
116    // @todo: Pretty convoluted way to avoid squashing from happening
117    // when using the TC during an instruction's execution
118    // (specifically for instructions that have side-effects that use
119    // the TC).  Fix this.
120    bool in_syscall = this->thread->inSyscall;
121    this->thread->inSyscall = true;
122
123    this->fault = this->staticInst->initiateAcc(this, this->traceData);
124
125    this->thread->inSyscall = in_syscall;
126
127    return this->fault;
128}
129
130template <class Impl>
131Fault
132BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
133{
134    // @todo: Pretty convoluted way to avoid squashing from happening
135    // when using the TC during an instruction's execution
136    // (specifically for instructions that have side-effects that use
137    // the TC).  Fix this.
138    bool in_syscall = this->thread->inSyscall;
139    this->thread->inSyscall = true;
140
141    if (this->cpu->checker) {
142        if (this->isStoreConditional()) {
143            this->reqToVerify->setExtraData(pkt->req->getExtraData());
144        }
145    }
146
147    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
148
149    this->thread->inSyscall = in_syscall;
150
151    return this->fault;
152}
153
154template <class Impl>
155Fault
156BaseO3DynInst<Impl>::hwrei()
157{
158#if THE_ISA == ALPHA_ISA
159    // Can only do a hwrei when in pal mode.
160    if (!(this->instAddr() & 0x3))
161        return new AlphaISA::UnimplementedOpcodeFault;
162
163    // Set the next PC based on the value of the EXC_ADDR IPR.
164    AlphaISA::PCState pc = this->pcState();
165    pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
166                                          this->threadNumber));
167    this->pcState(pc);
168    if (CPA::available()) {
169        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
170        CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
171    }
172
173    // Tell CPU to clear any state it needs to if a hwrei is taken.
174    this->cpu->hwrei(this->threadNumber);
175#else
176
177#endif
178    // FIXME: XXX check for interrupts? XXX
179    return NoFault;
180}
181
182template <class Impl>
183void
184BaseO3DynInst<Impl>::trap(Fault fault)
185{
186    this->cpu->trap(fault, this->threadNumber, this->staticInst);
187}
188
189template <class Impl>
190bool
191BaseO3DynInst<Impl>::simPalCheck(int palFunc)
192{
193#if THE_ISA != ALPHA_ISA
194    panic("simPalCheck called, but PAL only exists in Alpha!\n");
195#endif
196    return this->cpu->simPalCheck(palFunc, this->threadNumber);
197}
198
199template <class Impl>
200void
201BaseO3DynInst<Impl>::syscall(int64_t callnum)
202{
203    if (FullSystem)
204        panic("Syscall emulation isn't available in FS mode.\n");
205
206    // HACK: check CPU's nextPC before and after syscall. If it
207    // changes, update this instruction's nextPC because the syscall
208    // must have changed the nextPC.
209    TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
210    this->cpu->syscall(callnum, this->threadNumber);
211    TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
212    if (!(curPC == newPC)) {
213        this->pcState(newPC);
214    }
215}
216
217