dyn_inst_impl.hh revision 8557:f44572edfba3 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "base/cp_annotate.hh"
44#include "cpu/o3/dyn_inst.hh"
45
46template <class Impl>
47BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
48                                   StaticInstPtr macroop,
49                                   TheISA::PCState pc, TheISA::PCState predPC,
50                                   InstSeqNum seq_num, O3CPU *cpu)
51    : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
52{
53    initVars();
54}
55
56template <class Impl>
57BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
58                                   StaticInstPtr _macroop)
59    : BaseDynInst<Impl>(_staticInst, _macroop)
60{
61    initVars();
62}
63
64template <class Impl>
65void
66BaseO3DynInst<Impl>::initVars()
67{
68    // Make sure to have the renamed register entries set to the same
69    // as the normal register entries.  It will allow the IQ to work
70    // without any modifications.
71    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
72        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
73    }
74
75    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
76        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
77        this->_readySrcRegIdx[i] = 0;
78    }
79
80    _numDestMiscRegs = 0;
81
82#if TRACING_ON
83    fetchTick = 0;
84    decodeTick = 0;
85    renameTick = 0;
86    dispatchTick = 0;
87    issueTick = 0;
88    completeTick = 0;
89#endif
90}
91
92template <class Impl>
93Fault
94BaseO3DynInst<Impl>::execute()
95{
96    // @todo: Pretty convoluted way to avoid squashing from happening
97    // when using the TC during an instruction's execution
98    // (specifically for instructions that have side-effects that use
99    // the TC).  Fix this.
100    bool in_syscall = this->thread->inSyscall;
101    this->thread->inSyscall = true;
102
103    this->fault = this->staticInst->execute(this, this->traceData);
104
105    this->thread->inSyscall = in_syscall;
106
107    return this->fault;
108}
109
110template <class Impl>
111Fault
112BaseO3DynInst<Impl>::initiateAcc()
113{
114    // @todo: Pretty convoluted way to avoid squashing from happening
115    // when using the TC during an instruction's execution
116    // (specifically for instructions that have side-effects that use
117    // the TC).  Fix this.
118    bool in_syscall = this->thread->inSyscall;
119    this->thread->inSyscall = true;
120
121    this->fault = this->staticInst->initiateAcc(this, this->traceData);
122
123    this->thread->inSyscall = in_syscall;
124
125    return this->fault;
126}
127
128template <class Impl>
129Fault
130BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
131{
132    // @todo: Pretty convoluted way to avoid squashing from happening
133    // when using the TC during an instruction's execution
134    // (specifically for instructions that have side-effects that use
135    // the TC).  Fix this.
136    bool in_syscall = this->thread->inSyscall;
137    this->thread->inSyscall = true;
138
139    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
140
141    this->thread->inSyscall = in_syscall;
142
143    return this->fault;
144}
145
146#if FULL_SYSTEM
147template <class Impl>
148Fault
149BaseO3DynInst<Impl>::hwrei()
150{
151#if THE_ISA == ALPHA_ISA
152    // Can only do a hwrei when in pal mode.
153    if (!(this->instAddr() & 0x3))
154        return new AlphaISA::UnimplementedOpcodeFault;
155
156    // Set the next PC based on the value of the EXC_ADDR IPR.
157    AlphaISA::PCState pc = this->pcState();
158    pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
159                                          this->threadNumber));
160    this->pcState(pc);
161    if (CPA::available()) {
162        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
163        CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
164    }
165
166    // Tell CPU to clear any state it needs to if a hwrei is taken.
167    this->cpu->hwrei(this->threadNumber);
168#else
169
170#endif
171    // FIXME: XXX check for interrupts? XXX
172    return NoFault;
173}
174
175template <class Impl>
176void
177BaseO3DynInst<Impl>::trap(Fault fault)
178{
179    this->cpu->trap(fault, this->threadNumber, this->staticInst);
180}
181
182template <class Impl>
183bool
184BaseO3DynInst<Impl>::simPalCheck(int palFunc)
185{
186#if THE_ISA != ALPHA_ISA
187    panic("simPalCheck called, but PAL only exists in Alpha!\n");
188#endif
189    return this->cpu->simPalCheck(palFunc, this->threadNumber);
190}
191#endif
192
193template <class Impl>
194void
195BaseO3DynInst<Impl>::syscall(int64_t callnum)
196{
197#if FULL_SYSTEM
198    panic("Syscall emulation isn't available in FS mode.\n");
199#else
200    // HACK: check CPU's nextPC before and after syscall. If it
201    // changes, update this instruction's nextPC because the syscall
202    // must have changed the nextPC.
203    TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
204    this->cpu->syscall(callnum, this->threadNumber);
205    TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
206    if (!(curPC == newPC)) {
207        this->pcState(newPC);
208    }
209#endif
210}
211
212