dyn_inst_impl.hh revision 7684 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "base/cp_annotate.hh"
32#include "cpu/o3/dyn_inst.hh"
33
34template <class Impl>
35BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
36                                   Addr PC, Addr NPC, Addr microPC,
37                                   Addr Pred_PC, Addr Pred_NPC,
38                                   Addr Pred_MicroPC,
39                                   InstSeqNum seq_num, O3CPU *cpu)
40    : BaseDynInst<Impl>(staticInst, PC, NPC, microPC,
41                        Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
42{
43    initVars();
44}
45
46template <class Impl>
47BaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst,
48                                   Addr PC, Addr NPC, Addr microPC,
49                                   Addr Pred_PC, Addr Pred_NPC,
50                                   Addr Pred_MicroPC,
51                                   InstSeqNum seq_num, O3CPU *cpu)
52    : BaseDynInst<Impl>(inst, PC, NPC, microPC,
53                        Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
54{
55    initVars();
56}
57
58template <class Impl>
59BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst)
60    : BaseDynInst<Impl>(_staticInst)
61{
62    initVars();
63}
64
65template <class Impl>
66void
67BaseO3DynInst<Impl>::initVars()
68{
69    // Make sure to have the renamed register entries set to the same
70    // as the normal register entries.  It will allow the IQ to work
71    // without any modifications.
72    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
73        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
74    }
75
76    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
77        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
78        this->_readySrcRegIdx[i] = 0;
79    }
80}
81
82template <class Impl>
83Fault
84BaseO3DynInst<Impl>::execute()
85{
86    // @todo: Pretty convoluted way to avoid squashing from happening
87    // when using the TC during an instruction's execution
88    // (specifically for instructions that have side-effects that use
89    // the TC).  Fix this.
90    bool in_syscall = this->thread->inSyscall;
91    this->thread->inSyscall = true;
92
93    this->fault = this->staticInst->execute(this, this->traceData);
94
95    this->thread->inSyscall = in_syscall;
96
97    return this->fault;
98}
99
100template <class Impl>
101Fault
102BaseO3DynInst<Impl>::initiateAcc()
103{
104    // @todo: Pretty convoluted way to avoid squashing from happening
105    // when using the TC during an instruction's execution
106    // (specifically for instructions that have side-effects that use
107    // the TC).  Fix this.
108    bool in_syscall = this->thread->inSyscall;
109    this->thread->inSyscall = true;
110
111    this->fault = this->staticInst->initiateAcc(this, this->traceData);
112
113    this->thread->inSyscall = in_syscall;
114
115    return this->fault;
116}
117
118template <class Impl>
119Fault
120BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
121{
122    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
123
124    return this->fault;
125}
126
127#if FULL_SYSTEM
128template <class Impl>
129Fault
130BaseO3DynInst<Impl>::hwrei()
131{
132#if THE_ISA == ALPHA_ISA
133    // Can only do a hwrei when in pal mode.
134    if (!(this->readPC() & 0x3))
135        return new AlphaISA::UnimplementedOpcodeFault;
136
137    // Set the next PC based on the value of the EXC_ADDR IPR.
138    this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
139                                           this->threadNumber));
140    if (CPA::available()) {
141        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
142        CPA::cpa()->swAutoBegin(tc, this->readNextPC());
143    }
144
145    // Tell CPU to clear any state it needs to if a hwrei is taken.
146    this->cpu->hwrei(this->threadNumber);
147#else
148
149#endif
150    // FIXME: XXX check for interrupts? XXX
151    return NoFault;
152}
153
154template <class Impl>
155void
156BaseO3DynInst<Impl>::trap(Fault fault)
157{
158    this->cpu->trap(fault, this->threadNumber, this->staticInst);
159}
160
161template <class Impl>
162bool
163BaseO3DynInst<Impl>::simPalCheck(int palFunc)
164{
165#if THE_ISA != ALPHA_ISA
166    panic("simPalCheck called, but PAL only exists in Alpha!\n");
167#endif
168    return this->cpu->simPalCheck(palFunc, this->threadNumber);
169}
170#else
171template <class Impl>
172void
173BaseO3DynInst<Impl>::syscall(int64_t callnum)
174{
175    // HACK: check CPU's nextPC before and after syscall. If it
176    // changes, update this instruction's nextPC because the syscall
177    // must have changed the nextPC.
178    Addr cpu_next_pc = this->cpu->readNextPC(this->threadNumber);
179    this->cpu->syscall(callnum, this->threadNumber);
180    Addr new_next_pc = this->cpu->readNextPC(this->threadNumber);
181    if (cpu_next_pc != new_next_pc) {
182        this->setNextPC(new_next_pc);
183    }
184}
185#endif
186
187