dyn_inst_impl.hh revision 4637 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "cpu/o3/alpha/dyn_inst.hh"
32
33template <class Impl>
34AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr staticInst,
35                                 Addr PC, Addr NPC, Addr microPC,
36                                 Addr Pred_PC, Addr Pred_NPC,
37                                 Addr Pred_MicroPC,
38                                 InstSeqNum seq_num, O3CPU *cpu)
39    : BaseDynInst<Impl>(staticInst, PC, NPC, microPC,
40            Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
41{
42    initVars();
43}
44
45template <class Impl>
46AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst,
47                                 Addr PC, Addr NPC, Addr microPC,
48                                 Addr Pred_PC, Addr Pred_NPC,
49                                 Addr Pred_MicroPC,
50                                 InstSeqNum seq_num, O3CPU *cpu)
51    : BaseDynInst<Impl>(inst, PC, NPC, microPC,
52            Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
53{
54    initVars();
55}
56
57template <class Impl>
58AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
59    : BaseDynInst<Impl>(_staticInst)
60{
61    initVars();
62}
63
64template <class Impl>
65void
66AlphaDynInst<Impl>::initVars()
67{
68    // Make sure to have the renamed register entries set to the same
69    // as the normal register entries.  It will allow the IQ to work
70    // without any modifications.
71    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
72        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
73    }
74
75    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
76        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
77        this->_readySrcRegIdx[i] = 0;
78    }
79}
80
81template <class Impl>
82Fault
83AlphaDynInst<Impl>::execute()
84{
85    // @todo: Pretty convoluted way to avoid squashing from happening
86    // when using the TC during an instruction's execution
87    // (specifically for instructions that have side-effects that use
88    // the TC).  Fix this.
89    bool in_syscall = this->thread->inSyscall;
90    this->thread->inSyscall = true;
91
92    this->fault = this->staticInst->execute(this, this->traceData);
93
94    this->thread->inSyscall = in_syscall;
95
96    return this->fault;
97}
98
99template <class Impl>
100Fault
101AlphaDynInst<Impl>::initiateAcc()
102{
103    // @todo: Pretty convoluted way to avoid squashing from happening
104    // when using the TC during an instruction's execution
105    // (specifically for instructions that have side-effects that use
106    // the TC).  Fix this.
107    bool in_syscall = this->thread->inSyscall;
108    this->thread->inSyscall = true;
109
110    this->fault = this->staticInst->initiateAcc(this, this->traceData);
111
112    this->thread->inSyscall = in_syscall;
113
114    return this->fault;
115}
116
117template <class Impl>
118Fault
119AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
120{
121    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
122
123    return this->fault;
124}
125
126#if FULL_SYSTEM
127template <class Impl>
128Fault
129AlphaDynInst<Impl>::hwrei()
130{
131    // Can only do a hwrei when in pal mode.
132    if (!(this->readPC() & 0x3))
133        return new AlphaISA::UnimplementedOpcodeFault;
134
135    // Set the next PC based on the value of the EXC_ADDR IPR.
136    this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
137                                           this->threadNumber));
138
139    // Tell CPU to clear any state it needs to if a hwrei is taken.
140    this->cpu->hwrei(this->threadNumber);
141
142    // FIXME: XXX check for interrupts? XXX
143    return NoFault;
144}
145
146template <class Impl>
147void
148AlphaDynInst<Impl>::trap(Fault fault)
149{
150    this->cpu->trap(fault, this->threadNumber);
151}
152
153template <class Impl>
154bool
155AlphaDynInst<Impl>::simPalCheck(int palFunc)
156{
157    return this->cpu->simPalCheck(palFunc, this->threadNumber);
158}
159#else
160template <class Impl>
161void
162AlphaDynInst<Impl>::syscall(int64_t callnum)
163{
164    this->cpu->syscall(callnum, this->threadNumber);
165}
166#endif
167
168