dyn_inst_impl.hh revision 2348 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "cpu/o3/alpha_dyn_inst.hh"
30
31template <class Impl>
32AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
33                                 InstSeqNum seq_num, FullCPU *cpu)
34    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
35{
36    initVars();
37}
38
39template <class Impl>
40AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
41    : BaseDynInst<Impl>(_staticInst)
42{
43    initVars();
44}
45
46template <class Impl>
47void
48AlphaDynInst<Impl>::initVars()
49{
50    // Make sure to have the renamed register entries set to the same
51    // as the normal register entries.  It will allow the IQ to work
52    // without any modifications.
53    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
54        _destRegIdx[i] = this->staticInst->destRegIdx(i);
55    }
56
57    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
58        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
59        this->_readySrcRegIdx[i] = 0;
60    }
61}
62
63template <class Impl>
64Fault
65AlphaDynInst<Impl>::execute()
66{
67    // @todo: Pretty convoluted way to avoid squashing from happening
68    // when using the XC during an instruction's execution
69    // (specifically for instructions that have side-effects that use
70    // the XC).  Fix this.
71    bool in_syscall = this->thread->inSyscall;
72    this->thread->inSyscall = true;
73
74    this->fault = this->staticInst->execute(this, this->traceData);
75
76    this->thread->inSyscall = in_syscall;
77
78    return this->fault;
79}
80
81template <class Impl>
82Fault
83AlphaDynInst<Impl>::initiateAcc()
84{
85    // @todo: Pretty convoluted way to avoid squashing from happening
86    // when using the XC during an instruction's execution
87    // (specifically for instructions that have side-effects that use
88    // the XC).  Fix this.
89    bool in_syscall = this->thread->inSyscall;
90    this->thread->inSyscall = true;
91
92    this->fault = this->staticInst->initiateAcc(this, this->traceData);
93
94    this->thread->inSyscall = in_syscall;
95
96    return this->fault;
97}
98
99template <class Impl>
100Fault
101AlphaDynInst<Impl>::completeAcc()
102{
103    if (this->isLoad()) {
104        // Loads need the request's data to complete the access.
105        this->fault = this->staticInst->completeAcc(this->req->data,
106                                                    this,
107                                                    this->traceData);
108    } else if (this->isStore()) {
109        // Stores need the result of the request to complete their access.
110        this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
111                                                    this,
112                                                    this->traceData);
113    } else {
114        panic("Unknown type!");
115    }
116
117    return this->fault;
118}
119
120#if FULL_SYSTEM
121template <class Impl>
122Fault
123AlphaDynInst<Impl>::hwrei()
124{
125    // Can only do a hwrei when in pal mode.
126    if (!this->cpu->inPalMode(this->readPC()))
127        return new AlphaISA::UnimplementedOpcodeFault;
128
129    // Set the next PC based on the value of the EXC_ADDR IPR.
130    this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
131                                           this->threadNumber));
132
133    // Tell CPU to clear any state it needs to if a hwrei is taken.
134    this->cpu->hwrei(this->threadNumber);
135
136    // FIXME: XXX check for interrupts? XXX
137    return NoFault;
138}
139
140template <class Impl>
141int
142AlphaDynInst<Impl>::readIntrFlag()
143{
144    return this->cpu->readIntrFlag();
145}
146
147template <class Impl>
148void
149AlphaDynInst<Impl>::setIntrFlag(int val)
150{
151    this->cpu->setIntrFlag(val);
152}
153
154template <class Impl>
155bool
156AlphaDynInst<Impl>::inPalMode()
157{
158    return this->cpu->inPalMode(this->PC);
159}
160
161template <class Impl>
162void
163AlphaDynInst<Impl>::trap(Fault fault)
164{
165    this->cpu->trap(fault, this->threadNumber);
166}
167
168template <class Impl>
169bool
170AlphaDynInst<Impl>::simPalCheck(int palFunc)
171{
172    return this->cpu->simPalCheck(palFunc, this->threadNumber);
173}
174#else
175template <class Impl>
176void
177AlphaDynInst<Impl>::syscall()
178{
179    this->cpu->syscall(this->threadNumber);
180}
181#endif
182
183