dyn_inst_impl.hh revision 12104:edd63f9c6184
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2010-2011 ARM Limited 312855Sgabeblack@google.com * All rights reserved 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * The license below extends only to copyright in the software and shall 612855Sgabeblack@google.com * not be construed as granting a license to any other intellectual 712855Sgabeblack@google.com * property including but not limited to intellectual property relating 812855Sgabeblack@google.com * to a hardware implementation of the functionality of the software 912855Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1012855Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1112855Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1212855Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1312855Sgabeblack@google.com * 1412855Sgabeblack@google.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1512855Sgabeblack@google.com * All rights reserved. 1612855Sgabeblack@google.com * 1712855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1812855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 1912855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2112855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2212855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2312855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2412855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2512855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2612855Sgabeblack@google.com * this software without specific prior written permission. 2712855Sgabeblack@google.com * 2812855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912855Sgabeblack@google.com * 4012855Sgabeblack@google.com * Authors: Kevin Lim 4112855Sgabeblack@google.com */ 4212855Sgabeblack@google.com 4312855Sgabeblack@google.com#ifndef __CPU_O3_DYN_INST_IMPL_HH__ 4412855Sgabeblack@google.com#define __CPU_O3_DYN_INST_IMPL_HH__ 4512855Sgabeblack@google.com 4612855Sgabeblack@google.com#include "base/cp_annotate.hh" 4712855Sgabeblack@google.com#include "cpu/o3/dyn_inst.hh" 4812855Sgabeblack@google.com#include "sim/full_system.hh" 4912855Sgabeblack@google.com#include "debug/O3PipeView.hh" 5012855Sgabeblack@google.com 5112855Sgabeblack@google.comtemplate <class Impl> 5212855Sgabeblack@google.comBaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst, 5312855Sgabeblack@google.com const StaticInstPtr ¯oop, 5412855Sgabeblack@google.com TheISA::PCState pc, TheISA::PCState predPC, 5512855Sgabeblack@google.com InstSeqNum seq_num, O3CPU *cpu) 5612855Sgabeblack@google.com : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 5712855Sgabeblack@google.com{ 5812855Sgabeblack@google.com initVars(); 5912855Sgabeblack@google.com} 6012855Sgabeblack@google.com 6112855Sgabeblack@google.comtemplate <class Impl> 6212855Sgabeblack@google.comBaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &_staticInst, 6312855Sgabeblack@google.com const StaticInstPtr &_macroop) 6412855Sgabeblack@google.com : BaseDynInst<Impl>(_staticInst, _macroop) 6512855Sgabeblack@google.com{ 6612855Sgabeblack@google.com initVars(); 6712855Sgabeblack@google.com} 6812855Sgabeblack@google.com 6912855Sgabeblack@google.comtemplate <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst() 7012855Sgabeblack@google.com{ 7112855Sgabeblack@google.com#if TRACING_ON 7212855Sgabeblack@google.com if (DTRACE(O3PipeView)) { 7312855Sgabeblack@google.com Tick fetch = this->fetchTick; 7412855Sgabeblack@google.com // fetchTick can be -1 if the instruction fetched outside the trace window. 7512855Sgabeblack@google.com if (fetch != -1) { 7612855Sgabeblack@google.com Tick val; 7712855Sgabeblack@google.com // Print info needed by the pipeline activity viewer. 7812855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", 7912855Sgabeblack@google.com fetch, 8012855Sgabeblack@google.com this->instAddr(), 8112855Sgabeblack@google.com this->microPC(), 8212855Sgabeblack@google.com this->seqNum, 8312855Sgabeblack@google.com this->staticInst->disassemble(this->instAddr())); 8412855Sgabeblack@google.com 8512855Sgabeblack@google.com val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick; 8612855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val); 8712855Sgabeblack@google.com val = (this->renameTick == -1) ? 0 : fetch + this->renameTick; 8812855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val); 8912855Sgabeblack@google.com val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick; 9012855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val); 9112855Sgabeblack@google.com val = (this->issueTick == -1) ? 0 : fetch + this->issueTick; 9212855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val); 9312855Sgabeblack@google.com val = (this->completeTick == -1) ? 0 : fetch + this->completeTick; 9412855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val); 9512855Sgabeblack@google.com val = (this->commitTick == -1) ? 0 : fetch + this->commitTick; 9612855Sgabeblack@google.com 9712855Sgabeblack@google.com Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick; 9812855Sgabeblack@google.com DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS); 9912855Sgabeblack@google.com } 10012855Sgabeblack@google.com } 10112855Sgabeblack@google.com#endif 10212855Sgabeblack@google.com}; 10312855Sgabeblack@google.com 10412855Sgabeblack@google.com 10512855Sgabeblack@google.comtemplate <class Impl> 10612855Sgabeblack@google.comvoid 10712855Sgabeblack@google.comBaseO3DynInst<Impl>::initVars() 10812855Sgabeblack@google.com{ 10912855Sgabeblack@google.com // Make sure to have the renamed register entries set to the same 11012855Sgabeblack@google.com // as the normal register entries. It will allow the IQ to work 11112855Sgabeblack@google.com // without any modifications. 11212855Sgabeblack@google.com for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 11312855Sgabeblack@google.com this->_destRegIdx[i] = this->staticInst->destRegIdx(i).regIdx; 11412855Sgabeblack@google.com } 11512855Sgabeblack@google.com 11612855Sgabeblack@google.com for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 11712855Sgabeblack@google.com this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i).regIdx; 11812855Sgabeblack@google.com } 11912855Sgabeblack@google.com 12012855Sgabeblack@google.com this->_readySrcRegIdx.reset(); 12112855Sgabeblack@google.com 12212855Sgabeblack@google.com _numDestMiscRegs = 0; 12312855Sgabeblack@google.com 12412855Sgabeblack@google.com#if TRACING_ON 12512855Sgabeblack@google.com // Value -1 indicates that particular phase 12612855Sgabeblack@google.com // hasn't happened (yet). 12712855Sgabeblack@google.com fetchTick = -1; 12812855Sgabeblack@google.com decodeTick = -1; 12912855Sgabeblack@google.com renameTick = -1; 130 dispatchTick = -1; 131 issueTick = -1; 132 completeTick = -1; 133 commitTick = -1; 134 storeTick = -1; 135#endif 136} 137 138template <class Impl> 139Fault 140BaseO3DynInst<Impl>::execute() 141{ 142 // @todo: Pretty convoluted way to avoid squashing from happening 143 // when using the TC during an instruction's execution 144 // (specifically for instructions that have side-effects that use 145 // the TC). Fix this. 146 bool no_squash_from_TC = this->thread->noSquashFromTC; 147 this->thread->noSquashFromTC = true; 148 149 this->fault = this->staticInst->execute(this, this->traceData); 150 151 this->thread->noSquashFromTC = no_squash_from_TC; 152 153 return this->fault; 154} 155 156template <class Impl> 157Fault 158BaseO3DynInst<Impl>::initiateAcc() 159{ 160 // @todo: Pretty convoluted way to avoid squashing from happening 161 // when using the TC during an instruction's execution 162 // (specifically for instructions that have side-effects that use 163 // the TC). Fix this. 164 bool no_squash_from_TC = this->thread->noSquashFromTC; 165 this->thread->noSquashFromTC = true; 166 167 this->fault = this->staticInst->initiateAcc(this, this->traceData); 168 169 this->thread->noSquashFromTC = no_squash_from_TC; 170 171 return this->fault; 172} 173 174template <class Impl> 175Fault 176BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 177{ 178 // @todo: Pretty convoluted way to avoid squashing from happening 179 // when using the TC during an instruction's execution 180 // (specifically for instructions that have side-effects that use 181 // the TC). Fix this. 182 bool no_squash_from_TC = this->thread->noSquashFromTC; 183 this->thread->noSquashFromTC = true; 184 185 if (this->cpu->checker) { 186 if (this->isStoreConditional()) { 187 this->reqToVerify->setExtraData(pkt->req->getExtraData()); 188 } 189 } 190 191 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 192 193 this->thread->noSquashFromTC = no_squash_from_TC; 194 195 return this->fault; 196} 197 198template <class Impl> 199Fault 200BaseO3DynInst<Impl>::hwrei() 201{ 202#if THE_ISA == ALPHA_ISA 203 // Can only do a hwrei when in pal mode. 204 if (!(this->instAddr() & 0x3)) 205 return std::make_shared<AlphaISA::UnimplementedOpcodeFault>(); 206 207 // Set the next PC based on the value of the EXC_ADDR IPR. 208 AlphaISA::PCState pc = this->pcState(); 209 pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 210 this->threadNumber)); 211 this->pcState(pc); 212 if (CPA::available()) { 213 ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 214 CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 215 } 216 217 // Tell CPU to clear any state it needs to if a hwrei is taken. 218 this->cpu->hwrei(this->threadNumber); 219#else 220 221#endif 222 // FIXME: XXX check for interrupts? XXX 223 return NoFault; 224} 225 226template <class Impl> 227void 228BaseO3DynInst<Impl>::trap(const Fault &fault) 229{ 230 this->cpu->trap(fault, this->threadNumber, this->staticInst); 231} 232 233template <class Impl> 234bool 235BaseO3DynInst<Impl>::simPalCheck(int palFunc) 236{ 237#if THE_ISA != ALPHA_ISA 238 panic("simPalCheck called, but PAL only exists in Alpha!\n"); 239#endif 240 return this->cpu->simPalCheck(palFunc, this->threadNumber); 241} 242 243template <class Impl> 244void 245BaseO3DynInst<Impl>::syscall(int64_t callnum, Fault *fault) 246{ 247 if (FullSystem) 248 panic("Syscall emulation isn't available in FS mode.\n"); 249 250 // HACK: check CPU's nextPC before and after syscall. If it 251 // changes, update this instruction's nextPC because the syscall 252 // must have changed the nextPC. 253 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 254 this->cpu->syscall(callnum, this->threadNumber, fault); 255 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 256 if (!(curPC == newPC)) { 257 this->pcState(newPC); 258 } 259} 260 261#endif//__CPU_O3_DYN_INST_IMPL_HH__ 262