dyn_inst_impl.hh revision 8733
12SN/A/*
29608Sandreas.hansson@arm.com * Copyright (c) 2010-2011 ARM Limited
38707Sandreas.hansson@arm.com * All rights reserved
48707Sandreas.hansson@arm.com *
58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
98707Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
138707Sandreas.hansson@arm.com *
141762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
157897Shestness@cs.utexas.edu * All rights reserved.
162SN/A *
172SN/A * Redistribution and use in source and binary forms, with or without
182SN/A * modification, are permitted provided that the following conditions are
192SN/A * met: redistributions of source code must retain the above copyright
202SN/A * notice, this list of conditions and the following disclaimer;
212SN/A * redistributions in binary form must reproduce the above copyright
222SN/A * notice, this list of conditions and the following disclaimer in the
232SN/A * documentation and/or other materials provided with the distribution;
242SN/A * neither the name of the copyright holders nor the names of its
252SN/A * contributors may be used to endorse or promote products derived from
262SN/A * this software without specific prior written permission.
272SN/A *
282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392SN/A *
402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
412665Ssaidi@eecs.umich.edu */
422665Ssaidi@eecs.umich.edu
437897Shestness@cs.utexas.edu#include "base/cp_annotate.hh"
442SN/A#include "config/use_checker.hh"
452SN/A#include "cpu/o3/dyn_inst.hh"
461717SN/A
471717SN/Atemplate <class Impl>
482SN/ABaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
492SN/A                                   StaticInstPtr macroop,
502SN/A                                   TheISA::PCState pc, TheISA::PCState predPC,
518745Sgblack@eecs.umich.edu                                   InstSeqNum seq_num, O3CPU *cpu)
524182Sgblack@eecs.umich.edu    : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
535664Sgblack@eecs.umich.edu{
54707SN/A    initVars();
556658Snate@binkert.org}
568229Snate@binkert.org
5756SN/Atemplate <class Impl>
588779Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
594776Sgblack@eecs.umich.edu                                   StaticInstPtr _macroop)
602SN/A    : BaseDynInst<Impl>(_staticInst, _macroop)
618901Sandreas.hansson@arm.com{
622190SN/A    initVars();
632315SN/A}
642680Sktlim@umich.edu
652SN/Atemplate <class Impl>
662SN/Avoid
672356SN/ABaseO3DynInst<Impl>::initVars()
682356SN/A{
692356SN/A    // Make sure to have the renamed register entries set to the same
706144Sksewell@umich.edu    // as the normal register entries.  It will allow the IQ to work
712356SN/A    // without any modifications.
722356SN/A    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
736144Sksewell@umich.edu        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
742356SN/A    }
752356SN/A
766144Sksewell@umich.edu    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
772356SN/A        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
782356SN/A        this->_readySrcRegIdx[i] = 0;
792356SN/A    }
806144Sksewell@umich.edu
816144Sksewell@umich.edu    _numDestMiscRegs = 0;
826144Sksewell@umich.edu
836144Sksewell@umich.edu#if TRACING_ON
846144Sksewell@umich.edu    fetchTick = 0;
855336Shines@cs.fsu.edu    decodeTick = 0;
862356SN/A    renameTick = 0;
872356SN/A    dispatchTick = 0;
882856Srdreslin@umich.edu    issueTick = 0;
892SN/A    completeTick = 0;
901634SN/A#endif
919157Sandreas.hansson@arm.com}
923814Ssaidi@eecs.umich.edu
933814Ssaidi@eecs.umich.edutemplate <class Impl>
945712Shsul@eecs.umich.eduFault
955712Shsul@eecs.umich.eduBaseO3DynInst<Impl>::execute()
965715Shsul@eecs.umich.edu{
975712Shsul@eecs.umich.edu    // @todo: Pretty convoluted way to avoid squashing from happening
985712Shsul@eecs.umich.edu    // when using the TC during an instruction's execution
991634SN/A    // (specifically for instructions that have side-effects that use
1008832SAli.Saidi@ARM.com    // the TC).  Fix this.
1018832SAli.Saidi@ARM.com    bool in_syscall = this->thread->inSyscall;
1028832SAli.Saidi@ARM.com    this->thread->inSyscall = true;
1038832SAli.Saidi@ARM.com
1048832SAli.Saidi@ARM.com    this->fault = this->staticInst->execute(this, this->traceData);
1058832SAli.Saidi@ARM.com
1069332Sdam.sunwoo@arm.com    this->thread->inSyscall = in_syscall;
1079332Sdam.sunwoo@arm.com
1089332Sdam.sunwoo@arm.com    return this->fault;
1099332Sdam.sunwoo@arm.com}
1109332Sdam.sunwoo@arm.com
1119332Sdam.sunwoo@arm.comtemplate <class Impl>
1129332Sdam.sunwoo@arm.comFault
1139332Sdam.sunwoo@arm.comBaseO3DynInst<Impl>::initiateAcc()
1149332Sdam.sunwoo@arm.com{
1159332Sdam.sunwoo@arm.com    // @todo: Pretty convoluted way to avoid squashing from happening
1169332Sdam.sunwoo@arm.com    // when using the TC during an instruction's execution
1179430SAndreas.Sandberg@ARM.com    // (specifically for instructions that have side-effects that use
1189430SAndreas.Sandberg@ARM.com    // the TC).  Fix this.
1199430SAndreas.Sandberg@ARM.com    bool in_syscall = this->thread->inSyscall;
1201634SN/A    this->thread->inSyscall = true;
1218850Sandreas.hansson@arm.com
1228850Sandreas.hansson@arm.com    this->fault = this->staticInst->initiateAcc(this, this->traceData);
1238850Sandreas.hansson@arm.com
1248850Sandreas.hansson@arm.com    this->thread->inSyscall = in_syscall;
1258850Sandreas.hansson@arm.com
1268850Sandreas.hansson@arm.com    return this->fault;
1278850Sandreas.hansson@arm.com}
1289608Sandreas.hansson@arm.com
1298850Sandreas.hansson@arm.comtemplate <class Impl>
1308850Sandreas.hansson@arm.comFault
1318850Sandreas.hansson@arm.comBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
1328850Sandreas.hansson@arm.com{
1338850Sandreas.hansson@arm.com    // @todo: Pretty convoluted way to avoid squashing from happening
1348850Sandreas.hansson@arm.com    // when using the TC during an instruction's execution
1358850Sandreas.hansson@arm.com    // (specifically for instructions that have side-effects that use
1369608Sandreas.hansson@arm.com    // the TC).  Fix this.
1378850Sandreas.hansson@arm.com    bool in_syscall = this->thread->inSyscall;
1385712Shsul@eecs.umich.edu    this->thread->inSyscall = true;
1395712Shsul@eecs.umich.edu
1405712Shsul@eecs.umich.edu#if USE_CHECKER
1418832SAli.Saidi@ARM.com    if (this->isStoreConditional()) {
1428832SAli.Saidi@ARM.com       this->reqToVerify->setExtraData(pkt->req->getExtraData());
1438832SAli.Saidi@ARM.com    }
1448832SAli.Saidi@ARM.com#endif
1458832SAli.Saidi@ARM.com    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
1468850Sandreas.hansson@arm.com
1478926Sandreas.hansson@arm.com    this->thread->inSyscall = in_syscall;
1488926Sandreas.hansson@arm.com
1498926Sandreas.hansson@arm.com    return this->fault;
1508850Sandreas.hansson@arm.com}
1518850Sandreas.hansson@arm.com
1528850Sandreas.hansson@arm.com#if FULL_SYSTEM
1538850Sandreas.hansson@arm.comtemplate <class Impl>
1548922Swilliam.wang@arm.comFault
1558850Sandreas.hansson@arm.comBaseO3DynInst<Impl>::hwrei()
1569294Sandreas.hansson@arm.com{
1579294Sandreas.hansson@arm.com#if THE_ISA == ALPHA_ISA
1588850Sandreas.hansson@arm.com    // Can only do a hwrei when in pal mode.
1599332Sdam.sunwoo@arm.com    if (!(this->instAddr() & 0x3))
1609332Sdam.sunwoo@arm.com        return new AlphaISA::UnimplementedOpcodeFault;
1619332Sdam.sunwoo@arm.com
1629332Sdam.sunwoo@arm.com    // Set the next PC based on the value of the EXC_ADDR IPR.
1639332Sdam.sunwoo@arm.com    AlphaISA::PCState pc = this->pcState();
1649332Sdam.sunwoo@arm.com    pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
1659332Sdam.sunwoo@arm.com                                          this->threadNumber));
1669332Sdam.sunwoo@arm.com    this->pcState(pc);
1677914SBrad.Beckmann@amd.com    if (CPA::available()) {
1687914SBrad.Beckmann@amd.com        ThreadContext *tc = this->cpu->tcBase(this->threadNumber);
1693814Ssaidi@eecs.umich.edu        CPA::cpa()->swAutoBegin(tc, this->nextInstAddr());
1703814Ssaidi@eecs.umich.edu    }
1711634SN/A
1725664Sgblack@eecs.umich.edu    // Tell CPU to clear any state it needs to if a hwrei is taken.
1735664Sgblack@eecs.umich.edu    this->cpu->hwrei(this->threadNumber);
1742SN/A#else
1755704Snate@binkert.org
1762SN/A#endif
1772SN/A    // FIXME: XXX check for interrupts? XXX
1785645Sgblack@eecs.umich.edu    return NoFault;
1795645Sgblack@eecs.umich.edu}
1805645Sgblack@eecs.umich.edu
1815647Sgblack@eecs.umich.edutemplate <class Impl>
1825645Sgblack@eecs.umich.eduvoid
1835645Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::trap(Fault fault)
1845807Snate@binkert.org{
1855807Snate@binkert.org    this->cpu->trap(fault, this->threadNumber, this->staticInst);
1865807Snate@binkert.org}
1875807Snate@binkert.org
1885807Snate@binkert.orgtemplate <class Impl>
1895807Snate@binkert.orgbool
1908779Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc)
1918779Sgblack@eecs.umich.edu{
1925807Snate@binkert.org#if THE_ISA != ALPHA_ISA
1935807Snate@binkert.org    panic("simPalCheck called, but PAL only exists in Alpha!\n");
1945807Snate@binkert.org#endif
1955807Snate@binkert.org    return this->cpu->simPalCheck(palFunc, this->threadNumber);
1965807Snate@binkert.org}
1975807Snate@binkert.org#endif
1985807Snate@binkert.org
1995807Snate@binkert.orgtemplate <class Impl>
2005807Snate@binkert.orgvoid
2015807Snate@binkert.orgBaseO3DynInst<Impl>::syscall(int64_t callnum)
2025807Snate@binkert.org{
2035807Snate@binkert.org#if FULL_SYSTEM
2045807Snate@binkert.org    panic("Syscall emulation isn't available in FS mode.\n");
2052SN/A#else
2065704Snate@binkert.org    // HACK: check CPU's nextPC before and after syscall. If it
2075704Snate@binkert.org    // changes, update this instruction's nextPC because the syscall
2085704Snate@binkert.org    // must have changed the nextPC.
2098793Sgblack@eecs.umich.edu    TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
2105704Snate@binkert.org    this->cpu->syscall(callnum, this->threadNumber);
2111917SN/A    TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
2121917SN/A    if (!(curPC == newPC)) {
2131917SN/A        this->pcState(newPC);
2141917SN/A    }
2151917SN/A#endif
2165536Srstrong@hp.com}
2171917SN/A
2181917SN/A