dyn_inst_impl.hh revision 7783
11689SN/A/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 142316SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 411689SN/A */ 421061SN/A 435953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 445596Sgblack@eecs.umich.edu#include "cpu/o3/dyn_inst.hh" 451061SN/A 461061SN/Atemplate <class Impl> 475596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst, 487720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 495596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 507720Sgblack@eecs.umich.edu : BaseDynInst<Impl>(staticInst, pc, predPC, seq_num, cpu) 514637SN/A{ 524637SN/A initVars(); 534637SN/A} 544637SN/A 554637SN/Atemplate <class Impl> 565596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(ExtMachInst inst, 577720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 585596Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu) 597720Sgblack@eecs.umich.edu : BaseDynInst<Impl>(inst, pc, predPC, seq_num, cpu) 601061SN/A{ 612292SN/A initVars(); 621061SN/A} 631061SN/A 641061SN/Atemplate <class Impl> 655596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr &_staticInst) 661464SN/A : BaseDynInst<Impl>(_staticInst) 671061SN/A{ 682292SN/A initVars(); 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 735596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initVars() 742292SN/A{ 751464SN/A // Make sure to have the renamed register entries set to the same 761464SN/A // as the normal register entries. It will allow the IQ to work 771464SN/A // without any modifications. 782292SN/A for (int i = 0; i < this->staticInst->numDestRegs(); i++) { 793782SN/A this->_destRegIdx[i] = this->staticInst->destRegIdx(i); 801464SN/A } 811464SN/A 822292SN/A for (int i = 0; i < this->staticInst->numSrcRegs(); i++) { 833782SN/A this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i); 842292SN/A this->_readySrcRegIdx[i] = 0; 851464SN/A } 867783SGiacomo.Gabrielli@arm.com 877783SGiacomo.Gabrielli@arm.com _numDestMiscRegs = 0; 881061SN/A} 891061SN/A 902292SN/Atemplate <class Impl> 912292SN/AFault 925596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::execute() 932292SN/A{ 942348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 952680SN/A // when using the TC during an instruction's execution 962348SN/A // (specifically for instructions that have side-effects that use 972680SN/A // the TC). Fix this. 982292SN/A bool in_syscall = this->thread->inSyscall; 992292SN/A this->thread->inSyscall = true; 1002292SN/A 1012292SN/A this->fault = this->staticInst->execute(this, this->traceData); 1022292SN/A 1032292SN/A this->thread->inSyscall = in_syscall; 1042292SN/A 1052292SN/A return this->fault; 1062292SN/A} 1072292SN/A 1082292SN/Atemplate <class Impl> 1092292SN/AFault 1105596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::initiateAcc() 1112292SN/A{ 1122348SN/A // @todo: Pretty convoluted way to avoid squashing from happening 1132680SN/A // when using the TC during an instruction's execution 1142348SN/A // (specifically for instructions that have side-effects that use 1152680SN/A // the TC). Fix this. 1162292SN/A bool in_syscall = this->thread->inSyscall; 1172292SN/A this->thread->inSyscall = true; 1182292SN/A 1192292SN/A this->fault = this->staticInst->initiateAcc(this, this->traceData); 1202292SN/A 1212292SN/A this->thread->inSyscall = in_syscall; 1222292SN/A 1232292SN/A return this->fault; 1242292SN/A} 1252292SN/A 1262292SN/Atemplate <class Impl> 1272292SN/AFault 1285596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::completeAcc(PacketPtr pkt) 1292292SN/A{ 1307758Sminkyu.jeong@arm.com // @todo: Pretty convoluted way to avoid squashing from happening 1317758Sminkyu.jeong@arm.com // when using the TC during an instruction's execution 1327758Sminkyu.jeong@arm.com // (specifically for instructions that have side-effects that use 1337758Sminkyu.jeong@arm.com // the TC). Fix this. 1347758Sminkyu.jeong@arm.com bool in_syscall = this->thread->inSyscall; 1357758Sminkyu.jeong@arm.com this->thread->inSyscall = true; 1367758Sminkyu.jeong@arm.com 1372790SN/A this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 1382292SN/A 1397758Sminkyu.jeong@arm.com this->thread->inSyscall = in_syscall; 1407758Sminkyu.jeong@arm.com 1412292SN/A return this->fault; 1422292SN/A} 1432292SN/A 1441858SN/A#if FULL_SYSTEM 1451061SN/Atemplate <class Impl> 1465702Ssaidi@eecs.umich.eduFault 1475702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::hwrei() 1485702Ssaidi@eecs.umich.edu{ 1495702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1505702Ssaidi@eecs.umich.edu // Can only do a hwrei when in pal mode. 1517720Sgblack@eecs.umich.edu if (!(this->instAddr() & 0x3)) 1525702Ssaidi@eecs.umich.edu return new AlphaISA::UnimplementedOpcodeFault; 1535702Ssaidi@eecs.umich.edu 1545702Ssaidi@eecs.umich.edu // Set the next PC based on the value of the EXC_ADDR IPR. 1557720Sgblack@eecs.umich.edu AlphaISA::PCState pc = this->pcState(); 1567720Sgblack@eecs.umich.edu pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, 1577720Sgblack@eecs.umich.edu this->threadNumber)); 1587720Sgblack@eecs.umich.edu this->pcState(pc); 1595953Ssaidi@eecs.umich.edu if (CPA::available()) { 1605953Ssaidi@eecs.umich.edu ThreadContext *tc = this->cpu->tcBase(this->threadNumber); 1617720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); 1625953Ssaidi@eecs.umich.edu } 1635702Ssaidi@eecs.umich.edu 1645702Ssaidi@eecs.umich.edu // Tell CPU to clear any state it needs to if a hwrei is taken. 1655702Ssaidi@eecs.umich.edu this->cpu->hwrei(this->threadNumber); 1665702Ssaidi@eecs.umich.edu#else 1675702Ssaidi@eecs.umich.edu 1685702Ssaidi@eecs.umich.edu#endif 1695702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 1705702Ssaidi@eecs.umich.edu return NoFault; 1715702Ssaidi@eecs.umich.edu} 1725702Ssaidi@eecs.umich.edu 1735702Ssaidi@eecs.umich.edutemplate <class Impl> 1741061SN/Avoid 1755596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::trap(Fault fault) 1761061SN/A{ 1777684Sgblack@eecs.umich.edu this->cpu->trap(fault, this->threadNumber, this->staticInst); 1781061SN/A} 1795702Ssaidi@eecs.umich.edu 1805702Ssaidi@eecs.umich.edutemplate <class Impl> 1815702Ssaidi@eecs.umich.edubool 1825702Ssaidi@eecs.umich.eduBaseO3DynInst<Impl>::simPalCheck(int palFunc) 1835702Ssaidi@eecs.umich.edu{ 1845702Ssaidi@eecs.umich.edu#if THE_ISA != ALPHA_ISA 1855702Ssaidi@eecs.umich.edu panic("simPalCheck called, but PAL only exists in Alpha!\n"); 1865702Ssaidi@eecs.umich.edu#endif 1875702Ssaidi@eecs.umich.edu return this->cpu->simPalCheck(palFunc, this->threadNumber); 1885702Ssaidi@eecs.umich.edu} 1891061SN/A#else 1901061SN/Atemplate <class Impl> 1911061SN/Avoid 1925596Sgblack@eecs.umich.eduBaseO3DynInst<Impl>::syscall(int64_t callnum) 1931061SN/A{ 1945556SN/A // HACK: check CPU's nextPC before and after syscall. If it 1955556SN/A // changes, update this instruction's nextPC because the syscall 1965556SN/A // must have changed the nextPC. 1977720Sgblack@eecs.umich.edu TheISA::PCState curPC = this->cpu->pcState(this->threadNumber); 1982669SN/A this->cpu->syscall(callnum, this->threadNumber); 1997720Sgblack@eecs.umich.edu TheISA::PCState newPC = this->cpu->pcState(this->threadNumber); 2007720Sgblack@eecs.umich.edu if (!(curPC == newPC)) { 2017720Sgblack@eecs.umich.edu this->pcState(newPC); 2025556SN/A } 2031061SN/A} 2041061SN/A#endif 2051061SN/A 206