dyn_inst_impl.hh revision 4172 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "cpu/o3/alpha/dyn_inst.hh"
32
33template <class Impl>
34AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
35                                 Addr Pred_PC, Addr Pred_NPC,
36                                 InstSeqNum seq_num, O3CPU *cpu)
37    : BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu)
38{
39    initVars();
40}
41
42template <class Impl>
43AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
44    : BaseDynInst<Impl>(_staticInst)
45{
46    initVars();
47}
48
49template <class Impl>
50void
51AlphaDynInst<Impl>::initVars()
52{
53    // Make sure to have the renamed register entries set to the same
54    // as the normal register entries.  It will allow the IQ to work
55    // without any modifications.
56    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
57        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
58    }
59
60    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
61        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
62        this->_readySrcRegIdx[i] = 0;
63    }
64}
65
66template <class Impl>
67Fault
68AlphaDynInst<Impl>::execute()
69{
70    // @todo: Pretty convoluted way to avoid squashing from happening
71    // when using the TC during an instruction's execution
72    // (specifically for instructions that have side-effects that use
73    // the TC).  Fix this.
74    bool in_syscall = this->thread->inSyscall;
75    this->thread->inSyscall = true;
76
77    this->fault = this->staticInst->execute(this, this->traceData);
78
79    this->thread->inSyscall = in_syscall;
80
81    return this->fault;
82}
83
84template <class Impl>
85Fault
86AlphaDynInst<Impl>::initiateAcc()
87{
88    // @todo: Pretty convoluted way to avoid squashing from happening
89    // when using the TC during an instruction's execution
90    // (specifically for instructions that have side-effects that use
91    // the TC).  Fix this.
92    bool in_syscall = this->thread->inSyscall;
93    this->thread->inSyscall = true;
94
95    this->fault = this->staticInst->initiateAcc(this, this->traceData);
96
97    this->thread->inSyscall = in_syscall;
98
99    return this->fault;
100}
101
102template <class Impl>
103Fault
104AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
105{
106    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
107
108    return this->fault;
109}
110
111#if FULL_SYSTEM
112template <class Impl>
113Fault
114AlphaDynInst<Impl>::hwrei()
115{
116    // Can only do a hwrei when in pal mode.
117    if (!(this->readPC() & 0x3))
118        return new AlphaISA::UnimplementedOpcodeFault;
119
120    // Set the next PC based on the value of the EXC_ADDR IPR.
121    this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
122                                           this->threadNumber));
123
124    // Tell CPU to clear any state it needs to if a hwrei is taken.
125    this->cpu->hwrei(this->threadNumber);
126
127    // FIXME: XXX check for interrupts? XXX
128    return NoFault;
129}
130
131template <class Impl>
132void
133AlphaDynInst<Impl>::trap(Fault fault)
134{
135    this->cpu->trap(fault, this->threadNumber);
136}
137
138template <class Impl>
139bool
140AlphaDynInst<Impl>::simPalCheck(int palFunc)
141{
142    return this->cpu->simPalCheck(palFunc, this->threadNumber);
143}
144#else
145template <class Impl>
146void
147AlphaDynInst<Impl>::syscall(int64_t callnum)
148{
149    this->cpu->syscall(callnum, this->threadNumber);
150}
151#endif
152
153