dyn_inst_impl.hh revision 3782 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "cpu/o3/alpha/dyn_inst.hh"
32
33template <class Impl>
34AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
35                                 InstSeqNum seq_num, O3CPU *cpu)
36    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
37{
38    initVars();
39}
40
41template <class Impl>
42AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
43    : BaseDynInst<Impl>(_staticInst)
44{
45    initVars();
46}
47
48template <class Impl>
49void
50AlphaDynInst<Impl>::initVars()
51{
52    // Make sure to have the renamed register entries set to the same
53    // as the normal register entries.  It will allow the IQ to work
54    // without any modifications.
55    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
56        this->_destRegIdx[i] = this->staticInst->destRegIdx(i);
57    }
58
59    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
60        this->_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
61        this->_readySrcRegIdx[i] = 0;
62    }
63}
64
65template <class Impl>
66Fault
67AlphaDynInst<Impl>::execute()
68{
69    // @todo: Pretty convoluted way to avoid squashing from happening
70    // when using the TC during an instruction's execution
71    // (specifically for instructions that have side-effects that use
72    // the TC).  Fix this.
73    bool in_syscall = this->thread->inSyscall;
74    this->thread->inSyscall = true;
75
76    this->fault = this->staticInst->execute(this, this->traceData);
77
78    this->thread->inSyscall = in_syscall;
79
80    return this->fault;
81}
82
83template <class Impl>
84Fault
85AlphaDynInst<Impl>::initiateAcc()
86{
87    // @todo: Pretty convoluted way to avoid squashing from happening
88    // when using the TC during an instruction's execution
89    // (specifically for instructions that have side-effects that use
90    // the TC).  Fix this.
91    bool in_syscall = this->thread->inSyscall;
92    this->thread->inSyscall = true;
93
94    this->fault = this->staticInst->initiateAcc(this, this->traceData);
95
96    this->thread->inSyscall = in_syscall;
97
98    return this->fault;
99}
100
101template <class Impl>
102Fault
103AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
104{
105    this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
106
107    return this->fault;
108}
109
110#if FULL_SYSTEM
111template <class Impl>
112Fault
113AlphaDynInst<Impl>::hwrei()
114{
115    // Can only do a hwrei when in pal mode.
116    if (!(this->readPC() & 0x3))
117        return new AlphaISA::UnimplementedOpcodeFault;
118
119    // Set the next PC based on the value of the EXC_ADDR IPR.
120    this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
121                                           this->threadNumber));
122
123    // Tell CPU to clear any state it needs to if a hwrei is taken.
124    this->cpu->hwrei(this->threadNumber);
125
126    // FIXME: XXX check for interrupts? XXX
127    return NoFault;
128}
129
130template <class Impl>
131void
132AlphaDynInst<Impl>::trap(Fault fault)
133{
134    this->cpu->trap(fault, this->threadNumber);
135}
136
137template <class Impl>
138bool
139AlphaDynInst<Impl>::simPalCheck(int palFunc)
140{
141    return this->cpu->simPalCheck(palFunc, this->threadNumber);
142}
143#else
144template <class Impl>
145void
146AlphaDynInst<Impl>::syscall(int64_t callnum)
147{
148    this->cpu->syscall(callnum, this->threadNumber);
149}
150#endif
151
152