dyn_inst_impl.hh revision 2316 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "cpu/o3/alpha_dyn_inst.hh"
30
31template <class Impl>
32AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
33                                 InstSeqNum seq_num, FullCPU *cpu)
34    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
35{
36    initVars();
37}
38
39template <class Impl>
40AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
41    : BaseDynInst<Impl>(_staticInst)
42{
43    initVars();
44}
45
46template <class Impl>
47void
48AlphaDynInst<Impl>::initVars()
49{
50    // Make sure to have the renamed register entries set to the same
51    // as the normal register entries.  It will allow the IQ to work
52    // without any modifications.
53    for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
54        _destRegIdx[i] = this->staticInst->destRegIdx(i);
55    }
56
57    for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
58        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
59        this->_readySrcRegIdx[i] = 0;
60    }
61}
62
63template <class Impl>
64Fault
65AlphaDynInst<Impl>::execute()
66{
67    // @todo: Pretty convoluted way to avoid squashing from happening when using
68    // the XC during an instruction's execution (specifically for instructions
69    // that have sideeffects that use the XC).  Fix this.
70    bool in_syscall = this->thread->inSyscall;
71    this->thread->inSyscall = true;
72
73    this->fault = this->staticInst->execute(this, this->traceData);
74
75    this->thread->inSyscall = in_syscall;
76
77    return this->fault;
78}
79
80template <class Impl>
81Fault
82AlphaDynInst<Impl>::initiateAcc()
83{
84    // @todo: Pretty convoluted way to avoid squashing from happening when using
85    // the XC during an instruction's execution (specifically for instructions
86    // that have sideeffects that use the XC).  Fix this.
87    bool in_syscall = this->thread->inSyscall;
88    this->thread->inSyscall = true;
89
90    this->fault = this->staticInst->initiateAcc(this, this->traceData);
91
92    this->thread->inSyscall = in_syscall;
93
94    return this->fault;
95}
96
97template <class Impl>
98Fault
99AlphaDynInst<Impl>::completeAcc()
100{
101    if (this->isLoad()) {
102        this->fault = this->staticInst->completeAcc(this->req->data,
103                                                    this,
104                                                    this->traceData);
105    } else if (this->isStore()) {
106        this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
107                                                    this,
108                                                    this->traceData);
109    } else {
110        panic("Unknown type!");
111    }
112
113    return this->fault;
114}
115
116#if FULL_SYSTEM
117template <class Impl>
118Fault
119AlphaDynInst<Impl>::hwrei()
120{
121    if (!this->cpu->inPalMode(this->readPC()))
122        return new AlphaISA::UnimplementedOpcodeFault;
123
124    this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
125                                           this->threadNumber));
126
127    // Tell CPU to clear any state it needs to if a hwrei is taken.
128    this->cpu->hwrei(this->threadNumber);
129
130    // FIXME: XXX check for interrupts? XXX
131    return NoFault;
132}
133
134template <class Impl>
135int
136AlphaDynInst<Impl>::readIntrFlag()
137{
138    return this->cpu->readIntrFlag();
139}
140
141template <class Impl>
142void
143AlphaDynInst<Impl>::setIntrFlag(int val)
144{
145    this->cpu->setIntrFlag(val);
146}
147
148template <class Impl>
149bool
150AlphaDynInst<Impl>::inPalMode()
151{
152    return this->cpu->inPalMode(this->PC);
153}
154
155template <class Impl>
156void
157AlphaDynInst<Impl>::trap(Fault fault)
158{
159    this->cpu->trap(fault, this->threadNumber);
160}
161
162template <class Impl>
163bool
164AlphaDynInst<Impl>::simPalCheck(int palFunc)
165{
166    return this->cpu->simPalCheck(palFunc, this->threadNumber);
167}
168#else
169template <class Impl>
170void
171AlphaDynInst<Impl>::syscall()
172{
173    this->cpu->syscall(this->threadNumber);
174}
175#endif
176
177