dyn_inst_impl.hh revision 1858 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "cpu/o3/alpha_dyn_inst.hh"
30
31template <class Impl>
32AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
33                                 InstSeqNum seq_num, FullCPU *cpu)
34    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
35{
36    // Make sure to have the renamed register entries set to the same
37    // as the normal register entries.  It will allow the IQ to work
38    // without any modifications.
39    for (int i = 0; i < this->staticInst->numDestRegs(); i++)
40    {
41        _destRegIdx[i] = this->staticInst->destRegIdx(i);
42    }
43
44    for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
45    {
46        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
47        this->_readySrcRegIdx[i] = 0;
48    }
49
50}
51
52template <class Impl>
53AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
54    : BaseDynInst<Impl>(_staticInst)
55{
56    // Make sure to have the renamed register entries set to the same
57    // as the normal register entries.  It will allow the IQ to work
58    // without any modifications.
59    for (int i = 0; i < _staticInst->numDestRegs(); i++)
60    {
61        _destRegIdx[i] = _staticInst->destRegIdx(i);
62    }
63
64    for (int i = 0; i < _staticInst->numSrcRegs(); i++)
65    {
66        _srcRegIdx[i] = _staticInst->srcRegIdx(i);
67    }
68}
69
70template <class Impl>
71uint64_t
72AlphaDynInst<Impl>::readUniq()
73{
74    return this->cpu->readUniq();
75}
76
77template <class Impl>
78void
79AlphaDynInst<Impl>::setUniq(uint64_t val)
80{
81    this->cpu->setUniq(val);
82}
83
84template <class Impl>
85uint64_t
86AlphaDynInst<Impl>::readFpcr()
87{
88    return this->cpu->readFpcr();
89}
90
91template <class Impl>
92void
93AlphaDynInst<Impl>::setFpcr(uint64_t val)
94{
95    this->cpu->setFpcr(val);
96}
97
98#if FULL_SYSTEM
99template <class Impl>
100uint64_t
101AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
102{
103    return this->cpu->readIpr(idx, fault);
104}
105
106template <class Impl>
107Fault
108AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
109{
110    return this->cpu->setIpr(idx, val);
111}
112
113template <class Impl>
114Fault
115AlphaDynInst<Impl>::hwrei()
116{
117    return this->cpu->hwrei();
118}
119
120template <class Impl>
121int
122AlphaDynInst<Impl>::readIntrFlag()
123{
124return this->cpu->readIntrFlag();
125}
126
127template <class Impl>
128void
129AlphaDynInst<Impl>::setIntrFlag(int val)
130{
131    this->cpu->setIntrFlag(val);
132}
133
134template <class Impl>
135bool
136AlphaDynInst<Impl>::inPalMode()
137{
138    return this->cpu->inPalMode();
139}
140
141template <class Impl>
142void
143AlphaDynInst<Impl>::trap(Fault fault)
144{
145    this->cpu->trap(fault);
146}
147
148template <class Impl>
149bool
150AlphaDynInst<Impl>::simPalCheck(int palFunc)
151{
152    return this->cpu->simPalCheck(palFunc);
153}
154#else
155template <class Impl>
156void
157AlphaDynInst<Impl>::syscall()
158{
159    this->cpu->syscall(this->threadNumber);
160}
161#endif
162
163