dyn_inst_impl.hh revision 1858
18528SN/A/* 28528SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 38528SN/A * All rights reserved. 49988Snilay@cs.wisc.edu * 58835SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 69988Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 78528SN/A * met: redistributions of source code must retain the above copyright 88528SN/A * notice, this list of conditions and the following disclaimer; 98528SN/A * redistributions in binary form must reproduce the above copyright 108528SN/A * notice, this list of conditions and the following disclaimer in the 118528SN/A * documentation and/or other materials provided with the distribution; 128528SN/A * neither the name of the copyright holders nor the names of its 1310315Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1410513SAli.Saidi@ARM.com * this software without specific prior written permission. 1510513SAli.Saidi@ARM.com * 1610513SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710038SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189885Sstever@gmail.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199885Sstever@gmail.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010513SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219055Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229449SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239988Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410513SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510513SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610038SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710038SAli.Saidi@ARM.com */ 2810038SAli.Saidi@ARM.com 2910038SAli.Saidi@ARM.com#include "cpu/o3/alpha_dyn_inst.hh" 3010038SAli.Saidi@ARM.com 3110038SAli.Saidi@ARM.comtemplate <class Impl> 328528SN/AAlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, 3310513SAli.Saidi@ARM.com InstSeqNum seq_num, FullCPU *cpu) 3410315Snilay@cs.wisc.edu : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu) 358528SN/A{ 3610513SAli.Saidi@ARM.com // Make sure to have the renamed register entries set to the same 3710513SAli.Saidi@ARM.com // as the normal register entries. It will allow the IQ to work 388528SN/A // without any modifications. 3910513SAli.Saidi@ARM.com for (int i = 0; i < this->staticInst->numDestRegs(); i++) 4010513SAli.Saidi@ARM.com { 419079SAli.Saidi@ARM.com _destRegIdx[i] = this->staticInst->destRegIdx(i); 428721SN/A } 439885Sstever@gmail.com 449885Sstever@gmail.com for (int i = 0; i < this->staticInst->numSrcRegs(); i++) 4510038SAli.Saidi@ARM.com { 4610513SAli.Saidi@ARM.com _srcRegIdx[i] = this->staticInst->srcRegIdx(i); 4710038SAli.Saidi@ARM.com this->_readySrcRegIdx[i] = 0; 488528SN/A } 498528SN/A 508528SN/A} 518528SN/A 528528SN/Atemplate <class Impl> 538528SN/AAlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst) 548528SN/A : BaseDynInst<Impl>(_staticInst) 558528SN/A{ 5610513SAli.Saidi@ARM.com // Make sure to have the renamed register entries set to the same 578528SN/A // as the normal register entries. It will allow the IQ to work 588528SN/A // without any modifications. 598528SN/A for (int i = 0; i < _staticInst->numDestRegs(); i++) 609885Sstever@gmail.com { 618528SN/A _destRegIdx[i] = _staticInst->destRegIdx(i); 629988Snilay@cs.wisc.edu } 6310513SAli.Saidi@ARM.com 648721SN/A for (int i = 0; i < _staticInst->numSrcRegs(); i++) 658721SN/A { 668891SAli.Saidi@ARM.com _srcRegIdx[i] = _staticInst->srcRegIdx(i); 678891SAli.Saidi@ARM.com } 688528SN/A} 698528SN/A 708528SN/Atemplate <class Impl> 718528SN/Auint64_t 728528SN/AAlphaDynInst<Impl>::readUniq() 738528SN/A{ 749988Snilay@cs.wisc.edu return this->cpu->readUniq(); 758528SN/A} 768528SN/A 778528SN/Atemplate <class Impl> 788528SN/Avoid 798528SN/AAlphaDynInst<Impl>::setUniq(uint64_t val) 808528SN/A{ 819988Snilay@cs.wisc.edu this->cpu->setUniq(val); 828528SN/A} 838528SN/A 848528SN/Atemplate <class Impl> 858528SN/Auint64_t 868528SN/AAlphaDynInst<Impl>::readFpcr() 878528SN/A{ 889988Snilay@cs.wisc.edu return this->cpu->readFpcr(); 8910513SAli.Saidi@ARM.com} 908528SN/A 918528SN/Atemplate <class Impl> 929885Sstever@gmail.comvoid 939885Sstever@gmail.comAlphaDynInst<Impl>::setFpcr(uint64_t val) 949885Sstever@gmail.com{ 9510315Snilay@cs.wisc.edu this->cpu->setFpcr(val); 969988Snilay@cs.wisc.edu} 9710315Snilay@cs.wisc.edu 989885Sstever@gmail.com#if FULL_SYSTEM 999885Sstever@gmail.comtemplate <class Impl> 1008528SN/Auint64_t 1018528SN/AAlphaDynInst<Impl>::readIpr(int idx, Fault &fault) 10210451Snilay@cs.wisc.edu{ 10310315Snilay@cs.wisc.edu return this->cpu->readIpr(idx, fault); 1048528SN/A} 1059885Sstever@gmail.com 1068528SN/Atemplate <class Impl> 1078528SN/AFault 1088528SN/AAlphaDynInst<Impl>::setIpr(int idx, uint64_t val) 1098528SN/A{ 11010038SAli.Saidi@ARM.com return this->cpu->setIpr(idx, val); 1118528SN/A} 1129988Snilay@cs.wisc.edu 1138528SN/Atemplate <class Impl> 1148528SN/AFault 1158528SN/AAlphaDynInst<Impl>::hwrei() 1169449SAli.Saidi@ARM.com{ 11710038SAli.Saidi@ARM.com return this->cpu->hwrei(); 1188528SN/A} 1198528SN/A 1208528SN/Atemplate <class Impl> 1218528SN/Aint 1228528SN/AAlphaDynInst<Impl>::readIntrFlag() 1238528SN/A{ 1248528SN/Areturn this->cpu->readIntrFlag(); 1258528SN/A} 1269885Sstever@gmail.com 12710315Snilay@cs.wisc.edutemplate <class Impl> 1289449SAli.Saidi@ARM.comvoid 1298528SN/AAlphaDynInst<Impl>::setIntrFlag(int val) 1308528SN/A{ 1318835SAli.Saidi@ARM.com this->cpu->setIntrFlag(val); 1328528SN/A} 1338528SN/A 1348528SN/Atemplate <class Impl> 1358528SN/Abool 1368528SN/AAlphaDynInst<Impl>::inPalMode() 1379885Sstever@gmail.com{ 1388891SAli.Saidi@ARM.com return this->cpu->inPalMode(); 13910451Snilay@cs.wisc.edu} 1409885Sstever@gmail.com 1419988Snilay@cs.wisc.edutemplate <class Impl> 1428528SN/Avoid 1439449SAli.Saidi@ARM.comAlphaDynInst<Impl>::trap(Fault fault) 1448528SN/A{ 1458528SN/A this->cpu->trap(fault); 14610451Snilay@cs.wisc.edu} 1478528SN/A 1488835SAli.Saidi@ARM.comtemplate <class Impl> 1499449SAli.Saidi@ARM.combool 15010036SAli.Saidi@ARM.comAlphaDynInst<Impl>::simPalCheck(int palFunc) 1518528SN/A{ 1528835SAli.Saidi@ARM.com return this->cpu->simPalCheck(palFunc); 1539885Sstever@gmail.com} 15410451Snilay@cs.wisc.edu#else 1558528SN/Atemplate <class Impl> 15610451Snilay@cs.wisc.eduvoid 1578528SN/AAlphaDynInst<Impl>::syscall() 15810451Snilay@cs.wisc.edu{ 1598528SN/A this->cpu->syscall(this->threadNumber); 1609885Sstever@gmail.com} 1619885Sstever@gmail.com#endif 16210451Snilay@cs.wisc.edu 1639885Sstever@gmail.com