dyn_inst_impl.hh revision 1464 
1
2#include "cpu/beta_cpu/alpha_dyn_inst.hh"
3
4template <class Impl>
5AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
6                                 InstSeqNum seq_num, FullCPU *cpu)
7    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
8{
9    // Make sure to have the renamed register entries set to the same
10    // as the normal register entries.  It will allow the IQ to work
11    // without any modifications.
12    for (int i = 0; i < this->staticInst->numDestRegs(); i++)
13    {
14        _destRegIdx[i] = this->staticInst->destRegIdx(i);
15    }
16
17    for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
18    {
19        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
20        this->_readySrcRegIdx[i] = 0;
21    }
22
23}
24
25template <class Impl>
26AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
27    : BaseDynInst<Impl>(_staticInst)
28{
29    // Make sure to have the renamed register entries set to the same
30    // as the normal register entries.  It will allow the IQ to work
31    // without any modifications.
32    for (int i = 0; i < _staticInst->numDestRegs(); i++)
33    {
34        _destRegIdx[i] = _staticInst->destRegIdx(i);
35    }
36
37    for (int i = 0; i < _staticInst->numSrcRegs(); i++)
38    {
39        _srcRegIdx[i] = _staticInst->srcRegIdx(i);
40    }
41}
42
43template <class Impl>
44uint64_t
45AlphaDynInst<Impl>::readUniq()
46{
47    return this->cpu->readUniq();
48}
49
50template <class Impl>
51void
52AlphaDynInst<Impl>::setUniq(uint64_t val)
53{
54    this->cpu->setUniq(val);
55}
56
57template <class Impl>
58uint64_t
59AlphaDynInst<Impl>::readFpcr()
60{
61    return this->cpu->readFpcr();
62}
63
64template <class Impl>
65void
66AlphaDynInst<Impl>::setFpcr(uint64_t val)
67{
68    this->cpu->setFpcr(val);
69}
70
71#ifdef FULL_SYSTEM
72template <class Impl>
73uint64_t
74AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
75{
76    return this->cpu->readIpr(idx, fault);
77}
78
79template <class Impl>
80Fault
81AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
82{
83    return this->cpu->setIpr(idx, val);
84}
85
86template <class Impl>
87Fault
88AlphaDynInst<Impl>::hwrei()
89{
90    return this->cpu->hwrei();
91}
92
93template <class Impl>
94int
95AlphaDynInst<Impl>::readIntrFlag()
96{
97return this->cpu->readIntrFlag();
98}
99
100template <class Impl>
101void
102AlphaDynInst<Impl>::setIntrFlag(int val)
103{
104    this->cpu->setIntrFlag(val);
105}
106
107template <class Impl>
108bool
109AlphaDynInst<Impl>::inPalMode()
110{
111    return this->cpu->inPalMode();
112}
113
114template <class Impl>
115void
116AlphaDynInst<Impl>::trap(Fault fault)
117{
118    this->cpu->trap(fault);
119}
120
121template <class Impl>
122bool
123AlphaDynInst<Impl>::simPalCheck(int palFunc)
124{
125    return this->cpu->simPalCheck(palFunc);
126}
127#else
128template <class Impl>
129void
130AlphaDynInst<Impl>::syscall()
131{
132    this->cpu->syscall();
133}
134#endif
135
136