dyn_inst_impl.hh revision 1061 
1
2#include "cpu/beta_cpu/alpha_dyn_inst.hh"
3
4template <class Impl>
5AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
6                                 InstSeqNum seq_num, FullCPU *cpu)
7    : BaseDynInst<AlphaSimpleImpl>(inst, PC, Pred_PC, seq_num, cpu)
8{
9}
10
11template <class Impl>
12AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
13    : BaseDynInst<AlphaSimpleImpl>(_staticInst)
14{
15}
16
17template <class Impl>
18uint64_t
19AlphaDynInst<Impl>::readUniq()
20{
21    return cpu->readUniq();
22}
23
24template <class Impl>
25void
26AlphaDynInst<Impl>::setUniq(uint64_t val)
27{
28    cpu->setUniq(val);
29}
30
31template <class Impl>
32uint64_t
33AlphaDynInst<Impl>::readFpcr()
34{
35    return cpu->readFpcr();
36}
37
38template <class Impl>
39void
40AlphaDynInst<Impl>::setFpcr(uint64_t val)
41{
42    cpu->setFpcr(val);
43}
44
45#ifdef FULL_SYSTEM
46template <class Impl>
47uint64_t
48AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
49{
50    return cpu->readIpr(idx, fault);
51}
52
53template <class Impl>
54Fault
55AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
56{
57    return cpu->setIpr(idx, val);
58}
59
60template <class Impl>
61Fault
62AlphaDynInst<Impl>::hwrei()
63{
64    return cpu->hwrei();
65}
66
67template <class Impl>
68int
69AlphaDynInst<Impl>::readIntrFlag()
70{
71return cpu->readIntrFlag();
72}
73
74template <class Impl>
75void
76AlphaDynInst<Impl>::setIntrFlag(int val)
77{
78    cpu->setIntrFlag(val);
79}
80
81template <class Impl>
82bool
83AlphaDynInst<Impl>::inPalMode()
84{
85    return cpu->inPalMode();
86}
87
88template <class Impl>
89void
90AlphaDynInst<Impl>::trap(Fault fault)
91{
92    cpu->trap(fault);
93}
94
95template <class Impl>
96bool
97AlphaDynInst<Impl>::simPalCheck(int palFunc)
98{
99    return cpu->simPalCheck(palFunc);
100}
101#else
102template <class Impl>
103void
104AlphaDynInst<Impl>::syscall()
105{
106    cpu->syscall();
107}
108#endif
109
110