dyn_inst.hh revision 9252:f350fac86d0f
11917SN/A/* 21917SN/A * Copyright (c) 2010 ARM Limited 31917SN/A * All rights reserved 41917SN/A * 51917SN/A * The license below extends only to copyright in the software and shall 61917SN/A * not be construed as granting a license to any other intellectual 71917SN/A * property including but not limited to intellectual property relating 81917SN/A * to a hardware implementation of the functionality of the software 91917SN/A * licensed hereunder. You may use the software subject to the license 101917SN/A * terms below provided that you ensure that this notice is replicated 111917SN/A * unmodified and in its entirety in all distributions of the software, 121917SN/A * modified or unmodified, in source code or in binary form. 131917SN/A * 141917SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151917SN/A * All rights reserved. 161917SN/A * 171917SN/A * Redistribution and use in source and binary forms, with or without 181917SN/A * modification, are permitted provided that the following conditions are 191917SN/A * met: redistributions of source code must retain the above copyright 201917SN/A * notice, this list of conditions and the following disclaimer; 211917SN/A * redistributions in binary form must reproduce the above copyright 221917SN/A * notice, this list of conditions and the following disclaimer in the 231917SN/A * documentation and/or other materials provided with the distribution; 241917SN/A * neither the name of the copyright holders nor the names of its 251917SN/A * contributors may be used to endorse or promote products derived from 261917SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291917SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301917SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311917SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321917SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331917SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341917SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351917SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361917SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372680Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381917SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395569Snate@binkert.org * 405569Snate@binkert.org * Authors: Kevin Lim 415569Snate@binkert.org */ 425569Snate@binkert.org 435569Snate@binkert.org#ifndef __CPU_O3_DYN_INST_HH__ 441917SN/A#define __CPU_O3_DYN_INST_HH__ 455569Snate@binkert.org 465569Snate@binkert.org#include "arch/isa_traits.hh" 471917SN/A#include "config/the_isa.hh" 485569Snate@binkert.org#include "cpu/o3/cpu.hh" 495569Snate@binkert.org#include "cpu/o3/isa_specific.hh" 505569Snate@binkert.org#include "cpu/base_dyn_inst.hh" 515569Snate@binkert.org#include "cpu/inst_seq.hh" 525569Snate@binkert.org 535569Snate@binkert.orgclass Packet; 545569Snate@binkert.org 555569Snate@binkert.org/** 565569Snate@binkert.org * Mostly implementation & ISA specific AlphaDynInst. As with most 575569Snate@binkert.org * other classes in the new CPU model, it is templated on the Impl to 585569Snate@binkert.org * allow for passing in of all types, such as the CPU type and the ISA 595569Snate@binkert.org * type. The AlphaDynInst serves as the primary interface to the CPU 605569Snate@binkert.org * for instructions that are executing. 615569Snate@binkert.org */ 625569Snate@binkert.orgtemplate <class Impl> 635569Snate@binkert.orgclass BaseO3DynInst : public BaseDynInst<Impl> 645569Snate@binkert.org{ 655569Snate@binkert.org public: 665569Snate@binkert.org /** Typedef for the CPU. */ 675569Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 685569Snate@binkert.org 695569Snate@binkert.org /** Binary machine instruction type. */ 705569Snate@binkert.org typedef TheISA::MachInst MachInst; 715569Snate@binkert.org /** Extended machine instruction type. */ 725569Snate@binkert.org typedef TheISA::ExtMachInst ExtMachInst; 735569Snate@binkert.org /** Logical register index type. */ 745569Snate@binkert.org typedef TheISA::RegIndex RegIndex; 755569Snate@binkert.org /** Integer register index type. */ 765569Snate@binkert.org typedef TheISA::IntReg IntReg; 775569Snate@binkert.org typedef TheISA::FloatReg FloatReg; 785569Snate@binkert.org typedef TheISA::FloatRegBits FloatRegBits; 795569Snate@binkert.org /** Misc register index type. */ 805569Snate@binkert.org typedef TheISA::MiscReg MiscReg; 815569Snate@binkert.org 825569Snate@binkert.org enum { 833570Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 845569Snate@binkert.org MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 855569Snate@binkert.org }; 865569Snate@binkert.org 871917SN/A public: 885569Snate@binkert.org /** BaseDynInst constructor given a binary instruction. */ 895569Snate@binkert.org BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 901917SN/A TheISA::PCState pc, TheISA::PCState predPC, 915569Snate@binkert.org InstSeqNum seq_num, O3CPU *cpu); 925569Snate@binkert.org 931917SN/A /** BaseDynInst constructor given a static inst pointer. */ 945569Snate@binkert.org BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop); 955569Snate@binkert.org 965569Snate@binkert.org ~BaseO3DynInst(); 971917SN/A 981917SN/A /** Executes the instruction.*/ 995569Snate@binkert.org Fault execute(); 1005569Snate@binkert.org 1011917SN/A /** Initiates the access. Only valid for memory operations. */ 1025569Snate@binkert.org Fault initiateAcc(); 1035569Snate@binkert.org 1041917SN/A /** Completes the access. Only valid for memory operations. */ 1055569Snate@binkert.org Fault completeAcc(PacketPtr pkt); 1065569Snate@binkert.org 1071917SN/A private: 1085569Snate@binkert.org /** Initializes variables. */ 1091917SN/A void initVars(); 1105569Snate@binkert.org 1115569Snate@binkert.org protected: 1125569Snate@binkert.org /** Values to be written to the destination misc. registers. */ 1135569Snate@binkert.org MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; 1145569Snate@binkert.org 1151917SN/A /** Indexes of the destination misc. registers. They are needed to defer 1165569Snate@binkert.org * the write accesses to the misc. registers until the commit stage, when 1175569Snate@binkert.org * the instruction is out of its speculative state. 1181977SN/A */ 1195569Snate@binkert.org short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; 1205569Snate@binkert.org 1211917SN/A /** Number of destination misc. registers. */ 1221917SN/A uint8_t _numDestMiscRegs; 1235569Snate@binkert.org 1245569Snate@binkert.org 1251917SN/A public: 126#if TRACING_ON 127 /** Tick records used for the pipeline activity viewer. */ 128 Tick fetchTick; // instruction fetch is completed. 129 int32_t decodeTick; // instruction enters decode phase 130 int32_t renameTick; // instruction enters rename phase 131 int32_t dispatchTick; 132 int32_t issueTick; 133 int32_t completeTick; 134 int32_t commitTick; 135#endif 136 137 /** Reads a misc. register, including any side-effects the read 138 * might have as defined by the architecture. 139 */ 140 MiscReg readMiscReg(int misc_reg) 141 { 142 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 143 } 144 145 /** Sets a misc. register, including any side-effects the write 146 * might have as defined by the architecture. 147 */ 148 void setMiscReg(int misc_reg, const MiscReg &val) 149 { 150 /** Writes to misc. registers are recorded and deferred until the 151 * commit stage, when updateMiscRegs() is called. 152 */ 153 assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 154 _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 155 _destMiscRegVal[_numDestMiscRegs] = val; 156 _numDestMiscRegs++; 157 } 158 159 /** Reads a misc. register, including any side-effects the read 160 * might have as defined by the architecture. 161 */ 162 TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 163 { 164 return this->cpu->readMiscReg( 165 si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 166 this->threadNumber); 167 } 168 169 /** Sets a misc. register, including any side-effects the write 170 * might have as defined by the architecture. 171 */ 172 void setMiscRegOperand(const StaticInst *si, int idx, 173 const MiscReg &val) 174 { 175 int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 176 setMiscReg(misc_reg, val); 177 } 178 179 /** Called at the commit stage to update the misc. registers. */ 180 void updateMiscRegs() 181 { 182 // @todo: Pretty convoluted way to avoid squashing from happening when 183 // using the TC during an instruction's execution (specifically for 184 // instructions that have side-effects that use the TC). Fix this. 185 // See cpu/o3/dyn_inst_impl.hh. 186 bool in_syscall = this->thread->inSyscall; 187 this->thread->inSyscall = true; 188 189 for (int i = 0; i < _numDestMiscRegs; i++) 190 this->cpu->setMiscReg( 191 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 192 193 this->thread->inSyscall = in_syscall; 194 } 195 196 void forwardOldRegs() 197 { 198 199 for (int idx = 0; idx < this->numDestRegs(); idx++) { 200 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 201 TheISA::RegIndex original_dest_reg = this->staticInst->destRegIdx(idx); 202 if (original_dest_reg < TheISA::FP_Base_DepTag) 203 this->setIntRegOperand(this->staticInst.get(), idx, this->cpu->readIntReg(prev_phys_reg)); 204 else if (original_dest_reg < TheISA::Ctrl_Base_DepTag) 205 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg)); 206 } 207 } 208 /** Calls hardware return from error interrupt. */ 209 Fault hwrei(); 210 /** Traps to handle specified fault. */ 211 void trap(Fault fault); 212 bool simPalCheck(int palFunc); 213 214 /** Emulates a syscall. */ 215 void syscall(int64_t callnum); 216 217 public: 218 219 // The register accessor methods provide the index of the 220 // instruction's operand (e.g., 0 or 1), not the architectural 221 // register index, to simplify the implementation of register 222 // renaming. We find the architectural register index by indexing 223 // into the instruction's own operand index table. Note that a 224 // raw pointer to the StaticInst is provided instead of a 225 // ref-counted StaticInstPtr to redice overhead. This is fine as 226 // long as these methods don't copy the pointer into any long-term 227 // storage (which is pretty hard to imagine they would have reason 228 // to do). 229 230 uint64_t readIntRegOperand(const StaticInst *si, int idx) 231 { 232 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 233 } 234 235 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 236 { 237 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 238 } 239 240 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 241 { 242 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 243 } 244 245 /** @todo: Make results into arrays so they can handle multiple dest 246 * registers. 247 */ 248 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 249 { 250 this->cpu->setIntReg(this->_destRegIdx[idx], val); 251 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 252 } 253 254 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 255 { 256 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 257 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 258 } 259 260 void setFloatRegOperandBits(const StaticInst *si, int idx, 261 FloatRegBits val) 262 { 263 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 264 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 265 } 266 267#if THE_ISA == MIPS_ISA 268 uint64_t readRegOtherThread(int misc_reg) 269 { 270 panic("MIPS MT not defined for O3 CPU.\n"); 271 return 0; 272 } 273 274 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 275 { 276 panic("MIPS MT not defined for O3 CPU.\n"); 277 } 278#endif 279 280 public: 281 /** Calculates EA part of a memory instruction. Currently unused, 282 * though it may be useful in the future if we want to split 283 * memory operations into EA calculation and memory access parts. 284 */ 285 Fault calcEA() 286 { 287 return this->staticInst->eaCompInst()->execute(this, this->traceData); 288 } 289 290 /** Does the memory access part of a memory instruction. Currently unused, 291 * though it may be useful in the future if we want to split 292 * memory operations into EA calculation and memory access parts. 293 */ 294 Fault memAccess() 295 { 296 return this->staticInst->memAccInst()->execute(this, this->traceData); 297 } 298}; 299 300#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 301 302