dyn_inst.hh revision 12104:edd63f9c6184
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_O3_DYN_INST_HH__
45#define __CPU_O3_DYN_INST_HH__
46
47#include <array>
48
49#include "arch/isa_traits.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/base_dyn_inst.hh"
54#include "cpu/inst_seq.hh"
55#include "cpu/reg_class.hh"
56
57class Packet;
58
59template <class Impl>
60class BaseO3DynInst : public BaseDynInst<Impl>
61{
62  public:
63    /** Typedef for the CPU. */
64    typedef typename Impl::O3CPU O3CPU;
65
66    /** Binary machine instruction type. */
67    typedef TheISA::MachInst MachInst;
68    /** Extended machine instruction type. */
69    typedef TheISA::ExtMachInst ExtMachInst;
70    /** Register types. */
71    typedef TheISA::IntReg   IntReg;
72    typedef TheISA::FloatReg FloatReg;
73    typedef TheISA::FloatRegBits FloatRegBits;
74    typedef TheISA::CCReg   CCReg;
75
76    /** Misc register type. */
77    typedef TheISA::MiscReg  MiscReg;
78
79    enum {
80        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
81        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
82    };
83
84  public:
85    /** BaseDynInst constructor given a binary instruction. */
86    BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
87                  TheISA::PCState pc, TheISA::PCState predPC,
88                  InstSeqNum seq_num, O3CPU *cpu);
89
90    /** BaseDynInst constructor given a static inst pointer. */
91    BaseO3DynInst(const StaticInstPtr &_staticInst,
92                  const StaticInstPtr &_macroop);
93
94    ~BaseO3DynInst();
95
96    /** Executes the instruction.*/
97    Fault execute();
98
99    /** Initiates the access.  Only valid for memory operations. */
100    Fault initiateAcc();
101
102    /** Completes the access.  Only valid for memory operations. */
103    Fault completeAcc(PacketPtr pkt);
104
105  private:
106    /** Initializes variables. */
107    void initVars();
108
109  protected:
110    /** Values to be written to the destination misc. registers. */
111    std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
112
113    /** Indexes of the destination misc. registers. They are needed to defer
114     * the write accesses to the misc. registers until the commit stage, when
115     * the instruction is out of its speculative state.
116     */
117    std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
118
119    /** Number of destination misc. registers. */
120    uint8_t _numDestMiscRegs;
121
122
123  public:
124#if TRACING_ON
125    /** Tick records used for the pipeline activity viewer. */
126    Tick fetchTick;	     // instruction fetch is completed.
127    int32_t decodeTick;  // instruction enters decode phase
128    int32_t renameTick;  // instruction enters rename phase
129    int32_t dispatchTick;
130    int32_t issueTick;
131    int32_t completeTick;
132    int32_t commitTick;
133    int32_t storeTick;
134#endif
135
136    /** Reads a misc. register, including any side-effects the read
137     * might have as defined by the architecture.
138     */
139    MiscReg readMiscReg(int misc_reg)
140    {
141        return this->cpu->readMiscReg(misc_reg, this->threadNumber);
142    }
143
144    /** Sets a misc. register, including any side-effects the write
145     * might have as defined by the architecture.
146     */
147    void setMiscReg(int misc_reg, const MiscReg &val)
148    {
149        /** Writes to misc. registers are recorded and deferred until the
150         * commit stage, when updateMiscRegs() is called. First, check if
151         * the misc reg has been written before and update its value to be
152         * committed instead of making a new entry. If not, make a new
153         * entry and record the write.
154         */
155        for (int idx = 0; idx < _numDestMiscRegs; idx++) {
156            if (_destMiscRegIdx[idx] == misc_reg) {
157               _destMiscRegVal[idx] = val;
158               return;
159            }
160        }
161
162        assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
163        _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
164        _destMiscRegVal[_numDestMiscRegs] = val;
165        _numDestMiscRegs++;
166    }
167
168    /** Reads a misc. register, including any side-effects the read
169     * might have as defined by the architecture.
170     */
171    TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
172    {
173        RegId reg = si->srcRegIdx(idx);
174        assert(reg.regClass == MiscRegClass);
175        return this->cpu->readMiscReg(reg.regIdx, this->threadNumber);
176    }
177
178    /** Sets a misc. register, including any side-effects the write
179     * might have as defined by the architecture.
180     */
181    void setMiscRegOperand(const StaticInst *si, int idx,
182                                     const MiscReg &val)
183    {
184        RegId reg =  si->destRegIdx(idx);
185        assert(reg.regClass == MiscRegClass);
186        setMiscReg(reg.regIdx, val);
187    }
188
189    /** Called at the commit stage to update the misc. registers. */
190    void updateMiscRegs()
191    {
192        // @todo: Pretty convoluted way to avoid squashing from happening when
193        // using the TC during an instruction's execution (specifically for
194        // instructions that have side-effects that use the TC).  Fix this.
195        // See cpu/o3/dyn_inst_impl.hh.
196        bool no_squash_from_TC = this->thread->noSquashFromTC;
197        this->thread->noSquashFromTC = true;
198
199        for (int i = 0; i < _numDestMiscRegs; i++)
200            this->cpu->setMiscReg(
201                _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
202
203        this->thread->noSquashFromTC = no_squash_from_TC;
204    }
205
206    void forwardOldRegs()
207    {
208
209        for (int idx = 0; idx < this->numDestRegs(); idx++) {
210            PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx);
211            RegId original_dest_reg =
212                this->staticInst->destRegIdx(idx);
213            switch (original_dest_reg.regClass) {
214              case IntRegClass:
215                this->setIntRegOperand(this->staticInst.get(), idx,
216                                       this->cpu->readIntReg(prev_phys_reg));
217                break;
218              case FloatRegClass:
219                this->setFloatRegOperandBits(this->staticInst.get(), idx,
220                                             this->cpu->readFloatRegBits(prev_phys_reg));
221                break;
222              case CCRegClass:
223                this->setCCRegOperand(this->staticInst.get(), idx,
224                                      this->cpu->readCCReg(prev_phys_reg));
225                break;
226              case MiscRegClass:
227                // no need to forward misc reg values
228                break;
229            }
230        }
231    }
232    /** Calls hardware return from error interrupt. */
233    Fault hwrei();
234    /** Traps to handle specified fault. */
235    void trap(const Fault &fault);
236    bool simPalCheck(int palFunc);
237
238    /** Emulates a syscall. */
239    void syscall(int64_t callnum, Fault *fault);
240
241  public:
242
243    // The register accessor methods provide the index of the
244    // instruction's operand (e.g., 0 or 1), not the architectural
245    // register index, to simplify the implementation of register
246    // renaming.  We find the architectural register index by indexing
247    // into the instruction's own operand index table.  Note that a
248    // raw pointer to the StaticInst is provided instead of a
249    // ref-counted StaticInstPtr to redice overhead.  This is fine as
250    // long as these methods don't copy the pointer into any long-term
251    // storage (which is pretty hard to imagine they would have reason
252    // to do).
253
254    IntReg readIntRegOperand(const StaticInst *si, int idx)
255    {
256        return this->cpu->readIntReg(this->_srcRegIdx[idx]);
257    }
258
259    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
260    {
261        return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
262    }
263
264    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
265    {
266        return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
267    }
268
269    CCReg readCCRegOperand(const StaticInst *si, int idx)
270    {
271        return this->cpu->readCCReg(this->_srcRegIdx[idx]);
272    }
273
274    /** @todo: Make results into arrays so they can handle multiple dest
275     *  registers.
276     */
277    void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
278    {
279        this->cpu->setIntReg(this->_destRegIdx[idx], val);
280        BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
281    }
282
283    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
284    {
285        this->cpu->setFloatReg(this->_destRegIdx[idx], val);
286        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
287    }
288
289    void setFloatRegOperandBits(const StaticInst *si, int idx,
290                                FloatRegBits val)
291    {
292        this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
293        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
294    }
295
296    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
297    {
298        this->cpu->setCCReg(this->_destRegIdx[idx], val);
299        BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
300    }
301
302#if THE_ISA == MIPS_ISA
303    MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid)
304    {
305        panic("MIPS MT not defined for O3 CPU.\n");
306        return 0;
307    }
308
309    void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid)
310    {
311        panic("MIPS MT not defined for O3 CPU.\n");
312    }
313#endif
314
315  public:
316    /** Calculates EA part of a memory instruction. Currently unused,
317     * though it may be useful in the future if we want to split
318     * memory operations into EA calculation and memory access parts.
319     */
320    Fault calcEA()
321    {
322        return this->staticInst->eaCompInst()->execute(this, this->traceData);
323    }
324
325    /** Does the memory access part of a memory instruction. Currently unused,
326     * though it may be useful in the future if we want to split
327     * memory operations into EA calculation and memory access parts.
328     */
329    Fault memAccess()
330    {
331        return this->staticInst->memAccInst()->execute(this, this->traceData);
332    }
333};
334
335#endif // __CPU_O3_ALPHA_DYN_INST_HH__
336
337