dyn_inst.hh revision 10935:acd48ddd725f
19022Sgblack@eecs.umich.edu/* 212763Sgiacomo.travaglini@arm.com * Copyright (c) 2010 ARM Limited 310037SARM gem5 Developers * Copyright (c) 2013 Advanced Micro Devices, Inc. 410037SARM gem5 Developers * All rights reserved 510037SARM gem5 Developers * 610037SARM gem5 Developers * The license below extends only to copyright in the software and shall 710037SARM gem5 Developers * not be construed as granting a license to any other intellectual 810037SARM gem5 Developers * property including but not limited to intellectual property relating 910037SARM gem5 Developers * to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 149023Sgblack@eecs.umich.edu * 159022Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 169022Sgblack@eecs.umich.edu * All rights reserved. 179022Sgblack@eecs.umich.edu * 189022Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 199022Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 209022Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 219022Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 229022Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 239022Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 249022Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 259022Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 269022Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 279022Sgblack@eecs.umich.edu * this software without specific prior written permission. 289022Sgblack@eecs.umich.edu * 299022Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 309022Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 319022Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 329022Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 339022Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349022Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359022Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369022Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379022Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389022Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399022Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409022Sgblack@eecs.umich.edu * 419022Sgblack@eecs.umich.edu * Authors: Kevin Lim 429022Sgblack@eecs.umich.edu */ 439022Sgblack@eecs.umich.edu 4411165SRekai.GonzalezAlberquilla@arm.com#ifndef __CPU_O3_DYN_INST_HH__ 4511165SRekai.GonzalezAlberquilla@arm.com#define __CPU_O3_DYN_INST_HH__ 469023Sgblack@eecs.umich.edu 479023Sgblack@eecs.umich.edu#include <array> 489023Sgblack@eecs.umich.edu 499023Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 509022Sgblack@eecs.umich.edu#include "config/the_isa.hh" 519022Sgblack@eecs.umich.edu#include "cpu/o3/cpu.hh" 529022Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 539022Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 549024Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 559022Sgblack@eecs.umich.edu#include "cpu/reg_class.hh" 5611165SRekai.GonzalezAlberquilla@arm.com 5711165SRekai.GonzalezAlberquilla@arm.comclass Packet; 5811165SRekai.GonzalezAlberquilla@arm.com 5911165SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 6010610SAndreas.Sandberg@ARM.comclass BaseO3DynInst : public BaseDynInst<Impl> 6110610SAndreas.Sandberg@ARM.com{ 6210610SAndreas.Sandberg@ARM.com public: 6310610SAndreas.Sandberg@ARM.com /** Typedef for the CPU. */ 6410610SAndreas.Sandberg@ARM.com typedef typename Impl::O3CPU O3CPU; 6510610SAndreas.Sandberg@ARM.com 6610610SAndreas.Sandberg@ARM.com /** Binary machine instruction type. */ 6710610SAndreas.Sandberg@ARM.com typedef TheISA::MachInst MachInst; 6810610SAndreas.Sandberg@ARM.com /** Extended machine instruction type. */ 6910610SAndreas.Sandberg@ARM.com typedef TheISA::ExtMachInst ExtMachInst; 7010610SAndreas.Sandberg@ARM.com /** Logical register index type. */ 7110610SAndreas.Sandberg@ARM.com typedef TheISA::RegIndex RegIndex; 7210610SAndreas.Sandberg@ARM.com /** Integer register index type. */ 7310610SAndreas.Sandberg@ARM.com typedef TheISA::IntReg IntReg; 7410610SAndreas.Sandberg@ARM.com typedef TheISA::FloatReg FloatReg; 759023Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 769023Sgblack@eecs.umich.edu typedef TheISA::CCReg CCReg; 779023Sgblack@eecs.umich.edu 789023Sgblack@eecs.umich.edu /** Misc register index type. */ 799023Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 809023Sgblack@eecs.umich.edu 819023Sgblack@eecs.umich.edu enum { 829023Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 8310037SARM gem5 Developers MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 8410037SARM gem5 Developers }; 8510037SARM gem5 Developers 8610037SARM gem5 Developers public: 8710037SARM gem5 Developers /** BaseDynInst constructor given a binary instruction. */ 889023Sgblack@eecs.umich.edu BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 899023Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 909023Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 919023Sgblack@eecs.umich.edu 929023Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 939023Sgblack@eecs.umich.edu BaseO3DynInst(const StaticInstPtr &_staticInst, 949023Sgblack@eecs.umich.edu const StaticInstPtr &_macroop); 959023Sgblack@eecs.umich.edu 969023Sgblack@eecs.umich.edu ~BaseO3DynInst(); 979023Sgblack@eecs.umich.edu 989023Sgblack@eecs.umich.edu /** Executes the instruction.*/ 999023Sgblack@eecs.umich.edu Fault execute(); 1009023Sgblack@eecs.umich.edu 1019023Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 1029023Sgblack@eecs.umich.edu Fault initiateAcc(); 1039023Sgblack@eecs.umich.edu 1049023Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 1059023Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 1069023Sgblack@eecs.umich.edu 1079023Sgblack@eecs.umich.edu private: 1089023Sgblack@eecs.umich.edu /** Initializes variables. */ 1099023Sgblack@eecs.umich.edu void initVars(); 1109023Sgblack@eecs.umich.edu 1119023Sgblack@eecs.umich.edu protected: 1129023Sgblack@eecs.umich.edu /** Values to be written to the destination misc. registers. */ 1139023Sgblack@eecs.umich.edu std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 1149023Sgblack@eecs.umich.edu 1159023Sgblack@eecs.umich.edu /** Indexes of the destination misc. registers. They are needed to defer 1169023Sgblack@eecs.umich.edu * the write accesses to the misc. registers until the commit stage, when 1179023Sgblack@eecs.umich.edu * the instruction is out of its speculative state. 1189023Sgblack@eecs.umich.edu */ 1199023Sgblack@eecs.umich.edu std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 1209023Sgblack@eecs.umich.edu 1219023Sgblack@eecs.umich.edu /** Number of destination misc. registers. */ 1229023Sgblack@eecs.umich.edu uint8_t _numDestMiscRegs; 1239023Sgblack@eecs.umich.edu 1249023Sgblack@eecs.umich.edu 1259023Sgblack@eecs.umich.edu public: 1269023Sgblack@eecs.umich.edu#if TRACING_ON 1279023Sgblack@eecs.umich.edu /** Tick records used for the pipeline activity viewer. */ 1289023Sgblack@eecs.umich.edu Tick fetchTick; // instruction fetch is completed. 1299023Sgblack@eecs.umich.edu int32_t decodeTick; // instruction enters decode phase 1309023Sgblack@eecs.umich.edu int32_t renameTick; // instruction enters rename phase 1319023Sgblack@eecs.umich.edu int32_t dispatchTick; 1329023Sgblack@eecs.umich.edu int32_t issueTick; 1339023Sgblack@eecs.umich.edu int32_t completeTick; 1349023Sgblack@eecs.umich.edu int32_t commitTick; 1359023Sgblack@eecs.umich.edu int32_t storeTick; 1369023Sgblack@eecs.umich.edu#endif 1379023Sgblack@eecs.umich.edu 1389023Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1399023Sgblack@eecs.umich.edu * might have as defined by the architecture. 1409022Sgblack@eecs.umich.edu */ 1419023Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 14210610SAndreas.Sandberg@ARM.com { 14310610SAndreas.Sandberg@ARM.com return this->cpu->readMiscReg(misc_reg, this->threadNumber); 14410610SAndreas.Sandberg@ARM.com } 14510610SAndreas.Sandberg@ARM.com 14610611SAndreas.Sandberg@ARM.com /** Sets a misc. register, including any side-effects the write 14710610SAndreas.Sandberg@ARM.com * might have as defined by the architecture. 14810610SAndreas.Sandberg@ARM.com */ 14910610SAndreas.Sandberg@ARM.com void setMiscReg(int misc_reg, const MiscReg &val) 15010610SAndreas.Sandberg@ARM.com { 1519023Sgblack@eecs.umich.edu /** Writes to misc. registers are recorded and deferred until the 1529023Sgblack@eecs.umich.edu * commit stage, when updateMiscRegs() is called. First, check if 1539023Sgblack@eecs.umich.edu * the misc reg has been written before and update its value to be 1549023Sgblack@eecs.umich.edu * committed instead of making a new entry. If not, make a new 1559023Sgblack@eecs.umich.edu * entry and record the write. 1569023Sgblack@eecs.umich.edu */ 15710037SARM gem5 Developers for (int idx = 0; idx < _numDestMiscRegs; idx++) { 1589374Sgblack@eecs.umich.edu if (_destMiscRegIdx[idx] == misc_reg) { 1599374Sgblack@eecs.umich.edu _destMiscRegVal[idx] = val; 1609023Sgblack@eecs.umich.edu return; 16110611SAndreas.Sandberg@ARM.com } 16210611SAndreas.Sandberg@ARM.com } 16310611SAndreas.Sandberg@ARM.com 16410611SAndreas.Sandberg@ARM.com assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 1659023Sgblack@eecs.umich.edu _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1669023Sgblack@eecs.umich.edu _destMiscRegVal[_numDestMiscRegs] = val; 1679023Sgblack@eecs.umich.edu _numDestMiscRegs++; 1689023Sgblack@eecs.umich.edu } 16910610SAndreas.Sandberg@ARM.com 17010610SAndreas.Sandberg@ARM.com /** Reads a misc. register, including any side-effects the read 17110610SAndreas.Sandberg@ARM.com * might have as defined by the architecture. 17210610SAndreas.Sandberg@ARM.com */ 17310610SAndreas.Sandberg@ARM.com TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 17410610SAndreas.Sandberg@ARM.com { 17510610SAndreas.Sandberg@ARM.com return this->cpu->readMiscReg( 17610610SAndreas.Sandberg@ARM.com si->srcRegIdx(idx) - TheISA::Misc_Reg_Base, 17710610SAndreas.Sandberg@ARM.com this->threadNumber); 17810610SAndreas.Sandberg@ARM.com } 17910610SAndreas.Sandberg@ARM.com 18010610SAndreas.Sandberg@ARM.com /** Sets a misc. register, including any side-effects the write 18110610SAndreas.Sandberg@ARM.com * might have as defined by the architecture. 18212763Sgiacomo.travaglini@arm.com */ 18312763Sgiacomo.travaglini@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 18410610SAndreas.Sandberg@ARM.com const MiscReg &val) 18510610SAndreas.Sandberg@ARM.com { 18610610SAndreas.Sandberg@ARM.com int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 18710610SAndreas.Sandberg@ARM.com setMiscReg(misc_reg, val); 18810610SAndreas.Sandberg@ARM.com } 18910610SAndreas.Sandberg@ARM.com 19010610SAndreas.Sandberg@ARM.com /** Called at the commit stage to update the misc. registers. */ 1919023Sgblack@eecs.umich.edu void updateMiscRegs() 19210610SAndreas.Sandberg@ARM.com { 19310610SAndreas.Sandberg@ARM.com // @todo: Pretty convoluted way to avoid squashing from happening when 194 // using the TC during an instruction's execution (specifically for 195 // instructions that have side-effects that use the TC). Fix this. 196 // See cpu/o3/dyn_inst_impl.hh. 197 bool no_squash_from_TC = this->thread->noSquashFromTC; 198 this->thread->noSquashFromTC = true; 199 200 for (int i = 0; i < _numDestMiscRegs; i++) 201 this->cpu->setMiscReg( 202 _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 203 204 this->thread->noSquashFromTC = no_squash_from_TC; 205 } 206 207 void forwardOldRegs() 208 { 209 210 for (int idx = 0; idx < this->numDestRegs(); idx++) { 211 PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 212 TheISA::RegIndex original_dest_reg = 213 this->staticInst->destRegIdx(idx); 214 switch (regIdxToClass(original_dest_reg)) { 215 case IntRegClass: 216 this->setIntRegOperand(this->staticInst.get(), idx, 217 this->cpu->readIntReg(prev_phys_reg)); 218 break; 219 case FloatRegClass: 220 this->setFloatRegOperandBits(this->staticInst.get(), idx, 221 this->cpu->readFloatRegBits(prev_phys_reg)); 222 break; 223 case CCRegClass: 224 this->setCCRegOperand(this->staticInst.get(), idx, 225 this->cpu->readCCReg(prev_phys_reg)); 226 break; 227 case MiscRegClass: 228 // no need to forward misc reg values 229 break; 230 } 231 } 232 } 233 /** Calls hardware return from error interrupt. */ 234 Fault hwrei(); 235 /** Traps to handle specified fault. */ 236 void trap(const Fault &fault); 237 bool simPalCheck(int palFunc); 238 239 /** Emulates a syscall. */ 240 void syscall(int64_t callnum); 241 242 public: 243 244 // The register accessor methods provide the index of the 245 // instruction's operand (e.g., 0 or 1), not the architectural 246 // register index, to simplify the implementation of register 247 // renaming. We find the architectural register index by indexing 248 // into the instruction's own operand index table. Note that a 249 // raw pointer to the StaticInst is provided instead of a 250 // ref-counted StaticInstPtr to redice overhead. This is fine as 251 // long as these methods don't copy the pointer into any long-term 252 // storage (which is pretty hard to imagine they would have reason 253 // to do). 254 255 IntReg readIntRegOperand(const StaticInst *si, int idx) 256 { 257 return this->cpu->readIntReg(this->_srcRegIdx[idx]); 258 } 259 260 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 261 { 262 return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 263 } 264 265 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 266 { 267 return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 268 } 269 270 CCReg readCCRegOperand(const StaticInst *si, int idx) 271 { 272 return this->cpu->readCCReg(this->_srcRegIdx[idx]); 273 } 274 275 /** @todo: Make results into arrays so they can handle multiple dest 276 * registers. 277 */ 278 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 279 { 280 this->cpu->setIntReg(this->_destRegIdx[idx], val); 281 BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 282 } 283 284 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 285 { 286 this->cpu->setFloatReg(this->_destRegIdx[idx], val); 287 BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 288 } 289 290 void setFloatRegOperandBits(const StaticInst *si, int idx, 291 FloatRegBits val) 292 { 293 this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 294 BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 295 } 296 297 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 298 { 299 this->cpu->setCCReg(this->_destRegIdx[idx], val); 300 BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 301 } 302 303#if THE_ISA == MIPS_ISA 304 MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 305 { 306 panic("MIPS MT not defined for O3 CPU.\n"); 307 return 0; 308 } 309 310 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 311 { 312 panic("MIPS MT not defined for O3 CPU.\n"); 313 } 314#endif 315 316 public: 317 /** Calculates EA part of a memory instruction. Currently unused, 318 * though it may be useful in the future if we want to split 319 * memory operations into EA calculation and memory access parts. 320 */ 321 Fault calcEA() 322 { 323 return this->staticInst->eaCompInst()->execute(this, this->traceData); 324 } 325 326 /** Does the memory access part of a memory instruction. Currently unused, 327 * though it may be useful in the future if we want to split 328 * memory operations into EA calculation and memory access parts. 329 */ 330 Fault memAccess() 331 { 332 return this->staticInst->memAccInst()->execute(this, this->traceData); 333 } 334}; 335 336#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 337 338