dyn_inst.hh revision 7783
12847Sksewell@umich.edu/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 37783SGiacomo.Gabrielli@arm.com * All rights reserved 47783SGiacomo.Gabrielli@arm.com * 57783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137783SGiacomo.Gabrielli@arm.com * 145596Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152847Sksewell@umich.edu * All rights reserved. 162847Sksewell@umich.edu * 172847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182847Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232847Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262847Sksewell@umich.edu * this software without specific prior written permission. 272847Sksewell@umich.edu * 282847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392847Sksewell@umich.edu * 405596Sgblack@eecs.umich.edu * Authors: Kevin Lim 412847Sksewell@umich.edu */ 422847Sksewell@umich.edu 432847Sksewell@umich.edu#ifndef __CPU_O3_DYN_INST_HH__ 442847Sksewell@umich.edu#define __CPU_O3_DYN_INST_HH__ 452847Sksewell@umich.edu 465596Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 485596Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 495596Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 505596Sgblack@eecs.umich.edu#include "cpu/o3/cpu.hh" 515596Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 522847Sksewell@umich.edu 535596Sgblack@eecs.umich.educlass Packet; 545596Sgblack@eecs.umich.edu 555596Sgblack@eecs.umich.edu/** 565596Sgblack@eecs.umich.edu * Mostly implementation & ISA specific AlphaDynInst. As with most 575596Sgblack@eecs.umich.edu * other classes in the new CPU model, it is templated on the Impl to 585596Sgblack@eecs.umich.edu * allow for passing in of all types, such as the CPU type and the ISA 595596Sgblack@eecs.umich.edu * type. The AlphaDynInst serves as the primary interface to the CPU 605596Sgblack@eecs.umich.edu * for instructions that are executing. 615596Sgblack@eecs.umich.edu */ 625596Sgblack@eecs.umich.edutemplate <class Impl> 635596Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 645596Sgblack@eecs.umich.edu{ 655596Sgblack@eecs.umich.edu public: 665596Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 675596Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 685596Sgblack@eecs.umich.edu 695596Sgblack@eecs.umich.edu /** Binary machine instruction type. */ 705596Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 715596Sgblack@eecs.umich.edu /** Extended machine instruction type. */ 725596Sgblack@eecs.umich.edu typedef TheISA::ExtMachInst ExtMachInst; 735596Sgblack@eecs.umich.edu /** Logical register index type. */ 745596Sgblack@eecs.umich.edu typedef TheISA::RegIndex RegIndex; 755596Sgblack@eecs.umich.edu /** Integer register index type. */ 765596Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 775596Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 785596Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 795596Sgblack@eecs.umich.edu /** Misc register index type. */ 805596Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 815596Sgblack@eecs.umich.edu 825596Sgblack@eecs.umich.edu enum { 835596Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 845596Sgblack@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 855596Sgblack@eecs.umich.edu }; 865596Sgblack@eecs.umich.edu 875596Sgblack@eecs.umich.edu public: 885596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 897720Sgblack@eecs.umich.edu BaseO3DynInst(StaticInstPtr staticInst, 907720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 917720Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 925596Sgblack@eecs.umich.edu 935596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 947720Sgblack@eecs.umich.edu BaseO3DynInst(ExtMachInst inst, 957720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 967720Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 975596Sgblack@eecs.umich.edu 985596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 995596Sgblack@eecs.umich.edu BaseO3DynInst(StaticInstPtr &_staticInst); 1005596Sgblack@eecs.umich.edu 1015596Sgblack@eecs.umich.edu /** Executes the instruction.*/ 1025596Sgblack@eecs.umich.edu Fault execute(); 1035596Sgblack@eecs.umich.edu 1045596Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 1055596Sgblack@eecs.umich.edu Fault initiateAcc(); 1065596Sgblack@eecs.umich.edu 1075596Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 1085596Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 1095596Sgblack@eecs.umich.edu 1105596Sgblack@eecs.umich.edu private: 1115596Sgblack@eecs.umich.edu /** Initializes variables. */ 1125596Sgblack@eecs.umich.edu void initVars(); 1135596Sgblack@eecs.umich.edu 1147783SGiacomo.Gabrielli@arm.com protected: 1157783SGiacomo.Gabrielli@arm.com /** Indexes of the destination misc. registers. They are needed to defer 1167783SGiacomo.Gabrielli@arm.com * the write accesses to the misc. registers until the commit stage, when 1177783SGiacomo.Gabrielli@arm.com * the instruction is out of its speculative state. 1187783SGiacomo.Gabrielli@arm.com */ 1197783SGiacomo.Gabrielli@arm.com int _destMiscRegIdx[MaxInstDestRegs]; 1207783SGiacomo.Gabrielli@arm.com /** Values to be written to the destination misc. registers. */ 1217783SGiacomo.Gabrielli@arm.com MiscReg _destMiscRegVal[MaxInstDestRegs]; 1227783SGiacomo.Gabrielli@arm.com /** Number of destination misc. registers. */ 1237783SGiacomo.Gabrielli@arm.com int _numDestMiscRegs; 1247783SGiacomo.Gabrielli@arm.com 1255596Sgblack@eecs.umich.edu public: 1265596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1275596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1285596Sgblack@eecs.umich.edu */ 1295596Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 1305596Sgblack@eecs.umich.edu { 1315596Sgblack@eecs.umich.edu return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1325596Sgblack@eecs.umich.edu } 1335596Sgblack@eecs.umich.edu 1345596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1355596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1365596Sgblack@eecs.umich.edu */ 1375596Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 1385596Sgblack@eecs.umich.edu { 1397783SGiacomo.Gabrielli@arm.com /** Writes to misc. registers are recorded and deferred until the 1407783SGiacomo.Gabrielli@arm.com * commit stage, when updateMiscRegs() is called. 1417783SGiacomo.Gabrielli@arm.com */ 1427783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1437783SGiacomo.Gabrielli@arm.com _destMiscRegVal[_numDestMiscRegs] = val; 1447783SGiacomo.Gabrielli@arm.com _numDestMiscRegs++; 1455596Sgblack@eecs.umich.edu } 1465596Sgblack@eecs.umich.edu 1475596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1485596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1495596Sgblack@eecs.umich.edu */ 1505596Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 1515596Sgblack@eecs.umich.edu { 1525596Sgblack@eecs.umich.edu return this->cpu->readMiscReg( 1535596Sgblack@eecs.umich.edu si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 1545596Sgblack@eecs.umich.edu this->threadNumber); 1555596Sgblack@eecs.umich.edu } 1565596Sgblack@eecs.umich.edu 1575596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1585596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1595596Sgblack@eecs.umich.edu */ 1605596Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, 1615596Sgblack@eecs.umich.edu const MiscReg &val) 1625596Sgblack@eecs.umich.edu { 1637783SGiacomo.Gabrielli@arm.com int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 1647783SGiacomo.Gabrielli@arm.com setMiscReg(misc_reg, val); 1657783SGiacomo.Gabrielli@arm.com } 1667783SGiacomo.Gabrielli@arm.com 1677783SGiacomo.Gabrielli@arm.com /** Called at the commit stage to update the misc. registers. */ 1687783SGiacomo.Gabrielli@arm.com void updateMiscRegs() 1697783SGiacomo.Gabrielli@arm.com { 1707783SGiacomo.Gabrielli@arm.com // @todo: Pretty convoluted way to avoid squashing from happening when 1717783SGiacomo.Gabrielli@arm.com // using the TC during an instruction's execution (specifically for 1727783SGiacomo.Gabrielli@arm.com // instructions that have side-effects that use the TC). Fix this. 1737783SGiacomo.Gabrielli@arm.com // See cpu/o3/dyn_inst_impl.hh. 1747783SGiacomo.Gabrielli@arm.com bool in_syscall = this->thread->inSyscall; 1757783SGiacomo.Gabrielli@arm.com this->thread->inSyscall = true; 1767783SGiacomo.Gabrielli@arm.com 1777783SGiacomo.Gabrielli@arm.com for (int i = 0; i < _numDestMiscRegs; i++) 1787783SGiacomo.Gabrielli@arm.com this->cpu->setMiscReg( 1797783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 1807783SGiacomo.Gabrielli@arm.com 1817783SGiacomo.Gabrielli@arm.com this->thread->inSyscall = in_syscall; 1825596Sgblack@eecs.umich.edu } 1835596Sgblack@eecs.umich.edu 1845596Sgblack@eecs.umich.edu#if FULL_SYSTEM 1855702Ssaidi@eecs.umich.edu /** Calls hardware return from error interrupt. */ 1865702Ssaidi@eecs.umich.edu Fault hwrei(); 1875596Sgblack@eecs.umich.edu /** Traps to handle specified fault. */ 1885596Sgblack@eecs.umich.edu void trap(Fault fault); 1895702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1902935Sksewell@umich.edu#else 1915596Sgblack@eecs.umich.edu /** Calls a syscall. */ 1925596Sgblack@eecs.umich.edu void syscall(int64_t callnum); 1932848Sksewell@umich.edu#endif 1942847Sksewell@umich.edu 1955596Sgblack@eecs.umich.edu public: 1965596Sgblack@eecs.umich.edu 1975596Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 1985596Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 1995596Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 2005596Sgblack@eecs.umich.edu // renaming. We find the architectural register index by indexing 2015596Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 2025596Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 2035596Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2045596Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 2055596Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 2065596Sgblack@eecs.umich.edu // to do). 2075596Sgblack@eecs.umich.edu 2085596Sgblack@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2095596Sgblack@eecs.umich.edu { 2105596Sgblack@eecs.umich.edu return this->cpu->readIntReg(this->_srcRegIdx[idx]); 2115596Sgblack@eecs.umich.edu } 2125596Sgblack@eecs.umich.edu 2135596Sgblack@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2145596Sgblack@eecs.umich.edu { 2155596Sgblack@eecs.umich.edu return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 2165596Sgblack@eecs.umich.edu } 2175596Sgblack@eecs.umich.edu 2185596Sgblack@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2195596Sgblack@eecs.umich.edu { 2205596Sgblack@eecs.umich.edu return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 2215596Sgblack@eecs.umich.edu } 2225596Sgblack@eecs.umich.edu 2235596Sgblack@eecs.umich.edu /** @todo: Make results into arrays so they can handle multiple dest 2245596Sgblack@eecs.umich.edu * registers. 2255596Sgblack@eecs.umich.edu */ 2265596Sgblack@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2275596Sgblack@eecs.umich.edu { 2285596Sgblack@eecs.umich.edu this->cpu->setIntReg(this->_destRegIdx[idx], val); 2295596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 2305596Sgblack@eecs.umich.edu } 2315596Sgblack@eecs.umich.edu 2325596Sgblack@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2335596Sgblack@eecs.umich.edu { 2345596Sgblack@eecs.umich.edu this->cpu->setFloatReg(this->_destRegIdx[idx], val); 2355596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 2365596Sgblack@eecs.umich.edu } 2375596Sgblack@eecs.umich.edu 2385596Sgblack@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2395596Sgblack@eecs.umich.edu FloatRegBits val) 2405596Sgblack@eecs.umich.edu { 2415596Sgblack@eecs.umich.edu this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 2425596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 2435596Sgblack@eecs.umich.edu } 2445596Sgblack@eecs.umich.edu 2455596Sgblack@eecs.umich.edu#if THE_ISA == MIPS_ISA 2465596Sgblack@eecs.umich.edu uint64_t readRegOtherThread(int misc_reg) 2475596Sgblack@eecs.umich.edu { 2485596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 2495596Sgblack@eecs.umich.edu return 0; 2505596Sgblack@eecs.umich.edu } 2515596Sgblack@eecs.umich.edu 2525596Sgblack@eecs.umich.edu void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 2535596Sgblack@eecs.umich.edu { 2545596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 2555596Sgblack@eecs.umich.edu } 2565596Sgblack@eecs.umich.edu#endif 2575596Sgblack@eecs.umich.edu 2585596Sgblack@eecs.umich.edu public: 2595596Sgblack@eecs.umich.edu /** Calculates EA part of a memory instruction. Currently unused, 2605596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 2615596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 2625596Sgblack@eecs.umich.edu */ 2635596Sgblack@eecs.umich.edu Fault calcEA() 2645596Sgblack@eecs.umich.edu { 2655596Sgblack@eecs.umich.edu return this->staticInst->eaCompInst()->execute(this, this->traceData); 2665596Sgblack@eecs.umich.edu } 2675596Sgblack@eecs.umich.edu 2685596Sgblack@eecs.umich.edu /** Does the memory access part of a memory instruction. Currently unused, 2695596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 2705596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 2715596Sgblack@eecs.umich.edu */ 2725596Sgblack@eecs.umich.edu Fault memAccess() 2735596Sgblack@eecs.umich.edu { 2745596Sgblack@eecs.umich.edu return this->staticInst->memAccInst()->execute(this, this->traceData); 2755596Sgblack@eecs.umich.edu } 2765596Sgblack@eecs.umich.edu}; 2775596Sgblack@eecs.umich.edu 2785596Sgblack@eecs.umich.edu#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 2795596Sgblack@eecs.umich.edu 280