dyn_inst.hh revision 7720
12847Sksewell@umich.edu/* 25596Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32847Sksewell@umich.edu * All rights reserved. 42847Sksewell@umich.edu * 52847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62847Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112847Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142847Sksewell@umich.edu * this software without specific prior written permission. 152847Sksewell@umich.edu * 162847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272847Sksewell@umich.edu * 285596Sgblack@eecs.umich.edu * Authors: Kevin Lim 292847Sksewell@umich.edu */ 302847Sksewell@umich.edu 312847Sksewell@umich.edu#ifndef __CPU_O3_DYN_INST_HH__ 322847Sksewell@umich.edu#define __CPU_O3_DYN_INST_HH__ 332847Sksewell@umich.edu 345596Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 365596Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 375596Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 385596Sgblack@eecs.umich.edu#include "cpu/o3/cpu.hh" 395596Sgblack@eecs.umich.edu#include "cpu/o3/isa_specific.hh" 402847Sksewell@umich.edu 415596Sgblack@eecs.umich.educlass Packet; 425596Sgblack@eecs.umich.edu 435596Sgblack@eecs.umich.edu/** 445596Sgblack@eecs.umich.edu * Mostly implementation & ISA specific AlphaDynInst. As with most 455596Sgblack@eecs.umich.edu * other classes in the new CPU model, it is templated on the Impl to 465596Sgblack@eecs.umich.edu * allow for passing in of all types, such as the CPU type and the ISA 475596Sgblack@eecs.umich.edu * type. The AlphaDynInst serves as the primary interface to the CPU 485596Sgblack@eecs.umich.edu * for instructions that are executing. 495596Sgblack@eecs.umich.edu */ 505596Sgblack@eecs.umich.edutemplate <class Impl> 515596Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 525596Sgblack@eecs.umich.edu{ 535596Sgblack@eecs.umich.edu public: 545596Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 555596Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 565596Sgblack@eecs.umich.edu 575596Sgblack@eecs.umich.edu /** Binary machine instruction type. */ 585596Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 595596Sgblack@eecs.umich.edu /** Extended machine instruction type. */ 605596Sgblack@eecs.umich.edu typedef TheISA::ExtMachInst ExtMachInst; 615596Sgblack@eecs.umich.edu /** Logical register index type. */ 625596Sgblack@eecs.umich.edu typedef TheISA::RegIndex RegIndex; 635596Sgblack@eecs.umich.edu /** Integer register index type. */ 645596Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 655596Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 665596Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 675596Sgblack@eecs.umich.edu /** Misc register index type. */ 685596Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 695596Sgblack@eecs.umich.edu 705596Sgblack@eecs.umich.edu enum { 715596Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 725596Sgblack@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 735596Sgblack@eecs.umich.edu }; 745596Sgblack@eecs.umich.edu 755596Sgblack@eecs.umich.edu public: 765596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 777720Sgblack@eecs.umich.edu BaseO3DynInst(StaticInstPtr staticInst, 787720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 797720Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 805596Sgblack@eecs.umich.edu 815596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 827720Sgblack@eecs.umich.edu BaseO3DynInst(ExtMachInst inst, 837720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 847720Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 855596Sgblack@eecs.umich.edu 865596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 875596Sgblack@eecs.umich.edu BaseO3DynInst(StaticInstPtr &_staticInst); 885596Sgblack@eecs.umich.edu 895596Sgblack@eecs.umich.edu /** Executes the instruction.*/ 905596Sgblack@eecs.umich.edu Fault execute(); 915596Sgblack@eecs.umich.edu 925596Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 935596Sgblack@eecs.umich.edu Fault initiateAcc(); 945596Sgblack@eecs.umich.edu 955596Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 965596Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 975596Sgblack@eecs.umich.edu 985596Sgblack@eecs.umich.edu private: 995596Sgblack@eecs.umich.edu /** Initializes variables. */ 1005596Sgblack@eecs.umich.edu void initVars(); 1015596Sgblack@eecs.umich.edu 1025596Sgblack@eecs.umich.edu public: 1035596Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 1045596Sgblack@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 1055596Sgblack@eecs.umich.edu { 1065596Sgblack@eecs.umich.edu return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); 1075596Sgblack@eecs.umich.edu } 1085596Sgblack@eecs.umich.edu 1095596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1105596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1115596Sgblack@eecs.umich.edu */ 1125596Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 1135596Sgblack@eecs.umich.edu { 1145596Sgblack@eecs.umich.edu return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1155596Sgblack@eecs.umich.edu } 1165596Sgblack@eecs.umich.edu 1175596Sgblack@eecs.umich.edu /** Sets a misc. register. */ 1185596Sgblack@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 1195596Sgblack@eecs.umich.edu { 1205596Sgblack@eecs.umich.edu this->instResult.integer = val; 1215596Sgblack@eecs.umich.edu return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); 1225596Sgblack@eecs.umich.edu } 1235596Sgblack@eecs.umich.edu 1245596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1255596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1265596Sgblack@eecs.umich.edu */ 1275596Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 1285596Sgblack@eecs.umich.edu { 1295596Sgblack@eecs.umich.edu return this->cpu->setMiscReg(misc_reg, val, 1305596Sgblack@eecs.umich.edu this->threadNumber); 1315596Sgblack@eecs.umich.edu } 1325596Sgblack@eecs.umich.edu 1335596Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 1345596Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) 1355596Sgblack@eecs.umich.edu { 1365596Sgblack@eecs.umich.edu return this->cpu->readMiscRegNoEffect( 1375596Sgblack@eecs.umich.edu si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 1385596Sgblack@eecs.umich.edu this->threadNumber); 1395596Sgblack@eecs.umich.edu } 1405596Sgblack@eecs.umich.edu 1415596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1425596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1435596Sgblack@eecs.umich.edu */ 1445596Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 1455596Sgblack@eecs.umich.edu { 1465596Sgblack@eecs.umich.edu return this->cpu->readMiscReg( 1475596Sgblack@eecs.umich.edu si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 1485596Sgblack@eecs.umich.edu this->threadNumber); 1495596Sgblack@eecs.umich.edu } 1505596Sgblack@eecs.umich.edu 1515596Sgblack@eecs.umich.edu /** Sets a misc. register. */ 1525596Sgblack@eecs.umich.edu void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val) 1535596Sgblack@eecs.umich.edu { 1545596Sgblack@eecs.umich.edu this->instResult.integer = val; 1555596Sgblack@eecs.umich.edu return this->cpu->setMiscRegNoEffect( 1565596Sgblack@eecs.umich.edu si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 1575596Sgblack@eecs.umich.edu val, this->threadNumber); 1585596Sgblack@eecs.umich.edu } 1595596Sgblack@eecs.umich.edu 1605596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1615596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1625596Sgblack@eecs.umich.edu */ 1635596Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, 1645596Sgblack@eecs.umich.edu const MiscReg &val) 1655596Sgblack@eecs.umich.edu { 1665596Sgblack@eecs.umich.edu return this->cpu->setMiscReg( 1675596Sgblack@eecs.umich.edu si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, 1685596Sgblack@eecs.umich.edu val, this->threadNumber); 1695596Sgblack@eecs.umich.edu } 1705596Sgblack@eecs.umich.edu 1715596Sgblack@eecs.umich.edu#if FULL_SYSTEM 1725702Ssaidi@eecs.umich.edu /** Calls hardware return from error interrupt. */ 1735702Ssaidi@eecs.umich.edu Fault hwrei(); 1745596Sgblack@eecs.umich.edu /** Traps to handle specified fault. */ 1755596Sgblack@eecs.umich.edu void trap(Fault fault); 1765702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1772935Sksewell@umich.edu#else 1785596Sgblack@eecs.umich.edu /** Calls a syscall. */ 1795596Sgblack@eecs.umich.edu void syscall(int64_t callnum); 1802848Sksewell@umich.edu#endif 1812847Sksewell@umich.edu 1825596Sgblack@eecs.umich.edu public: 1835596Sgblack@eecs.umich.edu 1845596Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 1855596Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 1865596Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 1875596Sgblack@eecs.umich.edu // renaming. We find the architectural register index by indexing 1885596Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 1895596Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 1905596Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 1915596Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 1925596Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 1935596Sgblack@eecs.umich.edu // to do). 1945596Sgblack@eecs.umich.edu 1955596Sgblack@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 1965596Sgblack@eecs.umich.edu { 1975596Sgblack@eecs.umich.edu return this->cpu->readIntReg(this->_srcRegIdx[idx]); 1985596Sgblack@eecs.umich.edu } 1995596Sgblack@eecs.umich.edu 2005596Sgblack@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2015596Sgblack@eecs.umich.edu { 2025596Sgblack@eecs.umich.edu return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 2035596Sgblack@eecs.umich.edu } 2045596Sgblack@eecs.umich.edu 2055596Sgblack@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2065596Sgblack@eecs.umich.edu { 2075596Sgblack@eecs.umich.edu return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 2085596Sgblack@eecs.umich.edu } 2095596Sgblack@eecs.umich.edu 2105596Sgblack@eecs.umich.edu /** @todo: Make results into arrays so they can handle multiple dest 2115596Sgblack@eecs.umich.edu * registers. 2125596Sgblack@eecs.umich.edu */ 2135596Sgblack@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2145596Sgblack@eecs.umich.edu { 2155596Sgblack@eecs.umich.edu this->cpu->setIntReg(this->_destRegIdx[idx], val); 2165596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 2175596Sgblack@eecs.umich.edu } 2185596Sgblack@eecs.umich.edu 2195596Sgblack@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2205596Sgblack@eecs.umich.edu { 2215596Sgblack@eecs.umich.edu this->cpu->setFloatReg(this->_destRegIdx[idx], val); 2225596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 2235596Sgblack@eecs.umich.edu } 2245596Sgblack@eecs.umich.edu 2255596Sgblack@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2265596Sgblack@eecs.umich.edu FloatRegBits val) 2275596Sgblack@eecs.umich.edu { 2285596Sgblack@eecs.umich.edu this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 2295596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 2305596Sgblack@eecs.umich.edu } 2315596Sgblack@eecs.umich.edu 2325596Sgblack@eecs.umich.edu#if THE_ISA == MIPS_ISA 2335596Sgblack@eecs.umich.edu uint64_t readRegOtherThread(int misc_reg) 2345596Sgblack@eecs.umich.edu { 2355596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 2365596Sgblack@eecs.umich.edu return 0; 2375596Sgblack@eecs.umich.edu } 2385596Sgblack@eecs.umich.edu 2395596Sgblack@eecs.umich.edu void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 2405596Sgblack@eecs.umich.edu { 2415596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 2425596Sgblack@eecs.umich.edu } 2435596Sgblack@eecs.umich.edu#endif 2445596Sgblack@eecs.umich.edu 2455596Sgblack@eecs.umich.edu public: 2465596Sgblack@eecs.umich.edu /** Calculates EA part of a memory instruction. Currently unused, 2475596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 2485596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 2495596Sgblack@eecs.umich.edu */ 2505596Sgblack@eecs.umich.edu Fault calcEA() 2515596Sgblack@eecs.umich.edu { 2525596Sgblack@eecs.umich.edu return this->staticInst->eaCompInst()->execute(this, this->traceData); 2535596Sgblack@eecs.umich.edu } 2545596Sgblack@eecs.umich.edu 2555596Sgblack@eecs.umich.edu /** Does the memory access part of a memory instruction. Currently unused, 2565596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 2575596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 2585596Sgblack@eecs.umich.edu */ 2595596Sgblack@eecs.umich.edu Fault memAccess() 2605596Sgblack@eecs.umich.edu { 2615596Sgblack@eecs.umich.edu return this->staticInst->memAccInst()->execute(this, this->traceData); 2625596Sgblack@eecs.umich.edu } 2635596Sgblack@eecs.umich.edu}; 2645596Sgblack@eecs.umich.edu 2655596Sgblack@eecs.umich.edu#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 2665596Sgblack@eecs.umich.edu 267