dyn_inst.hh revision 13557
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 2010, 2016 ARM Limited 36145Snate@binkert.org * Copyright (c) 2013 Advanced Micro Devices, Inc. 46145Snate@binkert.org * All rights reserved 56145Snate@binkert.org * 66145Snate@binkert.org * The license below extends only to copyright in the software and shall 76145Snate@binkert.org * not be construed as granting a license to any other intellectual 86145Snate@binkert.org * property including but not limited to intellectual property relating 96145Snate@binkert.org * to a hardware implementation of the functionality of the software 106145Snate@binkert.org * licensed hereunder. You may use the software subject to the license 116145Snate@binkert.org * terms below provided that you ensure that this notice is replicated 126145Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 136145Snate@binkert.org * modified or unmodified, in source code or in binary form. 146145Snate@binkert.org * 156145Snate@binkert.org * Copyright (c) 2004-2006 The Regents of The University of Michigan 166145Snate@binkert.org * All rights reserved. 176145Snate@binkert.org * 186145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 196145Snate@binkert.org * modification, are permitted provided that the following conditions are 206145Snate@binkert.org * met: redistributions of source code must retain the above copyright 216145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 226145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 236145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 246145Snate@binkert.org * documentation and/or other materials provided with the distribution; 256145Snate@binkert.org * neither the name of the copyright holders nor the names of its 266145Snate@binkert.org * contributors may be used to endorse or promote products derived from 276145Snate@binkert.org * this software without specific prior written permission. 286145Snate@binkert.org * 298229Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307056Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 318615Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 328615Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 338615Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 348615Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357632SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 368232Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378232Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 388615Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399104Shestness@cs.utexas.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 408615Snilay@cs.wisc.edu * 418615Snilay@cs.wisc.edu * Authors: Kevin Lim 427039Snate@binkert.org */ 437039Snate@binkert.org 448229Snate@binkert.org#ifndef __CPU_O3_DYN_INST_HH__ 456154Snate@binkert.org#define __CPU_O3_DYN_INST_HH__ 466154Snate@binkert.org 477550SBrad.Beckmann@amd.com#include <array> 486876Ssteve.reinhardt@amd.com 497055Snate@binkert.org#include "arch/isa_traits.hh" 507055Snate@binkert.org#include "config/the_isa.hh" 516876Ssteve.reinhardt@amd.com#include "cpu/o3/cpu.hh" 526876Ssteve.reinhardt@amd.com#include "cpu/o3/isa_specific.hh" 536285Snate@binkert.org#include "cpu/base_dyn_inst.hh" 546876Ssteve.reinhardt@amd.com#include "cpu/inst_seq.hh" 556285Snate@binkert.org#include "cpu/reg_class.hh" 567039Snate@binkert.org 576876Ssteve.reinhardt@amd.comclass Packet; 586886SBrad.Beckmann@amd.com 596876Ssteve.reinhardt@amd.comtemplate <class Impl> 606876Ssteve.reinhardt@amd.comclass BaseO3DynInst : public BaseDynInst<Impl> 616876Ssteve.reinhardt@amd.com{ 626876Ssteve.reinhardt@amd.com public: 636876Ssteve.reinhardt@amd.com /** Typedef for the CPU. */ 647039Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 656876Ssteve.reinhardt@amd.com 666285Snate@binkert.org /** Binary machine instruction type. */ 676876Ssteve.reinhardt@amd.com typedef TheISA::MachInst MachInst; 686876Ssteve.reinhardt@amd.com /** Register types. */ 696876Ssteve.reinhardt@amd.com typedef TheISA::CCReg CCReg; 706876Ssteve.reinhardt@amd.com using VecRegContainer = TheISA::VecRegContainer; 716899SBrad.Beckmann@amd.com using VecElem = TheISA::VecElem; 726876Ssteve.reinhardt@amd.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 736876Ssteve.reinhardt@amd.com 746876Ssteve.reinhardt@amd.com enum { 756876Ssteve.reinhardt@amd.com MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 768171Stushar@csail.mit.edu MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 778171Stushar@csail.mit.edu }; 786145Snate@binkert.org 796145Snate@binkert.org public: 807039Snate@binkert.org /** BaseDynInst constructor given a binary instruction. */ 817039Snate@binkert.org BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr 826145Snate@binkert.org ¯oop, TheISA::PCState pc, TheISA::PCState predPC, 836145Snate@binkert.org InstSeqNum seq_num, O3CPU *cpu); 847039Snate@binkert.org 857039Snate@binkert.org /** BaseDynInst constructor given a static inst pointer. */ 867039Snate@binkert.org BaseO3DynInst(const StaticInstPtr &_staticInst, 879342SAndreas.Sandberg@arm.com const StaticInstPtr &_macroop); 889245Shestness@cs.wisc.edu 897039Snate@binkert.org ~BaseO3DynInst(); 909501Snilay@cs.wisc.edu 916145Snate@binkert.org /** Executes the instruction.*/ 927039Snate@binkert.org Fault execute(); 937039Snate@binkert.org 946285Snate@binkert.org /** Initiates the access. Only valid for memory operations. */ 957455Snate@binkert.org Fault initiateAcc(); 967455Snate@binkert.org 977455Snate@binkert.org /** Completes the access. Only valid for memory operations. */ 987455Snate@binkert.org Fault completeAcc(PacketPtr pkt); 997455Snate@binkert.org 1007455Snate@binkert.org private: 1017455Snate@binkert.org /** Initializes variables. */ 1027805Snilay@cs.wisc.edu void initVars(); 1037921SBrad.Beckmann@amd.com 1047805Snilay@cs.wisc.edu protected: 1058615Snilay@cs.wisc.edu /** Explicitation of dependent names. */ 1069467Smalek.musleh@gmail.com using BaseDynInst<Impl>::cpu; 1079467Smalek.musleh@gmail.com using BaseDynInst<Impl>::_srcRegIdx; 1086145Snate@binkert.org using BaseDynInst<Impl>::_destRegIdx; 1096145Snate@binkert.org 1107455Snate@binkert.org /** Values to be written to the destination misc. registers. */ 1117455Snate@binkert.org std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal; 1127455Snate@binkert.org 1137455Snate@binkert.org /** Indexes of the destination misc. registers. They are needed to defer 1147455Snate@binkert.org * the write accesses to the misc. registers until the commit stage, when 1157455Snate@binkert.org * the instruction is out of its speculative state. 1167455Snate@binkert.org */ 1177805Snilay@cs.wisc.edu std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 1187921SBrad.Beckmann@amd.com 1197805Snilay@cs.wisc.edu /** Number of destination misc. registers. */ 1208615Snilay@cs.wisc.edu uint8_t _numDestMiscRegs; 1219467Smalek.musleh@gmail.com 1229467Smalek.musleh@gmail.com 1236145Snate@binkert.org public: 1246285Snate@binkert.org#if TRACING_ON 1257039Snate@binkert.org /** Tick records used for the pipeline activity viewer. */ 1267039Snate@binkert.org Tick fetchTick; // instruction fetch is completed. 1276145Snate@binkert.org int32_t decodeTick; // instruction enters decode phase 1287039Snate@binkert.org int32_t renameTick; // instruction enters rename phase 1297039Snate@binkert.org int32_t dispatchTick; 1307039Snate@binkert.org int32_t issueTick; 1317039Snate@binkert.org int32_t completeTick; 1329465Snilay@cs.wisc.edu int32_t commitTick; 1337039Snate@binkert.org int32_t storeTick; 1346145Snate@binkert.org#endif 1356145Snate@binkert.org 1367039Snate@binkert.org /** Reads a misc. register, including any side-effects the read 1377039Snate@binkert.org * might have as defined by the architecture. 1387039Snate@binkert.org */ 1397039Snate@binkert.org RegVal 1407039Snate@binkert.org readMiscReg(int misc_reg) 1417039Snate@binkert.org { 1427039Snate@binkert.org return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1437039Snate@binkert.org } 1447039Snate@binkert.org 1457039Snate@binkert.org /** Sets a misc. register, including any side-effects the write 1467039Snate@binkert.org * might have as defined by the architecture. 1477039Snate@binkert.org */ 1486859Sdrh5@cs.wisc.edu void 1496859Sdrh5@cs.wisc.edu setMiscReg(int misc_reg, const RegVal &val) 1507039Snate@binkert.org { 1517039Snate@binkert.org /** Writes to misc. registers are recorded and deferred until the 1527039Snate@binkert.org * commit stage, when updateMiscRegs() is called. First, check if 1537039Snate@binkert.org * the misc reg has been written before and update its value to be 1547039Snate@binkert.org * committed instead of making a new entry. If not, make a new 1557039Snate@binkert.org * entry and record the write. 1569171Snilay@cs.wisc.edu */ 1577039Snate@binkert.org for (int idx = 0; idx < _numDestMiscRegs; idx++) { 1587039Snate@binkert.org if (_destMiscRegIdx[idx] == misc_reg) { 1596145Snate@binkert.org _destMiscRegVal[idx] = val; 1607455Snate@binkert.org return; 1617455Snate@binkert.org } 1626145Snate@binkert.org } 1637039Snate@binkert.org 1647455Snate@binkert.org assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 1657455Snate@binkert.org _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1667455Snate@binkert.org _destMiscRegVal[_numDestMiscRegs] = val; 1677455Snate@binkert.org _numDestMiscRegs++; 1687039Snate@binkert.org } 1697039Snate@binkert.org 1707039Snate@binkert.org /** Reads a misc. register, including any side-effects the read 1717039Snate@binkert.org * might have as defined by the architecture. 1726145Snate@binkert.org */ 1737039Snate@binkert.org RegVal 1746145Snate@binkert.org readMiscRegOperand(const StaticInst *si, int idx) 1757455Snate@binkert.org { 1767455Snate@binkert.org const RegId& reg = si->srcRegIdx(idx); 1776285Snate@binkert.org assert(reg.isMiscReg()); 1787039Snate@binkert.org return this->cpu->readMiscReg(reg.index(), this->threadNumber); 1797455Snate@binkert.org } 1807455Snate@binkert.org 1817455Snate@binkert.org /** Sets a misc. register, including any side-effects the write 1827455Snate@binkert.org * might have as defined by the architecture. 1837039Snate@binkert.org */ 1847039Snate@binkert.org void 1857039Snate@binkert.org setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val) 1867039Snate@binkert.org { 1877039Snate@binkert.org const RegId& reg = si->destRegIdx(idx); 1887039Snate@binkert.org assert(reg.isMiscReg()); 1897039Snate@binkert.org setMiscReg(reg.index(), val); 1907039Snate@binkert.org } 1917039Snate@binkert.org 1927039Snate@binkert.org /** Called at the commit stage to update the misc. registers. */ 1937039Snate@binkert.org void 1947039Snate@binkert.org updateMiscRegs() 1957039Snate@binkert.org { 1967039Snate@binkert.org // @todo: Pretty convoluted way to avoid squashing from happening when 1977039Snate@binkert.org // using the TC during an instruction's execution (specifically for 1987039Snate@binkert.org // instructions that have side-effects that use the TC). Fix this. 1996145Snate@binkert.org // See cpu/o3/dyn_inst_impl.hh. 2006145Snate@binkert.org bool no_squash_from_TC = this->thread->noSquashFromTC; 2016145Snate@binkert.org this->thread->noSquashFromTC = true; 2026145Snate@binkert.org 2038615Snilay@cs.wisc.edu for (int i = 0; i < _numDestMiscRegs; i++) 2048615Snilay@cs.wisc.edu this->cpu->setMiscReg( 2057039Snate@binkert.org _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 2068641Snate@binkert.org 2078641Snate@binkert.org this->thread->noSquashFromTC = no_squash_from_TC; 2086145Snate@binkert.org } 2097039Snate@binkert.org 2109342SAndreas.Sandberg@arm.com void forwardOldRegs() 2119342SAndreas.Sandberg@arm.com { 2129465Snilay@cs.wisc.edu 2137039Snate@binkert.org for (int idx = 0; idx < this->numDestRegs(); idx++) { 2146145Snate@binkert.org PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx); 2158615Snilay@cs.wisc.edu const RegId& original_dest_reg = 2167039Snate@binkert.org this->staticInst->destRegIdx(idx); 2179224Sandreas.hansson@arm.com switch (original_dest_reg.classValue()) { 2189224Sandreas.hansson@arm.com case IntRegClass: 2199224Sandreas.hansson@arm.com this->setIntRegOperand(this->staticInst.get(), idx, 2209224Sandreas.hansson@arm.com this->cpu->readIntReg(prev_phys_reg)); 2219224Sandreas.hansson@arm.com break; 2228615Snilay@cs.wisc.edu case FloatRegClass: 2238615Snilay@cs.wisc.edu this->setFloatRegOperandBits(this->staticInst.get(), idx, 2248615Snilay@cs.wisc.edu this->cpu->readFloatRegBits(prev_phys_reg)); 2258615Snilay@cs.wisc.edu break; 2268615Snilay@cs.wisc.edu case VecRegClass: 2278615Snilay@cs.wisc.edu this->setVecRegOperand(this->staticInst.get(), idx, 2288615Snilay@cs.wisc.edu this->cpu->readVecReg(prev_phys_reg)); 2298615Snilay@cs.wisc.edu break; 2308615Snilay@cs.wisc.edu case VecElemClass: 2318615Snilay@cs.wisc.edu this->setVecElemOperand(this->staticInst.get(), idx, 2328615Snilay@cs.wisc.edu this->cpu->readVecElem(prev_phys_reg)); 2338615Snilay@cs.wisc.edu break; 2348615Snilay@cs.wisc.edu case CCRegClass: 2358615Snilay@cs.wisc.edu this->setCCRegOperand(this->staticInst.get(), idx, 2368615Snilay@cs.wisc.edu this->cpu->readCCReg(prev_phys_reg)); 2378615Snilay@cs.wisc.edu break; 2387455Snate@binkert.org case MiscRegClass: 2399224Sandreas.hansson@arm.com // no need to forward misc reg values 2408615Snilay@cs.wisc.edu break; 2418615Snilay@cs.wisc.edu default: 2429465Snilay@cs.wisc.edu panic("Unknown register class: %d", 2438615Snilay@cs.wisc.edu (int)original_dest_reg.classValue()); 2448615Snilay@cs.wisc.edu } 2458615Snilay@cs.wisc.edu } 2468615Snilay@cs.wisc.edu } 2478615Snilay@cs.wisc.edu /** Calls hardware return from error interrupt. */ 2488615Snilay@cs.wisc.edu Fault hwrei(); 2498615Snilay@cs.wisc.edu /** Traps to handle specified fault. */ 2508615Snilay@cs.wisc.edu void trap(const Fault &fault); 2518615Snilay@cs.wisc.edu bool simPalCheck(int palFunc); 2528615Snilay@cs.wisc.edu 2538615Snilay@cs.wisc.edu /** Emulates a syscall. */ 2548615Snilay@cs.wisc.edu void syscall(int64_t callnum, Fault *fault); 2558615Snilay@cs.wisc.edu 2567039Snate@binkert.org public: 2577455Snate@binkert.org 2589224Sandreas.hansson@arm.com // The register accessor methods provide the index of the 2597039Snate@binkert.org // instruction's operand (e.g., 0 or 1), not the architectural 2608615Snilay@cs.wisc.edu // register index, to simplify the implementation of register 2618615Snilay@cs.wisc.edu // renaming. We find the architectural register index by indexing 2629465Snilay@cs.wisc.edu // into the instruction's own operand index table. Note that a 2638615Snilay@cs.wisc.edu // raw pointer to the StaticInst is provided instead of a 2648615Snilay@cs.wisc.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2658615Snilay@cs.wisc.edu // long as these methods don't copy the pointer into any long-term 2668615Snilay@cs.wisc.edu // storage (which is pretty hard to imagine they would have reason 2678615Snilay@cs.wisc.edu // to do). 2687039Snate@binkert.org 2696145Snate@binkert.org RegVal 2706145Snate@binkert.org readIntRegOperand(const StaticInst *si, int idx) 2717039Snate@binkert.org { 2728641Snate@binkert.org return this->cpu->readIntReg(this->_srcRegIdx[idx]); 2738641Snate@binkert.org } 2746145Snate@binkert.org 2758615Snilay@cs.wisc.edu RegVal 2766145Snate@binkert.org readFloatRegOperandBits(const StaticInst *si, int idx) 2776145Snate@binkert.org { 2787039Snate@binkert.org return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 2797455Snate@binkert.org } 2807455Snate@binkert.org 2817455Snate@binkert.org const VecRegContainer& 2827455Snate@binkert.org readVecRegOperand(const StaticInst *si, int idx) const 2837455Snate@binkert.org { 2847455Snate@binkert.org return this->cpu->readVecReg(this->_srcRegIdx[idx]); 2857455Snate@binkert.org } 2867455Snate@binkert.org 2877039Snate@binkert.org /** 2887039Snate@binkert.org * Read destination vector register operand for modification. 2897039Snate@binkert.org */ 2907039Snate@binkert.org VecRegContainer& 2916145Snate@binkert.org getWritableVecRegOperand(const StaticInst *si, int idx) 2928615Snilay@cs.wisc.edu { 2937039Snate@binkert.org return this->cpu->getWritableVecReg(this->_destRegIdx[idx]); 2948615Snilay@cs.wisc.edu } 2958615Snilay@cs.wisc.edu 2968615Snilay@cs.wisc.edu /** Vector Register Lane Interfaces. */ 2978615Snilay@cs.wisc.edu /** @{ */ 2988615Snilay@cs.wisc.edu /** Reads source vector 8bit operand. */ 2998615Snilay@cs.wisc.edu ConstVecLane8 3008615Snilay@cs.wisc.edu readVec8BitLaneOperand(const StaticInst *si, int idx) const 3017455Snate@binkert.org { 3027039Snate@binkert.org return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]); 3037455Snate@binkert.org } 3047039Snate@binkert.org 3056285Snate@binkert.org /** Reads source vector 16bit operand. */ 3067455Snate@binkert.org ConstVecLane16 3076145Snate@binkert.org readVec16BitLaneOperand(const StaticInst *si, int idx) const 3086145Snate@binkert.org { 3097560SBrad.Beckmann@amd.com return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]); 3107560SBrad.Beckmann@amd.com } 3117550SBrad.Beckmann@amd.com 3127560SBrad.Beckmann@amd.com /** Reads source vector 32bit operand. */ 3137560SBrad.Beckmann@amd.com ConstVecLane32 3147560SBrad.Beckmann@amd.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 3157560SBrad.Beckmann@amd.com { 3167560SBrad.Beckmann@amd.com return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]); 3177560SBrad.Beckmann@amd.com } 3188615Snilay@cs.wisc.edu 3197550SBrad.Beckmann@amd.com /** Reads source vector 64bit operand. */ 3207550SBrad.Beckmann@amd.com ConstVecLane64 3217550SBrad.Beckmann@amd.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 3227550SBrad.Beckmann@amd.com { 3237550SBrad.Beckmann@amd.com return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]); 3248615Snilay@cs.wisc.edu } 3257560SBrad.Beckmann@amd.com 3267550SBrad.Beckmann@amd.com /** Write a lane of the destination vector operand. */ 3277550SBrad.Beckmann@amd.com template <typename LD> 3287550SBrad.Beckmann@amd.com void 3297550SBrad.Beckmann@amd.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 3307550SBrad.Beckmann@amd.com { 3318615Snilay@cs.wisc.edu return cpu->template setVecLane(_destRegIdx[idx], val); 3327550SBrad.Beckmann@amd.com } 3337560SBrad.Beckmann@amd.com virtual void 3347560SBrad.Beckmann@amd.com setVecLaneOperand(const StaticInst *si, int idx, 3357560SBrad.Beckmann@amd.com const LaneData<LaneSize::Byte>& val) 3367550SBrad.Beckmann@amd.com { 3378615Snilay@cs.wisc.edu return setVecLaneOperandT(si, idx, val); 3387550SBrad.Beckmann@amd.com } 3397550SBrad.Beckmann@amd.com virtual void 3407550SBrad.Beckmann@amd.com setVecLaneOperand(const StaticInst *si, int idx, 3417550SBrad.Beckmann@amd.com const LaneData<LaneSize::TwoByte>& val) 3427550SBrad.Beckmann@amd.com { 3438615Snilay@cs.wisc.edu return setVecLaneOperandT(si, idx, val); 3448615Snilay@cs.wisc.edu } 3457550SBrad.Beckmann@amd.com virtual void 3467550SBrad.Beckmann@amd.com setVecLaneOperand(const StaticInst *si, int idx, 3477550SBrad.Beckmann@amd.com const LaneData<LaneSize::FourByte>& val) 3487550SBrad.Beckmann@amd.com { 3497550SBrad.Beckmann@amd.com return setVecLaneOperandT(si, idx, val); 3507560SBrad.Beckmann@amd.com } 3517550SBrad.Beckmann@amd.com virtual void 3527550SBrad.Beckmann@amd.com setVecLaneOperand(const StaticInst *si, int idx, 3537550SBrad.Beckmann@amd.com const LaneData<LaneSize::EightByte>& val) 3547039Snate@binkert.org { 3557039Snate@binkert.org return setVecLaneOperandT(si, idx, val); 3567546SBrad.Beckmann@amd.com } 3577546SBrad.Beckmann@amd.com /** @} */ 3587546SBrad.Beckmann@amd.com 3597546SBrad.Beckmann@amd.com VecElem readVecElemOperand(const StaticInst *si, int idx) const 3607546SBrad.Beckmann@amd.com { 3619507Snilay@cs.wisc.edu return this->cpu->readVecElem(this->_srcRegIdx[idx]); 3627546SBrad.Beckmann@amd.com } 3637546SBrad.Beckmann@amd.com 3649507Snilay@cs.wisc.edu CCReg readCCRegOperand(const StaticInst *si, int idx) 3657565SBrad.Beckmann@amd.com { 3667565SBrad.Beckmann@amd.com return this->cpu->readCCReg(this->_srcRegIdx[idx]); 3677565SBrad.Beckmann@amd.com } 3687565SBrad.Beckmann@amd.com 3699507Snilay@cs.wisc.edu /** @todo: Make results into arrays so they can handle multiple dest 3707565SBrad.Beckmann@amd.com * registers. 3719507Snilay@cs.wisc.edu */ 3729507Snilay@cs.wisc.edu void 3739507Snilay@cs.wisc.edu setIntRegOperand(const StaticInst *si, int idx, RegVal val) 3747565SBrad.Beckmann@amd.com { 3757039Snate@binkert.org this->cpu->setIntReg(this->_destRegIdx[idx], val); 3767455Snate@binkert.org BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 3776145Snate@binkert.org } 3787455Snate@binkert.org 3797455Snate@binkert.org void 3807455Snate@binkert.org setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) 3816145Snate@binkert.org { 3827455Snate@binkert.org this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 3837455Snate@binkert.org BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 3846846Spdudnik@cs.wisc.edu } 3858615Snilay@cs.wisc.edu 3868615Snilay@cs.wisc.edu void 3878615Snilay@cs.wisc.edu setVecRegOperand(const StaticInst *si, int idx, 3888615Snilay@cs.wisc.edu const VecRegContainer& val) 3898615Snilay@cs.wisc.edu { 3908615Snilay@cs.wisc.edu this->cpu->setVecReg(this->_destRegIdx[idx], val); 3918615Snilay@cs.wisc.edu BaseDynInst<Impl>::setVecRegOperand(si, idx, val); 3928615Snilay@cs.wisc.edu } 3938615Snilay@cs.wisc.edu 3948184Ssomayeh@cs.wisc.edu void setVecElemOperand(const StaticInst *si, int idx, 3956145Snate@binkert.org const VecElem val) 3967550SBrad.Beckmann@amd.com { 3977550SBrad.Beckmann@amd.com int reg_idx = idx; 3987550SBrad.Beckmann@amd.com this->cpu->setVecElem(this->_destRegIdx[reg_idx], val); 3997550SBrad.Beckmann@amd.com BaseDynInst<Impl>::setVecElemOperand(si, idx, val); 4008171Stushar@csail.mit.edu } 4018171Stushar@csail.mit.edu 4028171Stushar@csail.mit.edu void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 4038171Stushar@csail.mit.edu { 4048171Stushar@csail.mit.edu this->cpu->setCCReg(this->_destRegIdx[idx], val); 4057550SBrad.Beckmann@amd.com BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 4068615Snilay@cs.wisc.edu } 4077039Snate@binkert.org 4088615Snilay@cs.wisc.edu#if THE_ISA == MIPS_ISA 4097039Snate@binkert.org RegVal 4107039Snate@binkert.org readRegOtherThread(const RegId& misc_reg, ThreadID tid) 4116863Sdrh5@cs.wisc.edu { 4129507Snilay@cs.wisc.edu panic("MIPS MT not defined for O3 CPU.\n"); 4137565SBrad.Beckmann@amd.com return 0; 4146145Snate@binkert.org } 4156145Snate@binkert.org 4167039Snate@binkert.org void 4177039Snate@binkert.org setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) 4187039Snate@binkert.org { 4197546SBrad.Beckmann@amd.com panic("MIPS MT not defined for O3 CPU.\n"); 4207546SBrad.Beckmann@amd.com } 4217546SBrad.Beckmann@amd.com#endif 4227546SBrad.Beckmann@amd.com}; 4237546SBrad.Beckmann@amd.com 4247546SBrad.Beckmann@amd.com#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 4257546SBrad.Beckmann@amd.com 4267546SBrad.Beckmann@amd.com