dyn_inst.hh revision 12420
12847Sksewell@umich.edu/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010, 2016 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 155596Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162847Sksewell@umich.edu * All rights reserved. 172847Sksewell@umich.edu * 182847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192847Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242847Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272847Sksewell@umich.edu * this software without specific prior written permission. 282847Sksewell@umich.edu * 292847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402847Sksewell@umich.edu * 415596Sgblack@eecs.umich.edu * Authors: Kevin Lim 422847Sksewell@umich.edu */ 432847Sksewell@umich.edu 442847Sksewell@umich.edu#ifndef __CPU_O3_DYN_INST_HH__ 452847Sksewell@umich.edu#define __CPU_O3_DYN_INST_HH__ 462847Sksewell@umich.edu 4710835Sandreas.hansson@arm.com#include <array> 4810835Sandreas.hansson@arm.com 495596Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 535596Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 545596Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 559913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 562847Sksewell@umich.edu 575596Sgblack@eecs.umich.educlass Packet; 585596Sgblack@eecs.umich.edu 595596Sgblack@eecs.umich.edutemplate <class Impl> 605596Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 615596Sgblack@eecs.umich.edu{ 625596Sgblack@eecs.umich.edu public: 635596Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 645596Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 655596Sgblack@eecs.umich.edu 665596Sgblack@eecs.umich.edu /** Binary machine instruction type. */ 675596Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 685596Sgblack@eecs.umich.edu /** Extended machine instruction type. */ 695596Sgblack@eecs.umich.edu typedef TheISA::ExtMachInst ExtMachInst; 7012104Snathanael.premillieu@arm.com /** Register types. */ 715596Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 725596Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 735596Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 749920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 7512109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 7612109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 7712109SRekai.GonzalezAlberquilla@arm.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 7810319SAndreas.Sandberg@ARM.com 7912104Snathanael.premillieu@arm.com /** Misc register type. */ 805596Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 815596Sgblack@eecs.umich.edu 825596Sgblack@eecs.umich.edu enum { 835596Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 848902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 855596Sgblack@eecs.umich.edu }; 865596Sgblack@eecs.umich.edu 875596Sgblack@eecs.umich.edu public: 885596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 8912109SRekai.GonzalezAlberquilla@arm.com BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr 9012109SRekai.GonzalezAlberquilla@arm.com ¯oop, TheISA::PCState pc, TheISA::PCState predPC, 9112109SRekai.GonzalezAlberquilla@arm.com InstSeqNum seq_num, O3CPU *cpu); 925596Sgblack@eecs.umich.edu 935596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 9410417Sandreas.hansson@arm.com BaseO3DynInst(const StaticInstPtr &_staticInst, 9510417Sandreas.hansson@arm.com const StaticInstPtr &_macroop); 965596Sgblack@eecs.umich.edu 979252Sdjordje.kovacevic@arm.com ~BaseO3DynInst(); 989252Sdjordje.kovacevic@arm.com 995596Sgblack@eecs.umich.edu /** Executes the instruction.*/ 1005596Sgblack@eecs.umich.edu Fault execute(); 1015596Sgblack@eecs.umich.edu 1025596Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 1035596Sgblack@eecs.umich.edu Fault initiateAcc(); 1045596Sgblack@eecs.umich.edu 1055596Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 1065596Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 1075596Sgblack@eecs.umich.edu 1085596Sgblack@eecs.umich.edu private: 1095596Sgblack@eecs.umich.edu /** Initializes variables. */ 1105596Sgblack@eecs.umich.edu void initVars(); 1115596Sgblack@eecs.umich.edu 1127783SGiacomo.Gabrielli@arm.com protected: 11312109SRekai.GonzalezAlberquilla@arm.com /** Explicitation of dependent names. */ 11412109SRekai.GonzalezAlberquilla@arm.com using BaseDynInst<Impl>::cpu; 11512109SRekai.GonzalezAlberquilla@arm.com using BaseDynInst<Impl>::_srcRegIdx; 11612109SRekai.GonzalezAlberquilla@arm.com using BaseDynInst<Impl>::_destRegIdx; 11712109SRekai.GonzalezAlberquilla@arm.com 1189046SAli.Saidi@ARM.com /** Values to be written to the destination misc. registers. */ 11910835Sandreas.hansson@arm.com std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 1209046SAli.Saidi@ARM.com 1217783SGiacomo.Gabrielli@arm.com /** Indexes of the destination misc. registers. They are needed to defer 1227783SGiacomo.Gabrielli@arm.com * the write accesses to the misc. registers until the commit stage, when 1237783SGiacomo.Gabrielli@arm.com * the instruction is out of its speculative state. 1247783SGiacomo.Gabrielli@arm.com */ 12510835Sandreas.hansson@arm.com std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 1269046SAli.Saidi@ARM.com 1277783SGiacomo.Gabrielli@arm.com /** Number of destination misc. registers. */ 1289046SAli.Saidi@ARM.com uint8_t _numDestMiscRegs; 1299046SAli.Saidi@ARM.com 1307783SGiacomo.Gabrielli@arm.com 1315596Sgblack@eecs.umich.edu public: 1328471SGiacomo.Gabrielli@arm.com#if TRACING_ON 1338471SGiacomo.Gabrielli@arm.com /** Tick records used for the pipeline activity viewer. */ 13412106SRekai.GonzalezAlberquilla@arm.com Tick fetchTick; // instruction fetch is completed. 1359252Sdjordje.kovacevic@arm.com int32_t decodeTick; // instruction enters decode phase 1369252Sdjordje.kovacevic@arm.com int32_t renameTick; // instruction enters rename phase 1379252Sdjordje.kovacevic@arm.com int32_t dispatchTick; 1389252Sdjordje.kovacevic@arm.com int32_t issueTick; 1399252Sdjordje.kovacevic@arm.com int32_t completeTick; 1409252Sdjordje.kovacevic@arm.com int32_t commitTick; 1419527SMatt.Horsnell@arm.com int32_t storeTick; 1428471SGiacomo.Gabrielli@arm.com#endif 1438471SGiacomo.Gabrielli@arm.com 1445596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1455596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1465596Sgblack@eecs.umich.edu */ 1475596Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 1485596Sgblack@eecs.umich.edu { 1495596Sgblack@eecs.umich.edu return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1505596Sgblack@eecs.umich.edu } 1515596Sgblack@eecs.umich.edu 1525596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1535596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1545596Sgblack@eecs.umich.edu */ 1555596Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 1565596Sgblack@eecs.umich.edu { 1577783SGiacomo.Gabrielli@arm.com /** Writes to misc. registers are recorded and deferred until the 1589532Sgeoffrey.blake@arm.com * commit stage, when updateMiscRegs() is called. First, check if 1599532Sgeoffrey.blake@arm.com * the misc reg has been written before and update its value to be 1609532Sgeoffrey.blake@arm.com * committed instead of making a new entry. If not, make a new 1619532Sgeoffrey.blake@arm.com * entry and record the write. 1627783SGiacomo.Gabrielli@arm.com */ 1639532Sgeoffrey.blake@arm.com for (int idx = 0; idx < _numDestMiscRegs; idx++) { 1649532Sgeoffrey.blake@arm.com if (_destMiscRegIdx[idx] == misc_reg) { 1659532Sgeoffrey.blake@arm.com _destMiscRegVal[idx] = val; 1669532Sgeoffrey.blake@arm.com return; 1679532Sgeoffrey.blake@arm.com } 1689532Sgeoffrey.blake@arm.com } 1699532Sgeoffrey.blake@arm.com 1709046SAli.Saidi@ARM.com assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 1717783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1727783SGiacomo.Gabrielli@arm.com _destMiscRegVal[_numDestMiscRegs] = val; 1737783SGiacomo.Gabrielli@arm.com _numDestMiscRegs++; 1745596Sgblack@eecs.umich.edu } 1755596Sgblack@eecs.umich.edu 1765596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1775596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1785596Sgblack@eecs.umich.edu */ 1795596Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 1805596Sgblack@eecs.umich.edu { 18112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 18212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 18312106SRekai.GonzalezAlberquilla@arm.com return this->cpu->readMiscReg(reg.index(), this->threadNumber); 1845596Sgblack@eecs.umich.edu } 1855596Sgblack@eecs.umich.edu 1865596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1875596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1885596Sgblack@eecs.umich.edu */ 1895596Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, 1905596Sgblack@eecs.umich.edu const MiscReg &val) 1915596Sgblack@eecs.umich.edu { 19212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 19312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 19412106SRekai.GonzalezAlberquilla@arm.com setMiscReg(reg.index(), val); 1957783SGiacomo.Gabrielli@arm.com } 1967783SGiacomo.Gabrielli@arm.com 1977783SGiacomo.Gabrielli@arm.com /** Called at the commit stage to update the misc. registers. */ 1987783SGiacomo.Gabrielli@arm.com void updateMiscRegs() 1997783SGiacomo.Gabrielli@arm.com { 2007783SGiacomo.Gabrielli@arm.com // @todo: Pretty convoluted way to avoid squashing from happening when 2017783SGiacomo.Gabrielli@arm.com // using the TC during an instruction's execution (specifically for 2027783SGiacomo.Gabrielli@arm.com // instructions that have side-effects that use the TC). Fix this. 2037783SGiacomo.Gabrielli@arm.com // See cpu/o3/dyn_inst_impl.hh. 2049382SAli.Saidi@ARM.com bool no_squash_from_TC = this->thread->noSquashFromTC; 2059382SAli.Saidi@ARM.com this->thread->noSquashFromTC = true; 2067783SGiacomo.Gabrielli@arm.com 2077783SGiacomo.Gabrielli@arm.com for (int i = 0; i < _numDestMiscRegs; i++) 2087783SGiacomo.Gabrielli@arm.com this->cpu->setMiscReg( 2097783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 2107783SGiacomo.Gabrielli@arm.com 2119382SAli.Saidi@ARM.com this->thread->noSquashFromTC = no_squash_from_TC; 2125596Sgblack@eecs.umich.edu } 2135596Sgblack@eecs.umich.edu 2147848SAli.Saidi@ARM.com void forwardOldRegs() 2157848SAli.Saidi@ARM.com { 21610935Snilay@cs.wisc.edu 2177848SAli.Saidi@ARM.com for (int idx = 0; idx < this->numDestRegs(); idx++) { 21812105Snathanael.premillieu@arm.com PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx); 21912106SRekai.GonzalezAlberquilla@arm.com const RegId& original_dest_reg = 2209913Ssteve.reinhardt@amd.com this->staticInst->destRegIdx(idx); 22112106SRekai.GonzalezAlberquilla@arm.com switch (original_dest_reg.classValue()) { 2229913Ssteve.reinhardt@amd.com case IntRegClass: 2239913Ssteve.reinhardt@amd.com this->setIntRegOperand(this->staticInst.get(), idx, 22412109SRekai.GonzalezAlberquilla@arm.com this->cpu->readIntReg(prev_phys_reg)); 2259913Ssteve.reinhardt@amd.com break; 2269913Ssteve.reinhardt@amd.com case FloatRegClass: 2279913Ssteve.reinhardt@amd.com this->setFloatRegOperandBits(this->staticInst.get(), idx, 22812109SRekai.GonzalezAlberquilla@arm.com this->cpu->readFloatRegBits(prev_phys_reg)); 22912109SRekai.GonzalezAlberquilla@arm.com break; 23012109SRekai.GonzalezAlberquilla@arm.com case VecRegClass: 23112109SRekai.GonzalezAlberquilla@arm.com this->setVecRegOperand(this->staticInst.get(), idx, 23212109SRekai.GonzalezAlberquilla@arm.com this->cpu->readVecReg(prev_phys_reg)); 23312109SRekai.GonzalezAlberquilla@arm.com break; 23412109SRekai.GonzalezAlberquilla@arm.com case VecElemClass: 23512109SRekai.GonzalezAlberquilla@arm.com this->setVecElemOperand(this->staticInst.get(), idx, 23612109SRekai.GonzalezAlberquilla@arm.com this->cpu->readVecElem(prev_phys_reg)); 2379913Ssteve.reinhardt@amd.com break; 2389920Syasuko.eckert@amd.com case CCRegClass: 2399920Syasuko.eckert@amd.com this->setCCRegOperand(this->staticInst.get(), idx, 24012109SRekai.GonzalezAlberquilla@arm.com this->cpu->readCCReg(prev_phys_reg)); 2419920Syasuko.eckert@amd.com break; 2429913Ssteve.reinhardt@amd.com case MiscRegClass: 2439913Ssteve.reinhardt@amd.com // no need to forward misc reg values 2449913Ssteve.reinhardt@amd.com break; 24512109SRekai.GonzalezAlberquilla@arm.com default: 24612109SRekai.GonzalezAlberquilla@arm.com panic("Unknown register class: %d", 24712109SRekai.GonzalezAlberquilla@arm.com (int)original_dest_reg.classValue()); 2489913Ssteve.reinhardt@amd.com } 2497848SAli.Saidi@ARM.com } 2507848SAli.Saidi@ARM.com } 2515702Ssaidi@eecs.umich.edu /** Calls hardware return from error interrupt. */ 2525702Ssaidi@eecs.umich.edu Fault hwrei(); 2535596Sgblack@eecs.umich.edu /** Traps to handle specified fault. */ 25410379Sandreas.hansson@arm.com void trap(const Fault &fault); 2555702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2568557Sgblack@eecs.umich.edu 2578557Sgblack@eecs.umich.edu /** Emulates a syscall. */ 25811877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault); 2592847Sksewell@umich.edu 2605596Sgblack@eecs.umich.edu public: 2615596Sgblack@eecs.umich.edu 2625596Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 2635596Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 2645596Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 2655596Sgblack@eecs.umich.edu // renaming. We find the architectural register index by indexing 2665596Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 2675596Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 2685596Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2695596Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 2705596Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 2715596Sgblack@eecs.umich.edu // to do). 2725596Sgblack@eecs.umich.edu 27310319SAndreas.Sandberg@ARM.com IntReg readIntRegOperand(const StaticInst *si, int idx) 2745596Sgblack@eecs.umich.edu { 2755596Sgblack@eecs.umich.edu return this->cpu->readIntReg(this->_srcRegIdx[idx]); 2765596Sgblack@eecs.umich.edu } 2775596Sgblack@eecs.umich.edu 2785596Sgblack@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2795596Sgblack@eecs.umich.edu { 2805596Sgblack@eecs.umich.edu return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 2815596Sgblack@eecs.umich.edu } 2825596Sgblack@eecs.umich.edu 2835596Sgblack@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2845596Sgblack@eecs.umich.edu { 2855596Sgblack@eecs.umich.edu return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 2865596Sgblack@eecs.umich.edu } 2875596Sgblack@eecs.umich.edu 28812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 28912109SRekai.GonzalezAlberquilla@arm.com readVecRegOperand(const StaticInst *si, int idx) const 29012109SRekai.GonzalezAlberquilla@arm.com { 29112109SRekai.GonzalezAlberquilla@arm.com return this->cpu->readVecReg(this->_srcRegIdx[idx]); 29212109SRekai.GonzalezAlberquilla@arm.com } 29312109SRekai.GonzalezAlberquilla@arm.com 29412109SRekai.GonzalezAlberquilla@arm.com /** 29512109SRekai.GonzalezAlberquilla@arm.com * Read destination vector register operand for modification. 29612109SRekai.GonzalezAlberquilla@arm.com */ 29712109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 29812109SRekai.GonzalezAlberquilla@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) 29912109SRekai.GonzalezAlberquilla@arm.com { 30012109SRekai.GonzalezAlberquilla@arm.com return this->cpu->getWritableVecReg(this->_destRegIdx[idx]); 30112109SRekai.GonzalezAlberquilla@arm.com } 30212109SRekai.GonzalezAlberquilla@arm.com 30312109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 30412109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 30512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 30612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 30712109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 30812109SRekai.GonzalezAlberquilla@arm.com { 30912109SRekai.GonzalezAlberquilla@arm.com return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]); 31012109SRekai.GonzalezAlberquilla@arm.com } 31112109SRekai.GonzalezAlberquilla@arm.com 31212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 31312109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 31412109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 31512109SRekai.GonzalezAlberquilla@arm.com { 31612109SRekai.GonzalezAlberquilla@arm.com return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]); 31712109SRekai.GonzalezAlberquilla@arm.com } 31812109SRekai.GonzalezAlberquilla@arm.com 31912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 32012109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 32112109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 32212109SRekai.GonzalezAlberquilla@arm.com { 32312109SRekai.GonzalezAlberquilla@arm.com return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]); 32412109SRekai.GonzalezAlberquilla@arm.com } 32512109SRekai.GonzalezAlberquilla@arm.com 32612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 32712109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 32812109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 32912109SRekai.GonzalezAlberquilla@arm.com { 33012109SRekai.GonzalezAlberquilla@arm.com return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]); 33112109SRekai.GonzalezAlberquilla@arm.com } 33212109SRekai.GonzalezAlberquilla@arm.com 33312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 33412109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 33512109SRekai.GonzalezAlberquilla@arm.com void 33612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 33712109SRekai.GonzalezAlberquilla@arm.com { 33812109SRekai.GonzalezAlberquilla@arm.com return cpu->template setVecLane(_destRegIdx[idx], val); 33912109SRekai.GonzalezAlberquilla@arm.com } 34012109SRekai.GonzalezAlberquilla@arm.com virtual void 34112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 34212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 34312109SRekai.GonzalezAlberquilla@arm.com { 34412109SRekai.GonzalezAlberquilla@arm.com return setVecLaneOperandT(si, idx, val); 34512109SRekai.GonzalezAlberquilla@arm.com } 34612109SRekai.GonzalezAlberquilla@arm.com virtual void 34712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 34812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 34912109SRekai.GonzalezAlberquilla@arm.com { 35012109SRekai.GonzalezAlberquilla@arm.com return setVecLaneOperandT(si, idx, val); 35112109SRekai.GonzalezAlberquilla@arm.com } 35212109SRekai.GonzalezAlberquilla@arm.com virtual void 35312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 35412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 35512109SRekai.GonzalezAlberquilla@arm.com { 35612109SRekai.GonzalezAlberquilla@arm.com return setVecLaneOperandT(si, idx, val); 35712109SRekai.GonzalezAlberquilla@arm.com } 35812109SRekai.GonzalezAlberquilla@arm.com virtual void 35912109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 36012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 36112109SRekai.GonzalezAlberquilla@arm.com { 36212109SRekai.GonzalezAlberquilla@arm.com return setVecLaneOperandT(si, idx, val); 36312109SRekai.GonzalezAlberquilla@arm.com } 36412109SRekai.GonzalezAlberquilla@arm.com /** @} */ 36512109SRekai.GonzalezAlberquilla@arm.com 36612109SRekai.GonzalezAlberquilla@arm.com VecElem readVecElemOperand(const StaticInst *si, int idx) const 36712109SRekai.GonzalezAlberquilla@arm.com { 36812109SRekai.GonzalezAlberquilla@arm.com return this->cpu->readVecElem(this->_srcRegIdx[idx]); 36912109SRekai.GonzalezAlberquilla@arm.com } 37012109SRekai.GonzalezAlberquilla@arm.com 37110319SAndreas.Sandberg@ARM.com CCReg readCCRegOperand(const StaticInst *si, int idx) 3729920Syasuko.eckert@amd.com { 3739920Syasuko.eckert@amd.com return this->cpu->readCCReg(this->_srcRegIdx[idx]); 3749920Syasuko.eckert@amd.com } 3759920Syasuko.eckert@amd.com 3765596Sgblack@eecs.umich.edu /** @todo: Make results into arrays so they can handle multiple dest 3775596Sgblack@eecs.umich.edu * registers. 3785596Sgblack@eecs.umich.edu */ 37910319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 3805596Sgblack@eecs.umich.edu { 3815596Sgblack@eecs.umich.edu this->cpu->setIntReg(this->_destRegIdx[idx], val); 3825596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 3835596Sgblack@eecs.umich.edu } 3845596Sgblack@eecs.umich.edu 3855596Sgblack@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 3865596Sgblack@eecs.umich.edu { 3875596Sgblack@eecs.umich.edu this->cpu->setFloatReg(this->_destRegIdx[idx], val); 3885596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 3895596Sgblack@eecs.umich.edu } 3905596Sgblack@eecs.umich.edu 3915596Sgblack@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 3925596Sgblack@eecs.umich.edu FloatRegBits val) 3935596Sgblack@eecs.umich.edu { 3945596Sgblack@eecs.umich.edu this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 3955596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 3965596Sgblack@eecs.umich.edu } 3975596Sgblack@eecs.umich.edu 39812109SRekai.GonzalezAlberquilla@arm.com void 39912109SRekai.GonzalezAlberquilla@arm.com setVecRegOperand(const StaticInst *si, int idx, 40012109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) 40112109SRekai.GonzalezAlberquilla@arm.com { 40212109SRekai.GonzalezAlberquilla@arm.com this->cpu->setVecReg(this->_destRegIdx[idx], val); 40312109SRekai.GonzalezAlberquilla@arm.com BaseDynInst<Impl>::setVecRegOperand(si, idx, val); 40412109SRekai.GonzalezAlberquilla@arm.com } 40512109SRekai.GonzalezAlberquilla@arm.com 40612109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, 40712109SRekai.GonzalezAlberquilla@arm.com const VecElem val) 40812109SRekai.GonzalezAlberquilla@arm.com { 40912109SRekai.GonzalezAlberquilla@arm.com int reg_idx = idx; 41012109SRekai.GonzalezAlberquilla@arm.com this->cpu->setVecElem(this->_destRegIdx[reg_idx], val); 41112109SRekai.GonzalezAlberquilla@arm.com BaseDynInst<Impl>::setVecElemOperand(si, idx, val); 41212109SRekai.GonzalezAlberquilla@arm.com } 41312109SRekai.GonzalezAlberquilla@arm.com 41410319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 4159920Syasuko.eckert@amd.com { 4169920Syasuko.eckert@amd.com this->cpu->setCCReg(this->_destRegIdx[idx], val); 4179920Syasuko.eckert@amd.com BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 4189920Syasuko.eckert@amd.com } 4199920Syasuko.eckert@amd.com 4205596Sgblack@eecs.umich.edu#if THE_ISA == MIPS_ISA 42112106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) 4225596Sgblack@eecs.umich.edu { 4235596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 4245596Sgblack@eecs.umich.edu return 0; 4255596Sgblack@eecs.umich.edu } 4265596Sgblack@eecs.umich.edu 42712106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& misc_reg, MiscReg val, ThreadID tid) 4285596Sgblack@eecs.umich.edu { 4295596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 4305596Sgblack@eecs.umich.edu } 4315596Sgblack@eecs.umich.edu#endif 4325596Sgblack@eecs.umich.edu}; 4335596Sgblack@eecs.umich.edu 4345596Sgblack@eecs.umich.edu#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 4355596Sgblack@eecs.umich.edu 436