dyn_inst.hh revision 12105
12847Sksewell@umich.edu/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 155596Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162847Sksewell@umich.edu * All rights reserved. 172847Sksewell@umich.edu * 182847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192847Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242847Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272847Sksewell@umich.edu * this software without specific prior written permission. 282847Sksewell@umich.edu * 292847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402847Sksewell@umich.edu * 415596Sgblack@eecs.umich.edu * Authors: Kevin Lim 422847Sksewell@umich.edu */ 432847Sksewell@umich.edu 442847Sksewell@umich.edu#ifndef __CPU_O3_DYN_INST_HH__ 452847Sksewell@umich.edu#define __CPU_O3_DYN_INST_HH__ 462847Sksewell@umich.edu 4710835Sandreas.hansson@arm.com#include <array> 4810835Sandreas.hansson@arm.com 495596Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 535596Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 545596Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 559913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 562847Sksewell@umich.edu 575596Sgblack@eecs.umich.educlass Packet; 585596Sgblack@eecs.umich.edu 595596Sgblack@eecs.umich.edutemplate <class Impl> 605596Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 615596Sgblack@eecs.umich.edu{ 625596Sgblack@eecs.umich.edu public: 635596Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 645596Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 655596Sgblack@eecs.umich.edu 665596Sgblack@eecs.umich.edu /** Binary machine instruction type. */ 675596Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 685596Sgblack@eecs.umich.edu /** Extended machine instruction type. */ 695596Sgblack@eecs.umich.edu typedef TheISA::ExtMachInst ExtMachInst; 7012104Snathanael.premillieu@arm.com /** Register types. */ 715596Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 725596Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 735596Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 749920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 7510319SAndreas.Sandberg@ARM.com 7612104Snathanael.premillieu@arm.com /** Misc register type. */ 775596Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 785596Sgblack@eecs.umich.edu 795596Sgblack@eecs.umich.edu enum { 805596Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 818902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 825596Sgblack@eecs.umich.edu }; 835596Sgblack@eecs.umich.edu 845596Sgblack@eecs.umich.edu public: 855596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 8610417Sandreas.hansson@arm.com BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 877720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 887720Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 895596Sgblack@eecs.umich.edu 905596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 9110417Sandreas.hansson@arm.com BaseO3DynInst(const StaticInstPtr &_staticInst, 9210417Sandreas.hansson@arm.com const StaticInstPtr &_macroop); 935596Sgblack@eecs.umich.edu 949252Sdjordje.kovacevic@arm.com ~BaseO3DynInst(); 959252Sdjordje.kovacevic@arm.com 965596Sgblack@eecs.umich.edu /** Executes the instruction.*/ 975596Sgblack@eecs.umich.edu Fault execute(); 985596Sgblack@eecs.umich.edu 995596Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 1005596Sgblack@eecs.umich.edu Fault initiateAcc(); 1015596Sgblack@eecs.umich.edu 1025596Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 1035596Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 1045596Sgblack@eecs.umich.edu 1055596Sgblack@eecs.umich.edu private: 1065596Sgblack@eecs.umich.edu /** Initializes variables. */ 1075596Sgblack@eecs.umich.edu void initVars(); 1085596Sgblack@eecs.umich.edu 1097783SGiacomo.Gabrielli@arm.com protected: 1109046SAli.Saidi@ARM.com /** Values to be written to the destination misc. registers. */ 11110835Sandreas.hansson@arm.com std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 1129046SAli.Saidi@ARM.com 1137783SGiacomo.Gabrielli@arm.com /** Indexes of the destination misc. registers. They are needed to defer 1147783SGiacomo.Gabrielli@arm.com * the write accesses to the misc. registers until the commit stage, when 1157783SGiacomo.Gabrielli@arm.com * the instruction is out of its speculative state. 1167783SGiacomo.Gabrielli@arm.com */ 11710835Sandreas.hansson@arm.com std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 1189046SAli.Saidi@ARM.com 1197783SGiacomo.Gabrielli@arm.com /** Number of destination misc. registers. */ 1209046SAli.Saidi@ARM.com uint8_t _numDestMiscRegs; 1219046SAli.Saidi@ARM.com 1227783SGiacomo.Gabrielli@arm.com 1235596Sgblack@eecs.umich.edu public: 1248471SGiacomo.Gabrielli@arm.com#if TRACING_ON 1258471SGiacomo.Gabrielli@arm.com /** Tick records used for the pipeline activity viewer. */ 1269252Sdjordje.kovacevic@arm.com Tick fetchTick; // instruction fetch is completed. 1279252Sdjordje.kovacevic@arm.com int32_t decodeTick; // instruction enters decode phase 1289252Sdjordje.kovacevic@arm.com int32_t renameTick; // instruction enters rename phase 1299252Sdjordje.kovacevic@arm.com int32_t dispatchTick; 1309252Sdjordje.kovacevic@arm.com int32_t issueTick; 1319252Sdjordje.kovacevic@arm.com int32_t completeTick; 1329252Sdjordje.kovacevic@arm.com int32_t commitTick; 1339527SMatt.Horsnell@arm.com int32_t storeTick; 1348471SGiacomo.Gabrielli@arm.com#endif 1358471SGiacomo.Gabrielli@arm.com 1365596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1375596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1385596Sgblack@eecs.umich.edu */ 1395596Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 1405596Sgblack@eecs.umich.edu { 1415596Sgblack@eecs.umich.edu return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1425596Sgblack@eecs.umich.edu } 1435596Sgblack@eecs.umich.edu 1445596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1455596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1465596Sgblack@eecs.umich.edu */ 1475596Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 1485596Sgblack@eecs.umich.edu { 1497783SGiacomo.Gabrielli@arm.com /** Writes to misc. registers are recorded and deferred until the 1509532Sgeoffrey.blake@arm.com * commit stage, when updateMiscRegs() is called. First, check if 1519532Sgeoffrey.blake@arm.com * the misc reg has been written before and update its value to be 1529532Sgeoffrey.blake@arm.com * committed instead of making a new entry. If not, make a new 1539532Sgeoffrey.blake@arm.com * entry and record the write. 1547783SGiacomo.Gabrielli@arm.com */ 1559532Sgeoffrey.blake@arm.com for (int idx = 0; idx < _numDestMiscRegs; idx++) { 1569532Sgeoffrey.blake@arm.com if (_destMiscRegIdx[idx] == misc_reg) { 1579532Sgeoffrey.blake@arm.com _destMiscRegVal[idx] = val; 1589532Sgeoffrey.blake@arm.com return; 1599532Sgeoffrey.blake@arm.com } 1609532Sgeoffrey.blake@arm.com } 1619532Sgeoffrey.blake@arm.com 1629046SAli.Saidi@ARM.com assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 1637783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1647783SGiacomo.Gabrielli@arm.com _destMiscRegVal[_numDestMiscRegs] = val; 1657783SGiacomo.Gabrielli@arm.com _numDestMiscRegs++; 1665596Sgblack@eecs.umich.edu } 1675596Sgblack@eecs.umich.edu 1685596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1695596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1705596Sgblack@eecs.umich.edu */ 1715596Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 1725596Sgblack@eecs.umich.edu { 17312104Snathanael.premillieu@arm.com RegId reg = si->srcRegIdx(idx); 17412104Snathanael.premillieu@arm.com assert(reg.regClass == MiscRegClass); 17512104Snathanael.premillieu@arm.com return this->cpu->readMiscReg(reg.regIdx, this->threadNumber); 1765596Sgblack@eecs.umich.edu } 1775596Sgblack@eecs.umich.edu 1785596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1795596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1805596Sgblack@eecs.umich.edu */ 1815596Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, 1825596Sgblack@eecs.umich.edu const MiscReg &val) 1835596Sgblack@eecs.umich.edu { 18412104Snathanael.premillieu@arm.com RegId reg = si->destRegIdx(idx); 18512104Snathanael.premillieu@arm.com assert(reg.regClass == MiscRegClass); 18612104Snathanael.premillieu@arm.com setMiscReg(reg.regIdx, val); 1877783SGiacomo.Gabrielli@arm.com } 1887783SGiacomo.Gabrielli@arm.com 1897783SGiacomo.Gabrielli@arm.com /** Called at the commit stage to update the misc. registers. */ 1907783SGiacomo.Gabrielli@arm.com void updateMiscRegs() 1917783SGiacomo.Gabrielli@arm.com { 1927783SGiacomo.Gabrielli@arm.com // @todo: Pretty convoluted way to avoid squashing from happening when 1937783SGiacomo.Gabrielli@arm.com // using the TC during an instruction's execution (specifically for 1947783SGiacomo.Gabrielli@arm.com // instructions that have side-effects that use the TC). Fix this. 1957783SGiacomo.Gabrielli@arm.com // See cpu/o3/dyn_inst_impl.hh. 1969382SAli.Saidi@ARM.com bool no_squash_from_TC = this->thread->noSquashFromTC; 1979382SAli.Saidi@ARM.com this->thread->noSquashFromTC = true; 1987783SGiacomo.Gabrielli@arm.com 1997783SGiacomo.Gabrielli@arm.com for (int i = 0; i < _numDestMiscRegs; i++) 2007783SGiacomo.Gabrielli@arm.com this->cpu->setMiscReg( 2017783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 2027783SGiacomo.Gabrielli@arm.com 2039382SAli.Saidi@ARM.com this->thread->noSquashFromTC = no_squash_from_TC; 2045596Sgblack@eecs.umich.edu } 2055596Sgblack@eecs.umich.edu 2067848SAli.Saidi@ARM.com void forwardOldRegs() 2077848SAli.Saidi@ARM.com { 20810935Snilay@cs.wisc.edu 2097848SAli.Saidi@ARM.com for (int idx = 0; idx < this->numDestRegs(); idx++) { 21012105Snathanael.premillieu@arm.com PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx); 21112104Snathanael.premillieu@arm.com RegId original_dest_reg = 2129913Ssteve.reinhardt@amd.com this->staticInst->destRegIdx(idx); 21312104Snathanael.premillieu@arm.com switch (original_dest_reg.regClass) { 2149913Ssteve.reinhardt@amd.com case IntRegClass: 2159913Ssteve.reinhardt@amd.com this->setIntRegOperand(this->staticInst.get(), idx, 2169913Ssteve.reinhardt@amd.com this->cpu->readIntReg(prev_phys_reg)); 2179913Ssteve.reinhardt@amd.com break; 2189913Ssteve.reinhardt@amd.com case FloatRegClass: 2199913Ssteve.reinhardt@amd.com this->setFloatRegOperandBits(this->staticInst.get(), idx, 2209913Ssteve.reinhardt@amd.com this->cpu->readFloatRegBits(prev_phys_reg)); 2219913Ssteve.reinhardt@amd.com break; 2229920Syasuko.eckert@amd.com case CCRegClass: 2239920Syasuko.eckert@amd.com this->setCCRegOperand(this->staticInst.get(), idx, 2249920Syasuko.eckert@amd.com this->cpu->readCCReg(prev_phys_reg)); 2259920Syasuko.eckert@amd.com break; 2269913Ssteve.reinhardt@amd.com case MiscRegClass: 2279913Ssteve.reinhardt@amd.com // no need to forward misc reg values 2289913Ssteve.reinhardt@amd.com break; 2299913Ssteve.reinhardt@amd.com } 2307848SAli.Saidi@ARM.com } 2317848SAli.Saidi@ARM.com } 2325702Ssaidi@eecs.umich.edu /** Calls hardware return from error interrupt. */ 2335702Ssaidi@eecs.umich.edu Fault hwrei(); 2345596Sgblack@eecs.umich.edu /** Traps to handle specified fault. */ 23510379Sandreas.hansson@arm.com void trap(const Fault &fault); 2365702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2378557Sgblack@eecs.umich.edu 2388557Sgblack@eecs.umich.edu /** Emulates a syscall. */ 23911877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault); 2402847Sksewell@umich.edu 2415596Sgblack@eecs.umich.edu public: 2425596Sgblack@eecs.umich.edu 2435596Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 2445596Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 2455596Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 2465596Sgblack@eecs.umich.edu // renaming. We find the architectural register index by indexing 2475596Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 2485596Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 2495596Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2505596Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 2515596Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 2525596Sgblack@eecs.umich.edu // to do). 2535596Sgblack@eecs.umich.edu 25410319SAndreas.Sandberg@ARM.com IntReg readIntRegOperand(const StaticInst *si, int idx) 2555596Sgblack@eecs.umich.edu { 2565596Sgblack@eecs.umich.edu return this->cpu->readIntReg(this->_srcRegIdx[idx]); 2575596Sgblack@eecs.umich.edu } 2585596Sgblack@eecs.umich.edu 2595596Sgblack@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2605596Sgblack@eecs.umich.edu { 2615596Sgblack@eecs.umich.edu return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 2625596Sgblack@eecs.umich.edu } 2635596Sgblack@eecs.umich.edu 2645596Sgblack@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2655596Sgblack@eecs.umich.edu { 2665596Sgblack@eecs.umich.edu return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 2675596Sgblack@eecs.umich.edu } 2685596Sgblack@eecs.umich.edu 26910319SAndreas.Sandberg@ARM.com CCReg readCCRegOperand(const StaticInst *si, int idx) 2709920Syasuko.eckert@amd.com { 2719920Syasuko.eckert@amd.com return this->cpu->readCCReg(this->_srcRegIdx[idx]); 2729920Syasuko.eckert@amd.com } 2739920Syasuko.eckert@amd.com 2745596Sgblack@eecs.umich.edu /** @todo: Make results into arrays so they can handle multiple dest 2755596Sgblack@eecs.umich.edu * registers. 2765596Sgblack@eecs.umich.edu */ 27710319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 2785596Sgblack@eecs.umich.edu { 2795596Sgblack@eecs.umich.edu this->cpu->setIntReg(this->_destRegIdx[idx], val); 2805596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 2815596Sgblack@eecs.umich.edu } 2825596Sgblack@eecs.umich.edu 2835596Sgblack@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2845596Sgblack@eecs.umich.edu { 2855596Sgblack@eecs.umich.edu this->cpu->setFloatReg(this->_destRegIdx[idx], val); 2865596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 2875596Sgblack@eecs.umich.edu } 2885596Sgblack@eecs.umich.edu 2895596Sgblack@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2905596Sgblack@eecs.umich.edu FloatRegBits val) 2915596Sgblack@eecs.umich.edu { 2925596Sgblack@eecs.umich.edu this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 2935596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 2945596Sgblack@eecs.umich.edu } 2955596Sgblack@eecs.umich.edu 29610319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 2979920Syasuko.eckert@amd.com { 2989920Syasuko.eckert@amd.com this->cpu->setCCReg(this->_destRegIdx[idx], val); 2999920Syasuko.eckert@amd.com BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 3009920Syasuko.eckert@amd.com } 3019920Syasuko.eckert@amd.com 3025596Sgblack@eecs.umich.edu#if THE_ISA == MIPS_ISA 30312104Snathanael.premillieu@arm.com MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) 3045596Sgblack@eecs.umich.edu { 3055596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 3065596Sgblack@eecs.umich.edu return 0; 3075596Sgblack@eecs.umich.edu } 3085596Sgblack@eecs.umich.edu 30912104Snathanael.premillieu@arm.com void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) 3105596Sgblack@eecs.umich.edu { 3115596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 3125596Sgblack@eecs.umich.edu } 3135596Sgblack@eecs.umich.edu#endif 3145596Sgblack@eecs.umich.edu 3155596Sgblack@eecs.umich.edu public: 3165596Sgblack@eecs.umich.edu /** Calculates EA part of a memory instruction. Currently unused, 3175596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 3185596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 3195596Sgblack@eecs.umich.edu */ 3205596Sgblack@eecs.umich.edu Fault calcEA() 3215596Sgblack@eecs.umich.edu { 3225596Sgblack@eecs.umich.edu return this->staticInst->eaCompInst()->execute(this, this->traceData); 3235596Sgblack@eecs.umich.edu } 3245596Sgblack@eecs.umich.edu 3255596Sgblack@eecs.umich.edu /** Does the memory access part of a memory instruction. Currently unused, 3265596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 3275596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 3285596Sgblack@eecs.umich.edu */ 3295596Sgblack@eecs.umich.edu Fault memAccess() 3305596Sgblack@eecs.umich.edu { 3315596Sgblack@eecs.umich.edu return this->staticInst->memAccInst()->execute(this, this->traceData); 3325596Sgblack@eecs.umich.edu } 3335596Sgblack@eecs.umich.edu}; 3345596Sgblack@eecs.umich.edu 3355596Sgblack@eecs.umich.edu#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 3365596Sgblack@eecs.umich.edu 337