dyn_inst.hh revision 12104
112953Sgabeblack@google.com/* 212953Sgabeblack@google.com * Copyright (c) 2010 ARM Limited 312953Sgabeblack@google.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 412953Sgabeblack@google.com * All rights reserved 512953Sgabeblack@google.com * 612953Sgabeblack@google.com * The license below extends only to copyright in the software and shall 712953Sgabeblack@google.com * not be construed as granting a license to any other intellectual 812953Sgabeblack@google.com * property including but not limited to intellectual property relating 912953Sgabeblack@google.com * to a hardware implementation of the functionality of the software 1012953Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1112953Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1212953Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1312953Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1412953Sgabeblack@google.com * 1512953Sgabeblack@google.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1612953Sgabeblack@google.com * All rights reserved. 1712953Sgabeblack@google.com * 1812953Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1912953Sgabeblack@google.com * modification, are permitted provided that the following conditions are 2012953Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2112953Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2212953Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2312953Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2412953Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2512953Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2612953Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2712953Sgabeblack@google.com * this software without specific prior written permission. 2812953Sgabeblack@google.com * 2912953Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012953Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112953Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212953Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3313063Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3413063Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3513063Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612957Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712957Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812961Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3913063Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012954Sgabeblack@google.com * 4112954Sgabeblack@google.com * Authors: Kevin Lim 4212953Sgabeblack@google.com */ 4312953Sgabeblack@google.com 4413063Sgabeblack@google.com#ifndef __CPU_O3_DYN_INST_HH__ 4512953Sgabeblack@google.com#define __CPU_O3_DYN_INST_HH__ 4612961Sgabeblack@google.com 4712961Sgabeblack@google.com#include <array> 4812953Sgabeblack@google.com 4912953Sgabeblack@google.com#include "arch/isa_traits.hh" 5012953Sgabeblack@google.com#include "config/the_isa.hh" 5112953Sgabeblack@google.com#include "cpu/o3/cpu.hh" 5212954Sgabeblack@google.com#include "cpu/o3/isa_specific.hh" 5312954Sgabeblack@google.com#include "cpu/base_dyn_inst.hh" 5412954Sgabeblack@google.com#include "cpu/inst_seq.hh" 5512954Sgabeblack@google.com#include "cpu/reg_class.hh" 5612954Sgabeblack@google.com 5712954Sgabeblack@google.comclass Packet; 5812954Sgabeblack@google.com 5912954Sgabeblack@google.comtemplate <class Impl> 6012954Sgabeblack@google.comclass BaseO3DynInst : public BaseDynInst<Impl> 6112954Sgabeblack@google.com{ 6212954Sgabeblack@google.com public: 6312954Sgabeblack@google.com /** Typedef for the CPU. */ 6412954Sgabeblack@google.com typedef typename Impl::O3CPU O3CPU; 6512954Sgabeblack@google.com 6612954Sgabeblack@google.com /** Binary machine instruction type. */ 6712954Sgabeblack@google.com typedef TheISA::MachInst MachInst; 6812954Sgabeblack@google.com /** Extended machine instruction type. */ 6912954Sgabeblack@google.com typedef TheISA::ExtMachInst ExtMachInst; 7012954Sgabeblack@google.com /** Register types. */ 7112957Sgabeblack@google.com typedef TheISA::IntReg IntReg; 7212954Sgabeblack@google.com typedef TheISA::FloatReg FloatReg; 7312954Sgabeblack@google.com typedef TheISA::FloatRegBits FloatRegBits; 7412954Sgabeblack@google.com typedef TheISA::CCReg CCReg; 7512954Sgabeblack@google.com 7612954Sgabeblack@google.com /** Misc register type. */ 7712954Sgabeblack@google.com typedef TheISA::MiscReg MiscReg; 7812954Sgabeblack@google.com 7912954Sgabeblack@google.com enum { 8012954Sgabeblack@google.com MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 8112954Sgabeblack@google.com MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 8212954Sgabeblack@google.com }; 8312954Sgabeblack@google.com 8412954Sgabeblack@google.com public: 8512954Sgabeblack@google.com /** BaseDynInst constructor given a binary instruction. */ 8612954Sgabeblack@google.com BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 8712954Sgabeblack@google.com TheISA::PCState pc, TheISA::PCState predPC, 8812954Sgabeblack@google.com InstSeqNum seq_num, O3CPU *cpu); 8913063Sgabeblack@google.com 9012954Sgabeblack@google.com /** BaseDynInst constructor given a static inst pointer. */ 9112954Sgabeblack@google.com BaseO3DynInst(const StaticInstPtr &_staticInst, 9212954Sgabeblack@google.com const StaticInstPtr &_macroop); 9312954Sgabeblack@google.com 9412954Sgabeblack@google.com ~BaseO3DynInst(); 9512954Sgabeblack@google.com 9612954Sgabeblack@google.com /** Executes the instruction.*/ 9712954Sgabeblack@google.com Fault execute(); 9812954Sgabeblack@google.com 9913063Sgabeblack@google.com /** Initiates the access. Only valid for memory operations. */ 10013063Sgabeblack@google.com Fault initiateAcc(); 10112954Sgabeblack@google.com 10212954Sgabeblack@google.com /** Completes the access. Only valid for memory operations. */ 10313063Sgabeblack@google.com Fault completeAcc(PacketPtr pkt); 10413063Sgabeblack@google.com 10512954Sgabeblack@google.com private: 10612954Sgabeblack@google.com /** Initializes variables. */ 10712954Sgabeblack@google.com void initVars(); 10812954Sgabeblack@google.com 10913063Sgabeblack@google.com protected: 11013063Sgabeblack@google.com /** Values to be written to the destination misc. registers. */ 11113063Sgabeblack@google.com std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal; 11213063Sgabeblack@google.com 11313063Sgabeblack@google.com /** Indexes of the destination misc. registers. They are needed to defer 11412961Sgabeblack@google.com * the write accesses to the misc. registers until the commit stage, when 11512961Sgabeblack@google.com * the instruction is out of its speculative state. 11612961Sgabeblack@google.com */ 11712961Sgabeblack@google.com std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx; 11812961Sgabeblack@google.com 11912961Sgabeblack@google.com /** Number of destination misc. registers. */ 12012961Sgabeblack@google.com uint8_t _numDestMiscRegs; 12112961Sgabeblack@google.com 12212961Sgabeblack@google.com 12312961Sgabeblack@google.com public: 12412961Sgabeblack@google.com#if TRACING_ON 12512961Sgabeblack@google.com /** Tick records used for the pipeline activity viewer. */ 12612961Sgabeblack@google.com Tick fetchTick; // instruction fetch is completed. 12712961Sgabeblack@google.com int32_t decodeTick; // instruction enters decode phase 12812961Sgabeblack@google.com int32_t renameTick; // instruction enters rename phase 12912961Sgabeblack@google.com int32_t dispatchTick; 13012961Sgabeblack@google.com int32_t issueTick; 13112961Sgabeblack@google.com int32_t completeTick; 13212961Sgabeblack@google.com int32_t commitTick; 13312961Sgabeblack@google.com int32_t storeTick; 13412961Sgabeblack@google.com#endif 13513058Sgabeblack@google.com 13613058Sgabeblack@google.com /** Reads a misc. register, including any side-effects the read 13713058Sgabeblack@google.com * might have as defined by the architecture. 13813058Sgabeblack@google.com */ 13913058Sgabeblack@google.com MiscReg readMiscReg(int misc_reg) 14013058Sgabeblack@google.com { 14113058Sgabeblack@google.com return this->cpu->readMiscReg(misc_reg, this->threadNumber); 14213058Sgabeblack@google.com } 14312954Sgabeblack@google.com 14412953Sgabeblack@google.com /** Sets a misc. register, including any side-effects the write 14512953Sgabeblack@google.com * might have as defined by the architecture. 14612953Sgabeblack@google.com */ 14712953Sgabeblack@google.com void setMiscReg(int misc_reg, const MiscReg &val) 14813144Sgabeblack@google.com { 14913063Sgabeblack@google.com /** Writes to misc. registers are recorded and deferred until the 15013063Sgabeblack@google.com * commit stage, when updateMiscRegs() is called. First, check if 15113063Sgabeblack@google.com * the misc reg has been written before and update its value to be 15213063Sgabeblack@google.com * committed instead of making a new entry. If not, make a new 15313063Sgabeblack@google.com * entry and record the write. 15413063Sgabeblack@google.com */ 15513063Sgabeblack@google.com for (int idx = 0; idx < _numDestMiscRegs; idx++) { 15613063Sgabeblack@google.com if (_destMiscRegIdx[idx] == misc_reg) { 15713063Sgabeblack@google.com _destMiscRegVal[idx] = val; 15813063Sgabeblack@google.com return; 15913063Sgabeblack@google.com } 16013063Sgabeblack@google.com } 16112953Sgabeblack@google.com 16213072Sgabeblack@google.com assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 16312953Sgabeblack@google.com _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 16413076Sgabeblack@google.com _destMiscRegVal[_numDestMiscRegs] = val; 16513076Sgabeblack@google.com _numDestMiscRegs++; 16612954Sgabeblack@google.com } 16712954Sgabeblack@google.com 16812953Sgabeblack@google.com /** Reads a misc. register, including any side-effects the read 16912953Sgabeblack@google.com * might have as defined by the architecture. 17012953Sgabeblack@google.com */ 17113067Sgabeblack@google.com TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 17212953Sgabeblack@google.com { 17312957Sgabeblack@google.com RegId reg = si->srcRegIdx(idx); 17412957Sgabeblack@google.com assert(reg.regClass == MiscRegClass); 17512957Sgabeblack@google.com return this->cpu->readMiscReg(reg.regIdx, this->threadNumber); 17612953Sgabeblack@google.com } 17712953Sgabeblack@google.com 17812953Sgabeblack@google.com /** Sets a misc. register, including any side-effects the write 17912953Sgabeblack@google.com * might have as defined by the architecture. 18012954Sgabeblack@google.com */ 18112954Sgabeblack@google.com void setMiscRegOperand(const StaticInst *si, int idx, 18213133Sgabeblack@google.com const MiscReg &val) 18313133Sgabeblack@google.com { 18413133Sgabeblack@google.com RegId reg = si->destRegIdx(idx); 18513133Sgabeblack@google.com assert(reg.regClass == MiscRegClass); 18613133Sgabeblack@google.com setMiscReg(reg.regIdx, val); 18713133Sgabeblack@google.com } 18813133Sgabeblack@google.com 18913133Sgabeblack@google.com /** Called at the commit stage to update the misc. registers. */ 19012954Sgabeblack@google.com void updateMiscRegs() 19112954Sgabeblack@google.com { 19212953Sgabeblack@google.com // @todo: Pretty convoluted way to avoid squashing from happening when 19312953Sgabeblack@google.com // using the TC during an instruction's execution (specifically for 19412953Sgabeblack@google.com // instructions that have side-effects that use the TC). Fix this. 19512953Sgabeblack@google.com // See cpu/o3/dyn_inst_impl.hh. 19612953Sgabeblack@google.com bool no_squash_from_TC = this->thread->noSquashFromTC; 19713209Sgabeblack@google.com this->thread->noSquashFromTC = true; 19813209Sgabeblack@google.com 19913209Sgabeblack@google.com for (int i = 0; i < _numDestMiscRegs; i++) 20013209Sgabeblack@google.com this->cpu->setMiscReg( 20113176Sgabeblack@google.com _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 20212953Sgabeblack@google.com 20312953Sgabeblack@google.com this->thread->noSquashFromTC = no_squash_from_TC; 20413209Sgabeblack@google.com } 20512953Sgabeblack@google.com 20613209Sgabeblack@google.com void forwardOldRegs() 20712953Sgabeblack@google.com { 20812953Sgabeblack@google.com 20912953Sgabeblack@google.com for (int idx = 0; idx < this->numDestRegs(); idx++) { 21012954Sgabeblack@google.com PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 21112954Sgabeblack@google.com RegId original_dest_reg = 21212954Sgabeblack@google.com this->staticInst->destRegIdx(idx); 21312962Sgabeblack@google.com switch (original_dest_reg.regClass) { 21412962Sgabeblack@google.com case IntRegClass: 21512962Sgabeblack@google.com this->setIntRegOperand(this->staticInst.get(), idx, 21613063Sgabeblack@google.com this->cpu->readIntReg(prev_phys_reg)); 21713063Sgabeblack@google.com break; 21813063Sgabeblack@google.com case FloatRegClass: 21913063Sgabeblack@google.com this->setFloatRegOperandBits(this->staticInst.get(), idx, 22013063Sgabeblack@google.com this->cpu->readFloatRegBits(prev_phys_reg)); 22113063Sgabeblack@google.com break; 22213063Sgabeblack@google.com case CCRegClass: 22312962Sgabeblack@google.com this->setCCRegOperand(this->staticInst.get(), idx, 22412962Sgabeblack@google.com this->cpu->readCCReg(prev_phys_reg)); 22513063Sgabeblack@google.com break; 22612962Sgabeblack@google.com case MiscRegClass: 22713063Sgabeblack@google.com // no need to forward misc reg values 22813125Sgabeblack@google.com break; 22913125Sgabeblack@google.com } 23013125Sgabeblack@google.com } 23113063Sgabeblack@google.com } 23213063Sgabeblack@google.com /** Calls hardware return from error interrupt. */ 23313144Sgabeblack@google.com Fault hwrei(); 23413244Sgabeblack@google.com /** Traps to handle specified fault. */ 23513244Sgabeblack@google.com void trap(const Fault &fault); 23613063Sgabeblack@google.com bool simPalCheck(int palFunc); 23713063Sgabeblack@google.com 23813063Sgabeblack@google.com /** Emulates a syscall. */ 23913063Sgabeblack@google.com void syscall(int64_t callnum, Fault *fault); 24013063Sgabeblack@google.com 24113063Sgabeblack@google.com public: 24213063Sgabeblack@google.com 24313069Sgabeblack@google.com // The register accessor methods provide the index of the 24413063Sgabeblack@google.com // instruction's operand (e.g., 0 or 1), not the architectural 24513144Sgabeblack@google.com // register index, to simplify the implementation of register 24612962Sgabeblack@google.com // renaming. We find the architectural register index by indexing 24712962Sgabeblack@google.com // into the instruction's own operand index table. Note that a 24812962Sgabeblack@google.com // raw pointer to the StaticInst is provided instead of a 24912962Sgabeblack@google.com // ref-counted StaticInstPtr to redice overhead. This is fine as 25013063Sgabeblack@google.com // long as these methods don't copy the pointer into any long-term 25112962Sgabeblack@google.com // storage (which is pretty hard to imagine they would have reason 25213144Sgabeblack@google.com // to do). 25313144Sgabeblack@google.com 25413144Sgabeblack@google.com IntReg readIntRegOperand(const StaticInst *si, int idx) 25513144Sgabeblack@google.com { 25613144Sgabeblack@google.com return this->cpu->readIntReg(this->_srcRegIdx[idx]); 25713063Sgabeblack@google.com } 25812985Sgabeblack@google.com 25913063Sgabeblack@google.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) 26013063Sgabeblack@google.com { 26113063Sgabeblack@google.com return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 26213063Sgabeblack@google.com } 26313063Sgabeblack@google.com 26413063Sgabeblack@google.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 26513144Sgabeblack@google.com { 26613063Sgabeblack@google.com return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 26713063Sgabeblack@google.com } 26813063Sgabeblack@google.com 26913063Sgabeblack@google.com CCReg readCCRegOperand(const StaticInst *si, int idx) 27013069Sgabeblack@google.com { 27113063Sgabeblack@google.com return this->cpu->readCCReg(this->_srcRegIdx[idx]); 27213063Sgabeblack@google.com } 27312962Sgabeblack@google.com 27412962Sgabeblack@google.com /** @todo: Make results into arrays so they can handle multiple dest 27512962Sgabeblack@google.com * registers. 27613063Sgabeblack@google.com */ 27712962Sgabeblack@google.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 27813140Sgabeblack@google.com { 27913063Sgabeblack@google.com this->cpu->setIntReg(this->_destRegIdx[idx], val); 28013063Sgabeblack@google.com BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 28113096Sgabeblack@google.com } 28213096Sgabeblack@google.com 28312962Sgabeblack@google.com void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 28412962Sgabeblack@google.com { 28512962Sgabeblack@google.com this->cpu->setFloatReg(this->_destRegIdx[idx], val); 28612962Sgabeblack@google.com BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 28712962Sgabeblack@google.com } 28812962Sgabeblack@google.com 28912962Sgabeblack@google.com void setFloatRegOperandBits(const StaticInst *si, int idx, 29012962Sgabeblack@google.com FloatRegBits val) 29112962Sgabeblack@google.com { 29212962Sgabeblack@google.com this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 29312962Sgabeblack@google.com BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 29412962Sgabeblack@google.com } 29512962Sgabeblack@google.com 29613176Sgabeblack@google.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 29713176Sgabeblack@google.com { 29812962Sgabeblack@google.com this->cpu->setCCReg(this->_destRegIdx[idx], val); 29912962Sgabeblack@google.com BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 30012962Sgabeblack@google.com } 30112962Sgabeblack@google.com 30212962Sgabeblack@google.com#if THE_ISA == MIPS_ISA 30312962Sgabeblack@google.com MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) 30413063Sgabeblack@google.com { 30512962Sgabeblack@google.com panic("MIPS MT not defined for O3 CPU.\n"); 30612962Sgabeblack@google.com return 0; 30712962Sgabeblack@google.com } 30812962Sgabeblack@google.com 30912962Sgabeblack@google.com void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) 31012962Sgabeblack@google.com { 31113063Sgabeblack@google.com panic("MIPS MT not defined for O3 CPU.\n"); 31212962Sgabeblack@google.com } 31313063Sgabeblack@google.com#endif 31413063Sgabeblack@google.com 31513063Sgabeblack@google.com public: 31612962Sgabeblack@google.com /** Calculates EA part of a memory instruction. Currently unused, 31712954Sgabeblack@google.com * though it may be useful in the future if we want to split 31812954Sgabeblack@google.com * memory operations into EA calculation and memory access parts. 31913186Sgabeblack@google.com */ 32013186Sgabeblack@google.com Fault calcEA() 32113186Sgabeblack@google.com { 32213186Sgabeblack@google.com return this->staticInst->eaCompInst()->execute(this, this->traceData); 32312954Sgabeblack@google.com } 32412961Sgabeblack@google.com 32512961Sgabeblack@google.com /** Does the memory access part of a memory instruction. Currently unused, 32612961Sgabeblack@google.com * though it may be useful in the future if we want to split 32713061Sgabeblack@google.com * memory operations into EA calculation and memory access parts. 32812961Sgabeblack@google.com */ 32912961Sgabeblack@google.com Fault memAccess() 33012961Sgabeblack@google.com { 33112961Sgabeblack@google.com return this->staticInst->memAccInst()->execute(this, this->traceData); 33213186Sgabeblack@google.com } 33313186Sgabeblack@google.com}; 33413186Sgabeblack@google.com 33513244Sgabeblack@google.com#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 33613244Sgabeblack@google.com 33713186Sgabeblack@google.com