dyn_inst.hh revision 10319
12847Sksewell@umich.edu/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2010 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 155596Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162847Sksewell@umich.edu * All rights reserved. 172847Sksewell@umich.edu * 182847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192847Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242847Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272847Sksewell@umich.edu * this software without specific prior written permission. 282847Sksewell@umich.edu * 292847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402847Sksewell@umich.edu * 415596Sgblack@eecs.umich.edu * Authors: Kevin Lim 422847Sksewell@umich.edu */ 432847Sksewell@umich.edu 442847Sksewell@umich.edu#ifndef __CPU_O3_DYN_INST_HH__ 452847Sksewell@umich.edu#define __CPU_O3_DYN_INST_HH__ 462847Sksewell@umich.edu 475596Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/o3/cpu.hh" 508229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 515596Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh" 525596Sgblack@eecs.umich.edu#include "cpu/inst_seq.hh" 539913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 542847Sksewell@umich.edu 555596Sgblack@eecs.umich.educlass Packet; 565596Sgblack@eecs.umich.edu 575596Sgblack@eecs.umich.edutemplate <class Impl> 585596Sgblack@eecs.umich.educlass BaseO3DynInst : public BaseDynInst<Impl> 595596Sgblack@eecs.umich.edu{ 605596Sgblack@eecs.umich.edu public: 615596Sgblack@eecs.umich.edu /** Typedef for the CPU. */ 625596Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 635596Sgblack@eecs.umich.edu 645596Sgblack@eecs.umich.edu /** Binary machine instruction type. */ 655596Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 665596Sgblack@eecs.umich.edu /** Extended machine instruction type. */ 675596Sgblack@eecs.umich.edu typedef TheISA::ExtMachInst ExtMachInst; 685596Sgblack@eecs.umich.edu /** Logical register index type. */ 695596Sgblack@eecs.umich.edu typedef TheISA::RegIndex RegIndex; 705596Sgblack@eecs.umich.edu /** Integer register index type. */ 715596Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 725596Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 735596Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 749920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 7510319SAndreas.Sandberg@ARM.com 765596Sgblack@eecs.umich.edu /** Misc register index type. */ 775596Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 785596Sgblack@eecs.umich.edu 795596Sgblack@eecs.umich.edu enum { 805596Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 818902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 825596Sgblack@eecs.umich.edu }; 835596Sgblack@eecs.umich.edu 845596Sgblack@eecs.umich.edu public: 855596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. */ 868502Sgblack@eecs.umich.edu BaseO3DynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 877720Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 887720Sgblack@eecs.umich.edu InstSeqNum seq_num, O3CPU *cpu); 895596Sgblack@eecs.umich.edu 905596Sgblack@eecs.umich.edu /** BaseDynInst constructor given a static inst pointer. */ 918502Sgblack@eecs.umich.edu BaseO3DynInst(StaticInstPtr _staticInst, StaticInstPtr _macroop); 925596Sgblack@eecs.umich.edu 939252Sdjordje.kovacevic@arm.com ~BaseO3DynInst(); 949252Sdjordje.kovacevic@arm.com 955596Sgblack@eecs.umich.edu /** Executes the instruction.*/ 965596Sgblack@eecs.umich.edu Fault execute(); 975596Sgblack@eecs.umich.edu 985596Sgblack@eecs.umich.edu /** Initiates the access. Only valid for memory operations. */ 995596Sgblack@eecs.umich.edu Fault initiateAcc(); 1005596Sgblack@eecs.umich.edu 1015596Sgblack@eecs.umich.edu /** Completes the access. Only valid for memory operations. */ 1025596Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr pkt); 1035596Sgblack@eecs.umich.edu 1045596Sgblack@eecs.umich.edu private: 1055596Sgblack@eecs.umich.edu /** Initializes variables. */ 1065596Sgblack@eecs.umich.edu void initVars(); 1075596Sgblack@eecs.umich.edu 1087783SGiacomo.Gabrielli@arm.com protected: 1099046SAli.Saidi@ARM.com /** Values to be written to the destination misc. registers. */ 1109046SAli.Saidi@ARM.com MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs]; 1119046SAli.Saidi@ARM.com 1127783SGiacomo.Gabrielli@arm.com /** Indexes of the destination misc. registers. They are needed to defer 1137783SGiacomo.Gabrielli@arm.com * the write accesses to the misc. registers until the commit stage, when 1147783SGiacomo.Gabrielli@arm.com * the instruction is out of its speculative state. 1157783SGiacomo.Gabrielli@arm.com */ 1169046SAli.Saidi@ARM.com short _destMiscRegIdx[TheISA::MaxMiscDestRegs]; 1179046SAli.Saidi@ARM.com 1187783SGiacomo.Gabrielli@arm.com /** Number of destination misc. registers. */ 1199046SAli.Saidi@ARM.com uint8_t _numDestMiscRegs; 1209046SAli.Saidi@ARM.com 1217783SGiacomo.Gabrielli@arm.com 1225596Sgblack@eecs.umich.edu public: 1238471SGiacomo.Gabrielli@arm.com#if TRACING_ON 1248471SGiacomo.Gabrielli@arm.com /** Tick records used for the pipeline activity viewer. */ 1259252Sdjordje.kovacevic@arm.com Tick fetchTick; // instruction fetch is completed. 1269252Sdjordje.kovacevic@arm.com int32_t decodeTick; // instruction enters decode phase 1279252Sdjordje.kovacevic@arm.com int32_t renameTick; // instruction enters rename phase 1289252Sdjordje.kovacevic@arm.com int32_t dispatchTick; 1299252Sdjordje.kovacevic@arm.com int32_t issueTick; 1309252Sdjordje.kovacevic@arm.com int32_t completeTick; 1319252Sdjordje.kovacevic@arm.com int32_t commitTick; 1329527SMatt.Horsnell@arm.com int32_t storeTick; 1338471SGiacomo.Gabrielli@arm.com#endif 1348471SGiacomo.Gabrielli@arm.com 1355596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1365596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1375596Sgblack@eecs.umich.edu */ 1385596Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 1395596Sgblack@eecs.umich.edu { 1405596Sgblack@eecs.umich.edu return this->cpu->readMiscReg(misc_reg, this->threadNumber); 1415596Sgblack@eecs.umich.edu } 1425596Sgblack@eecs.umich.edu 1435596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1445596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1455596Sgblack@eecs.umich.edu */ 1465596Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 1475596Sgblack@eecs.umich.edu { 1487783SGiacomo.Gabrielli@arm.com /** Writes to misc. registers are recorded and deferred until the 1499532Sgeoffrey.blake@arm.com * commit stage, when updateMiscRegs() is called. First, check if 1509532Sgeoffrey.blake@arm.com * the misc reg has been written before and update its value to be 1519532Sgeoffrey.blake@arm.com * committed instead of making a new entry. If not, make a new 1529532Sgeoffrey.blake@arm.com * entry and record the write. 1537783SGiacomo.Gabrielli@arm.com */ 1549532Sgeoffrey.blake@arm.com for (int idx = 0; idx < _numDestMiscRegs; idx++) { 1559532Sgeoffrey.blake@arm.com if (_destMiscRegIdx[idx] == misc_reg) { 1569532Sgeoffrey.blake@arm.com _destMiscRegVal[idx] = val; 1579532Sgeoffrey.blake@arm.com return; 1589532Sgeoffrey.blake@arm.com } 1599532Sgeoffrey.blake@arm.com } 1609532Sgeoffrey.blake@arm.com 1619046SAli.Saidi@ARM.com assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs); 1627783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[_numDestMiscRegs] = misc_reg; 1637783SGiacomo.Gabrielli@arm.com _destMiscRegVal[_numDestMiscRegs] = val; 1647783SGiacomo.Gabrielli@arm.com _numDestMiscRegs++; 1655596Sgblack@eecs.umich.edu } 1665596Sgblack@eecs.umich.edu 1675596Sgblack@eecs.umich.edu /** Reads a misc. register, including any side-effects the read 1685596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1695596Sgblack@eecs.umich.edu */ 1705596Sgblack@eecs.umich.edu TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) 1715596Sgblack@eecs.umich.edu { 1725596Sgblack@eecs.umich.edu return this->cpu->readMiscReg( 1739918Ssteve.reinhardt@amd.com si->srcRegIdx(idx) - TheISA::Misc_Reg_Base, 1745596Sgblack@eecs.umich.edu this->threadNumber); 1755596Sgblack@eecs.umich.edu } 1765596Sgblack@eecs.umich.edu 1775596Sgblack@eecs.umich.edu /** Sets a misc. register, including any side-effects the write 1785596Sgblack@eecs.umich.edu * might have as defined by the architecture. 1795596Sgblack@eecs.umich.edu */ 1805596Sgblack@eecs.umich.edu void setMiscRegOperand(const StaticInst *si, int idx, 1815596Sgblack@eecs.umich.edu const MiscReg &val) 1825596Sgblack@eecs.umich.edu { 1839918Ssteve.reinhardt@amd.com int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 1847783SGiacomo.Gabrielli@arm.com setMiscReg(misc_reg, val); 1857783SGiacomo.Gabrielli@arm.com } 1867783SGiacomo.Gabrielli@arm.com 1877783SGiacomo.Gabrielli@arm.com /** Called at the commit stage to update the misc. registers. */ 1887783SGiacomo.Gabrielli@arm.com void updateMiscRegs() 1897783SGiacomo.Gabrielli@arm.com { 1907783SGiacomo.Gabrielli@arm.com // @todo: Pretty convoluted way to avoid squashing from happening when 1917783SGiacomo.Gabrielli@arm.com // using the TC during an instruction's execution (specifically for 1927783SGiacomo.Gabrielli@arm.com // instructions that have side-effects that use the TC). Fix this. 1937783SGiacomo.Gabrielli@arm.com // See cpu/o3/dyn_inst_impl.hh. 1949382SAli.Saidi@ARM.com bool no_squash_from_TC = this->thread->noSquashFromTC; 1959382SAli.Saidi@ARM.com this->thread->noSquashFromTC = true; 1967783SGiacomo.Gabrielli@arm.com 1977783SGiacomo.Gabrielli@arm.com for (int i = 0; i < _numDestMiscRegs; i++) 1987783SGiacomo.Gabrielli@arm.com this->cpu->setMiscReg( 1997783SGiacomo.Gabrielli@arm.com _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber); 2007783SGiacomo.Gabrielli@arm.com 2019382SAli.Saidi@ARM.com this->thread->noSquashFromTC = no_squash_from_TC; 2025596Sgblack@eecs.umich.edu } 2035596Sgblack@eecs.umich.edu 2047848SAli.Saidi@ARM.com void forwardOldRegs() 2057848SAli.Saidi@ARM.com { 2067848SAli.Saidi@ARM.com 2077848SAli.Saidi@ARM.com for (int idx = 0; idx < this->numDestRegs(); idx++) { 2087848SAli.Saidi@ARM.com PhysRegIndex prev_phys_reg = this->prevDestRegIdx(idx); 2099913Ssteve.reinhardt@amd.com TheISA::RegIndex original_dest_reg = 2109913Ssteve.reinhardt@amd.com this->staticInst->destRegIdx(idx); 2119913Ssteve.reinhardt@amd.com switch (regIdxToClass(original_dest_reg)) { 2129913Ssteve.reinhardt@amd.com case IntRegClass: 2139913Ssteve.reinhardt@amd.com this->setIntRegOperand(this->staticInst.get(), idx, 2149913Ssteve.reinhardt@amd.com this->cpu->readIntReg(prev_phys_reg)); 2159913Ssteve.reinhardt@amd.com break; 2169913Ssteve.reinhardt@amd.com case FloatRegClass: 2179913Ssteve.reinhardt@amd.com this->setFloatRegOperandBits(this->staticInst.get(), idx, 2189913Ssteve.reinhardt@amd.com this->cpu->readFloatRegBits(prev_phys_reg)); 2199913Ssteve.reinhardt@amd.com break; 2209920Syasuko.eckert@amd.com case CCRegClass: 2219920Syasuko.eckert@amd.com this->setCCRegOperand(this->staticInst.get(), idx, 2229920Syasuko.eckert@amd.com this->cpu->readCCReg(prev_phys_reg)); 2239920Syasuko.eckert@amd.com break; 2249913Ssteve.reinhardt@amd.com case MiscRegClass: 2259913Ssteve.reinhardt@amd.com // no need to forward misc reg values 2269913Ssteve.reinhardt@amd.com break; 2279913Ssteve.reinhardt@amd.com } 2287848SAli.Saidi@ARM.com } 2297848SAli.Saidi@ARM.com } 2305702Ssaidi@eecs.umich.edu /** Calls hardware return from error interrupt. */ 2315702Ssaidi@eecs.umich.edu Fault hwrei(); 2325596Sgblack@eecs.umich.edu /** Traps to handle specified fault. */ 2335596Sgblack@eecs.umich.edu void trap(Fault fault); 2345702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2358557Sgblack@eecs.umich.edu 2368557Sgblack@eecs.umich.edu /** Emulates a syscall. */ 2375596Sgblack@eecs.umich.edu void syscall(int64_t callnum); 2382847Sksewell@umich.edu 2395596Sgblack@eecs.umich.edu public: 2405596Sgblack@eecs.umich.edu 2415596Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 2425596Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 2435596Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 2445596Sgblack@eecs.umich.edu // renaming. We find the architectural register index by indexing 2455596Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 2465596Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 2475596Sgblack@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 2485596Sgblack@eecs.umich.edu // long as these methods don't copy the pointer into any long-term 2495596Sgblack@eecs.umich.edu // storage (which is pretty hard to imagine they would have reason 2505596Sgblack@eecs.umich.edu // to do). 2515596Sgblack@eecs.umich.edu 25210319SAndreas.Sandberg@ARM.com IntReg readIntRegOperand(const StaticInst *si, int idx) 2535596Sgblack@eecs.umich.edu { 2545596Sgblack@eecs.umich.edu return this->cpu->readIntReg(this->_srcRegIdx[idx]); 2555596Sgblack@eecs.umich.edu } 2565596Sgblack@eecs.umich.edu 2575596Sgblack@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2585596Sgblack@eecs.umich.edu { 2595596Sgblack@eecs.umich.edu return this->cpu->readFloatReg(this->_srcRegIdx[idx]); 2605596Sgblack@eecs.umich.edu } 2615596Sgblack@eecs.umich.edu 2625596Sgblack@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2635596Sgblack@eecs.umich.edu { 2645596Sgblack@eecs.umich.edu return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); 2655596Sgblack@eecs.umich.edu } 2665596Sgblack@eecs.umich.edu 26710319SAndreas.Sandberg@ARM.com CCReg readCCRegOperand(const StaticInst *si, int idx) 2689920Syasuko.eckert@amd.com { 2699920Syasuko.eckert@amd.com return this->cpu->readCCReg(this->_srcRegIdx[idx]); 2709920Syasuko.eckert@amd.com } 2719920Syasuko.eckert@amd.com 2725596Sgblack@eecs.umich.edu /** @todo: Make results into arrays so they can handle multiple dest 2735596Sgblack@eecs.umich.edu * registers. 2745596Sgblack@eecs.umich.edu */ 27510319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 2765596Sgblack@eecs.umich.edu { 2775596Sgblack@eecs.umich.edu this->cpu->setIntReg(this->_destRegIdx[idx], val); 2785596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setIntRegOperand(si, idx, val); 2795596Sgblack@eecs.umich.edu } 2805596Sgblack@eecs.umich.edu 2815596Sgblack@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2825596Sgblack@eecs.umich.edu { 2835596Sgblack@eecs.umich.edu this->cpu->setFloatReg(this->_destRegIdx[idx], val); 2845596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); 2855596Sgblack@eecs.umich.edu } 2865596Sgblack@eecs.umich.edu 2875596Sgblack@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2885596Sgblack@eecs.umich.edu FloatRegBits val) 2895596Sgblack@eecs.umich.edu { 2905596Sgblack@eecs.umich.edu this->cpu->setFloatRegBits(this->_destRegIdx[idx], val); 2915596Sgblack@eecs.umich.edu BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); 2925596Sgblack@eecs.umich.edu } 2935596Sgblack@eecs.umich.edu 29410319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 2959920Syasuko.eckert@amd.com { 2969920Syasuko.eckert@amd.com this->cpu->setCCReg(this->_destRegIdx[idx], val); 2979920Syasuko.eckert@amd.com BaseDynInst<Impl>::setCCRegOperand(si, idx, val); 2989920Syasuko.eckert@amd.com } 2999920Syasuko.eckert@amd.com 3005596Sgblack@eecs.umich.edu#if THE_ISA == MIPS_ISA 30110319SAndreas.Sandberg@ARM.com MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 3025596Sgblack@eecs.umich.edu { 3035596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 3045596Sgblack@eecs.umich.edu return 0; 3055596Sgblack@eecs.umich.edu } 3065596Sgblack@eecs.umich.edu 30710319SAndreas.Sandberg@ARM.com void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 3085596Sgblack@eecs.umich.edu { 3095596Sgblack@eecs.umich.edu panic("MIPS MT not defined for O3 CPU.\n"); 3105596Sgblack@eecs.umich.edu } 3115596Sgblack@eecs.umich.edu#endif 3125596Sgblack@eecs.umich.edu 3135596Sgblack@eecs.umich.edu public: 3145596Sgblack@eecs.umich.edu /** Calculates EA part of a memory instruction. Currently unused, 3155596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 3165596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 3175596Sgblack@eecs.umich.edu */ 3185596Sgblack@eecs.umich.edu Fault calcEA() 3195596Sgblack@eecs.umich.edu { 3205596Sgblack@eecs.umich.edu return this->staticInst->eaCompInst()->execute(this, this->traceData); 3215596Sgblack@eecs.umich.edu } 3225596Sgblack@eecs.umich.edu 3235596Sgblack@eecs.umich.edu /** Does the memory access part of a memory instruction. Currently unused, 3245596Sgblack@eecs.umich.edu * though it may be useful in the future if we want to split 3255596Sgblack@eecs.umich.edu * memory operations into EA calculation and memory access parts. 3265596Sgblack@eecs.umich.edu */ 3275596Sgblack@eecs.umich.edu Fault memAccess() 3285596Sgblack@eecs.umich.edu { 3295596Sgblack@eecs.umich.edu return this->staticInst->memAccInst()->execute(this, this->traceData); 3305596Sgblack@eecs.umich.edu } 3315596Sgblack@eecs.umich.edu}; 3325596Sgblack@eecs.umich.edu 3335596Sgblack@eecs.umich.edu#endif // __CPU_O3_ALPHA_DYN_INST_HH__ 3345596Sgblack@eecs.umich.edu 335