deriv.cc revision 3760 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include <string>
32
33#include "cpu/base.hh"
34#include "cpu/o3/sparc/cpu.hh"
35#include "cpu/o3/sparc/impl.hh"
36#include "cpu/o3/sparc/params.hh"
37#include "cpu/o3/fu_pool.hh"
38#include "sim/builder.hh"
39
40class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
41{
42  public:
43    DerivO3CPU(SparcSimpleParams *p)
44        : SparcO3CPU<SparcSimpleImpl>(p)
45    { }
46};
47
48BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
49
50    Param<int> clock;
51    Param<int> phase;
52    Param<int> numThreads;
53    Param<int> activity;
54
55#if FULL_SYSTEM
56    SimObjectParam<System *> system;
57    Param<int> cpu_id;
58    SimObjectParam<AlphaISA::ITB *> itb;
59    SimObjectParam<AlphaISA::DTB *> dtb;
60    Param<Tick> profile;
61
62    Param<bool> do_quiesce;
63    Param<bool> do_checkpoint_insts;
64    Param<bool> do_statistics_insts;
65#else
66    SimObjectVectorParam<Process *> workload;
67#endif // FULL_SYSTEM
68
69    SimObjectParam<BaseCPU *> checker;
70
71    Param<Counter> max_insts_any_thread;
72    Param<Counter> max_insts_all_threads;
73    Param<Counter> max_loads_any_thread;
74    Param<Counter> max_loads_all_threads;
75    Param<Tick> progress_interval;
76
77    Param<unsigned> cachePorts;
78
79    Param<unsigned> decodeToFetchDelay;
80    Param<unsigned> renameToFetchDelay;
81    Param<unsigned> iewToFetchDelay;
82    Param<unsigned> commitToFetchDelay;
83    Param<unsigned> fetchWidth;
84
85    Param<unsigned> renameToDecodeDelay;
86    Param<unsigned> iewToDecodeDelay;
87    Param<unsigned> commitToDecodeDelay;
88    Param<unsigned> fetchToDecodeDelay;
89    Param<unsigned> decodeWidth;
90
91    Param<unsigned> iewToRenameDelay;
92    Param<unsigned> commitToRenameDelay;
93    Param<unsigned> decodeToRenameDelay;
94    Param<unsigned> renameWidth;
95
96    Param<unsigned> commitToIEWDelay;
97    Param<unsigned> renameToIEWDelay;
98    Param<unsigned> issueToExecuteDelay;
99    Param<unsigned> dispatchWidth;
100    Param<unsigned> issueWidth;
101    Param<unsigned> wbWidth;
102    Param<unsigned> wbDepth;
103    SimObjectParam<FUPool *> fuPool;
104
105    Param<unsigned> iewToCommitDelay;
106    Param<unsigned> renameToROBDelay;
107    Param<unsigned> commitWidth;
108    Param<unsigned> squashWidth;
109    Param<Tick> trapLatency;
110
111    Param<unsigned> backComSize;
112    Param<unsigned> forwardComSize;
113
114    Param<std::string> predType;
115    Param<unsigned> localPredictorSize;
116    Param<unsigned> localCtrBits;
117    Param<unsigned> localHistoryTableSize;
118    Param<unsigned> localHistoryBits;
119    Param<unsigned> globalPredictorSize;
120    Param<unsigned> globalCtrBits;
121    Param<unsigned> globalHistoryBits;
122    Param<unsigned> choicePredictorSize;
123    Param<unsigned> choiceCtrBits;
124
125    Param<unsigned> BTBEntries;
126    Param<unsigned> BTBTagSize;
127
128    Param<unsigned> RASSize;
129
130    Param<unsigned> LQEntries;
131    Param<unsigned> SQEntries;
132    Param<unsigned> LFSTSize;
133    Param<unsigned> SSITSize;
134
135    Param<unsigned> numPhysIntRegs;
136    Param<unsigned> numPhysFloatRegs;
137    Param<unsigned> numIQEntries;
138    Param<unsigned> numROBEntries;
139
140    Param<unsigned> smtNumFetchingThreads;
141    Param<std::string>   smtFetchPolicy;
142    Param<std::string>   smtLSQPolicy;
143    Param<unsigned> smtLSQThreshold;
144    Param<std::string>   smtIQPolicy;
145    Param<unsigned> smtIQThreshold;
146    Param<std::string>   smtROBPolicy;
147    Param<unsigned> smtROBThreshold;
148    Param<std::string>   smtCommitPolicy;
149
150    Param<unsigned> instShiftAmt;
151
152    Param<bool> defer_registration;
153
154    Param<bool> function_trace;
155    Param<Tick> function_trace_start;
156
157END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
158
159BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
160
161    INIT_PARAM(clock, "clock speed"),
162    INIT_PARAM_DFLT(phase, "clock phase", 0),
163    INIT_PARAM(numThreads, "number of HW thread contexts"),
164    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
165
166#if FULL_SYSTEM
167    INIT_PARAM(system, "System object"),
168    INIT_PARAM(cpu_id, "processor ID"),
169    INIT_PARAM(itb, "Instruction translation buffer"),
170    INIT_PARAM(dtb, "Data translation buffer"),
171    INIT_PARAM(profile, ""),
172
173    INIT_PARAM(do_quiesce, ""),
174    INIT_PARAM(do_checkpoint_insts, ""),
175    INIT_PARAM(do_statistics_insts, ""),
176#else
177    INIT_PARAM(workload, "Processes to run"),
178#endif // FULL_SYSTEM
179
180    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
181
182    INIT_PARAM_DFLT(max_insts_any_thread,
183                    "Terminate when any thread reaches this inst count",
184                    0),
185    INIT_PARAM_DFLT(max_insts_all_threads,
186                    "Terminate when all threads have reached"
187                    "this inst count",
188                    0),
189    INIT_PARAM_DFLT(max_loads_any_thread,
190                    "Terminate when any thread reaches this load count",
191                    0),
192    INIT_PARAM_DFLT(max_loads_all_threads,
193                    "Terminate when all threads have reached this load"
194                    "count",
195                    0),
196    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
197
198    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
199
200    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
201    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
202    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
203               "delay"),
204    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
205    INIT_PARAM(fetchWidth, "Fetch width"),
206    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
207    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
208               "delay"),
209    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
210    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
211    INIT_PARAM(decodeWidth, "Decode width"),
212
213    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
214               "delay"),
215    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
216    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
217    INIT_PARAM(renameWidth, "Rename width"),
218
219    INIT_PARAM(commitToIEWDelay, "Commit to "
220               "Issue/Execute/Writeback delay"),
221    INIT_PARAM(renameToIEWDelay, "Rename to "
222               "Issue/Execute/Writeback delay"),
223    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
224               "to the IEW stage)"),
225    INIT_PARAM(dispatchWidth, "Dispatch width"),
226    INIT_PARAM(issueWidth, "Issue width"),
227    INIT_PARAM(wbWidth, "Writeback width"),
228    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
229    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
230
231    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
232               "delay"),
233    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
234    INIT_PARAM(commitWidth, "Commit width"),
235    INIT_PARAM(squashWidth, "Squash width"),
236    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
237
238    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
239    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
240
241    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
242    INIT_PARAM(localPredictorSize, "Size of local predictor"),
243    INIT_PARAM(localCtrBits, "Bits per counter"),
244    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
245    INIT_PARAM(localHistoryBits, "Bits for the local history"),
246    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
247    INIT_PARAM(globalCtrBits, "Bits per counter"),
248    INIT_PARAM(globalHistoryBits, "Bits of history"),
249    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
250    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
251
252    INIT_PARAM(BTBEntries, "Number of BTB entries"),
253    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
254
255    INIT_PARAM(RASSize, "RAS size"),
256
257    INIT_PARAM(LQEntries, "Number of load queue entries"),
258    INIT_PARAM(SQEntries, "Number of store queue entries"),
259    INIT_PARAM(LFSTSize, "Last fetched store table size"),
260    INIT_PARAM(SSITSize, "Store set ID table size"),
261
262    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
263    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
264               "registers"),
265    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
266    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
267
268    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
269    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
270    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
271    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
272    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
273    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
274    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
275    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
276    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
277
278    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
279    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
280
281    INIT_PARAM(function_trace, "Enable function trace"),
282    INIT_PARAM(function_trace_start, "Cycle to start function trace")
283
284END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
285
286CREATE_SIM_OBJECT(DerivO3CPU)
287{
288    DerivO3CPU *cpu;
289
290#if FULL_SYSTEM
291    // Full-system only supports a single thread for the moment.
292    int actual_num_threads = 1;
293#else
294    // In non-full-system mode, we infer the number of threads from
295    // the workload if it's not explicitly specified.
296    int actual_num_threads =
297        (numThreads.isValid() && numThreads >= workload.size()) ?
298         numThreads : workload.size();
299
300    if (workload.size() == 0) {
301        fatal("Must specify at least one workload!");
302    }
303#endif
304
305    SparcSimpleParams *params = new SparcSimpleParams;
306
307    params->clock = clock;
308
309    params->name = getInstanceName();
310    params->numberOfThreads = actual_num_threads;
311    params->activity = activity;
312
313#if FULL_SYSTEM
314    params->system = system;
315    params->cpu_id = cpu_id;
316    params->itb = itb;
317    params->dtb = dtb;
318    params->profile = profile;
319
320    params->do_quiesce = do_quiesce;
321    params->do_checkpoint_insts = do_checkpoint_insts;
322    params->do_statistics_insts = do_statistics_insts;
323#else
324    params->workload = workload;
325#endif // FULL_SYSTEM
326
327    params->checker = checker;
328
329    params->max_insts_any_thread = max_insts_any_thread;
330    params->max_insts_all_threads = max_insts_all_threads;
331    params->max_loads_any_thread = max_loads_any_thread;
332    params->max_loads_all_threads = max_loads_all_threads;
333    params->progress_interval = progress_interval;
334
335    //
336    // Caches
337    //
338    params->cachePorts = cachePorts;
339
340    params->decodeToFetchDelay = decodeToFetchDelay;
341    params->renameToFetchDelay = renameToFetchDelay;
342    params->iewToFetchDelay = iewToFetchDelay;
343    params->commitToFetchDelay = commitToFetchDelay;
344    params->fetchWidth = fetchWidth;
345
346    params->renameToDecodeDelay = renameToDecodeDelay;
347    params->iewToDecodeDelay = iewToDecodeDelay;
348    params->commitToDecodeDelay = commitToDecodeDelay;
349    params->fetchToDecodeDelay = fetchToDecodeDelay;
350    params->decodeWidth = decodeWidth;
351
352    params->iewToRenameDelay = iewToRenameDelay;
353    params->commitToRenameDelay = commitToRenameDelay;
354    params->decodeToRenameDelay = decodeToRenameDelay;
355    params->renameWidth = renameWidth;
356
357    params->commitToIEWDelay = commitToIEWDelay;
358    params->renameToIEWDelay = renameToIEWDelay;
359    params->issueToExecuteDelay = issueToExecuteDelay;
360    params->dispatchWidth = dispatchWidth;
361    params->issueWidth = issueWidth;
362    params->wbWidth = wbWidth;
363    params->wbDepth = wbDepth;
364    params->fuPool = fuPool;
365
366    params->iewToCommitDelay = iewToCommitDelay;
367    params->renameToROBDelay = renameToROBDelay;
368    params->commitWidth = commitWidth;
369    params->squashWidth = squashWidth;
370    params->trapLatency = trapLatency;
371
372    params->backComSize = backComSize;
373    params->forwardComSize = forwardComSize;
374
375    params->predType = predType;
376    params->localPredictorSize = localPredictorSize;
377    params->localCtrBits = localCtrBits;
378    params->localHistoryTableSize = localHistoryTableSize;
379    params->localHistoryBits = localHistoryBits;
380    params->globalPredictorSize = globalPredictorSize;
381    params->globalCtrBits = globalCtrBits;
382    params->globalHistoryBits = globalHistoryBits;
383    params->choicePredictorSize = choicePredictorSize;
384    params->choiceCtrBits = choiceCtrBits;
385
386    params->BTBEntries = BTBEntries;
387    params->BTBTagSize = BTBTagSize;
388
389    params->RASSize = RASSize;
390
391    params->LQEntries = LQEntries;
392    params->SQEntries = SQEntries;
393
394    params->SSITSize = SSITSize;
395    params->LFSTSize = LFSTSize;
396
397    params->numPhysIntRegs = numPhysIntRegs;
398    params->numPhysFloatRegs = numPhysFloatRegs;
399    params->numIQEntries = numIQEntries;
400    params->numROBEntries = numROBEntries;
401
402    params->smtNumFetchingThreads = smtNumFetchingThreads;
403
404    // Default smtFetchPolicy to "RoundRobin", if necessary.
405    std::string round_robin_policy = "RoundRobin";
406    std::string single_thread = "SingleThread";
407
408    if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
409        params->smtFetchPolicy = round_robin_policy;
410    else
411        params->smtFetchPolicy = smtFetchPolicy;
412
413    params->smtIQPolicy    = smtIQPolicy;
414    params->smtLSQPolicy    = smtLSQPolicy;
415    params->smtLSQThreshold = smtLSQThreshold;
416    params->smtROBPolicy   = smtROBPolicy;
417    params->smtROBThreshold = smtROBThreshold;
418    params->smtCommitPolicy = smtCommitPolicy;
419
420    params->instShiftAmt = 2;
421
422    params->deferRegistration = defer_registration;
423
424    params->functionTrace = function_trace;
425    params->functionTraceStart = function_trace_start;
426
427    cpu = new DerivO3CPU(params);
428
429    return cpu;
430}
431
432REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
433
434