decode_impl.hh revision 6221
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include "cpu/o3/decode.hh" 32#include "params/DerivO3CPU.hh" 33 34using namespace std; 35 36template<class Impl> 37DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 38 : cpu(_cpu), 39 renameToDecodeDelay(params->renameToDecodeDelay), 40 iewToDecodeDelay(params->iewToDecodeDelay), 41 commitToDecodeDelay(params->commitToDecodeDelay), 42 fetchToDecodeDelay(params->fetchToDecodeDelay), 43 decodeWidth(params->decodeWidth), 44 numThreads(params->numThreads) 45{ 46 _status = Inactive; 47 48 // Setup status, make sure stall signals are clear. 49 for (ThreadID tid = 0; tid < numThreads; ++tid) { 50 decodeStatus[tid] = Idle; 51 52 stalls[tid].rename = false; 53 stalls[tid].iew = false; 54 stalls[tid].commit = false; 55 } 56 57 // @todo: Make into a parameter 58 skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 59} 60 61template <class Impl> 62std::string 63DefaultDecode<Impl>::name() const 64{ 65 return cpu->name() + ".decode"; 66} 67 68template <class Impl> 69void 70DefaultDecode<Impl>::regStats() 71{ 72 decodeIdleCycles 73 .name(name() + ".DECODE:IdleCycles") 74 .desc("Number of cycles decode is idle") 75 .prereq(decodeIdleCycles); 76 decodeBlockedCycles 77 .name(name() + ".DECODE:BlockedCycles") 78 .desc("Number of cycles decode is blocked") 79 .prereq(decodeBlockedCycles); 80 decodeRunCycles 81 .name(name() + ".DECODE:RunCycles") 82 .desc("Number of cycles decode is running") 83 .prereq(decodeRunCycles); 84 decodeUnblockCycles 85 .name(name() + ".DECODE:UnblockCycles") 86 .desc("Number of cycles decode is unblocking") 87 .prereq(decodeUnblockCycles); 88 decodeSquashCycles 89 .name(name() + ".DECODE:SquashCycles") 90 .desc("Number of cycles decode is squashing") 91 .prereq(decodeSquashCycles); 92 decodeBranchResolved 93 .name(name() + ".DECODE:BranchResolved") 94 .desc("Number of times decode resolved a branch") 95 .prereq(decodeBranchResolved); 96 decodeBranchMispred 97 .name(name() + ".DECODE:BranchMispred") 98 .desc("Number of times decode detected a branch misprediction") 99 .prereq(decodeBranchMispred); 100 decodeControlMispred 101 .name(name() + ".DECODE:ControlMispred") 102 .desc("Number of times decode detected an instruction incorrectly" 103 " predicted as a control") 104 .prereq(decodeControlMispred); 105 decodeDecodedInsts 106 .name(name() + ".DECODE:DecodedInsts") 107 .desc("Number of instructions handled by decode") 108 .prereq(decodeDecodedInsts); 109 decodeSquashedInsts 110 .name(name() + ".DECODE:SquashedInsts") 111 .desc("Number of squashed instructions handled by decode") 112 .prereq(decodeSquashedInsts); 113} 114 115template<class Impl> 116void 117DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 118{ 119 timeBuffer = tb_ptr; 120 121 // Setup wire to write information back to fetch. 122 toFetch = timeBuffer->getWire(0); 123 124 // Create wires to get information from proper places in time buffer. 125 fromRename = timeBuffer->getWire(-renameToDecodeDelay); 126 fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 127 fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 128} 129 130template<class Impl> 131void 132DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 133{ 134 decodeQueue = dq_ptr; 135 136 // Setup wire to write information to proper place in decode queue. 137 toRename = decodeQueue->getWire(0); 138} 139 140template<class Impl> 141void 142DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 143{ 144 fetchQueue = fq_ptr; 145 146 // Setup wire to read information from fetch queue. 147 fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 148} 149 150template<class Impl> 151void 152DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 153{ 154 activeThreads = at_ptr; 155} 156 157template <class Impl> 158bool 159DefaultDecode<Impl>::drain() 160{ 161 // Decode is done draining at any time. 162 cpu->signalDrained(); 163 return true; 164} 165 166template <class Impl> 167void 168DefaultDecode<Impl>::takeOverFrom() 169{ 170 _status = Inactive; 171 172 // Be sure to reset state and clear out any old instructions. 173 for (ThreadID tid = 0; tid < numThreads; ++tid) { 174 decodeStatus[tid] = Idle; 175 176 stalls[tid].rename = false; 177 stalls[tid].iew = false; 178 stalls[tid].commit = false; 179 while (!insts[tid].empty()) 180 insts[tid].pop(); 181 while (!skidBuffer[tid].empty()) 182 skidBuffer[tid].pop(); 183 branchCount[tid] = 0; 184 } 185 wroteToTimeBuffer = false; 186} 187 188template<class Impl> 189bool 190DefaultDecode<Impl>::checkStall(ThreadID tid) const 191{ 192 bool ret_val = false; 193 194 if (stalls[tid].rename) { 195 DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 196 ret_val = true; 197 } else if (stalls[tid].iew) { 198 DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 199 ret_val = true; 200 } else if (stalls[tid].commit) { 201 DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 202 ret_val = true; 203 } 204 205 return ret_val; 206} 207 208template<class Impl> 209inline bool 210DefaultDecode<Impl>::fetchInstsValid() 211{ 212 return fromFetch->size > 0; 213} 214 215template<class Impl> 216bool 217DefaultDecode<Impl>::block(ThreadID tid) 218{ 219 DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 220 221 // Add the current inputs to the skid buffer so they can be 222 // reprocessed when this stage unblocks. 223 skidInsert(tid); 224 225 // If the decode status is blocked or unblocking then decode has not yet 226 // signalled fetch to unblock. In that case, there is no need to tell 227 // fetch to block. 228 if (decodeStatus[tid] != Blocked) { 229 // Set the status to Blocked. 230 decodeStatus[tid] = Blocked; 231 232 if (decodeStatus[tid] != Unblocking) { 233 toFetch->decodeBlock[tid] = true; 234 wroteToTimeBuffer = true; 235 } 236 237 return true; 238 } 239 240 return false; 241} 242 243template<class Impl> 244bool 245DefaultDecode<Impl>::unblock(ThreadID tid) 246{ 247 // Decode is done unblocking only if the skid buffer is empty. 248 if (skidBuffer[tid].empty()) { 249 DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 250 toFetch->decodeUnblock[tid] = true; 251 wroteToTimeBuffer = true; 252 253 decodeStatus[tid] = Running; 254 return true; 255 } 256 257 DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 258 259 return false; 260} 261 262template<class Impl> 263void 264DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 265{ 266 DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction " 267 "detected at decode.\n", tid, inst->seqNum); 268 269 // Send back mispredict information. 270 toFetch->decodeInfo[tid].branchMispredict = true; 271 toFetch->decodeInfo[tid].predIncorrect = true; 272 toFetch->decodeInfo[tid].squash = true; 273 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 274 toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC(); 275 276#if ISA_HAS_DELAY_SLOT 277 toFetch->decodeInfo[tid].nextPC = inst->readPC() + sizeof(TheISA::MachInst); 278 toFetch->decodeInfo[tid].nextNPC = inst->branchTarget(); 279 toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 280 (inst->readNextPC() + sizeof(TheISA::MachInst)); 281#else 282 toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 283 toFetch->decodeInfo[tid].nextNPC = 284 inst->branchTarget() + sizeof(TheISA::MachInst); 285 toFetch->decodeInfo[tid].branchTaken = 286 inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 287#endif 288 289 290 InstSeqNum squash_seq_num = inst->seqNum; 291 292 // Might have to tell fetch to unblock. 293 if (decodeStatus[tid] == Blocked || 294 decodeStatus[tid] == Unblocking) { 295 toFetch->decodeUnblock[tid] = 1; 296 } 297 298 // Set status to squashing. 299 decodeStatus[tid] = Squashing; 300 301 for (int i=0; i<fromFetch->size; i++) { 302 if (fromFetch->insts[i]->threadNumber == tid && 303 fromFetch->insts[i]->seqNum > squash_seq_num) { 304 fromFetch->insts[i]->setSquashed(); 305 } 306 } 307 308 // Clear the instruction list and skid buffer in case they have any 309 // insts in them. 310 while (!insts[tid].empty()) { 311 insts[tid].pop(); 312 } 313 314 while (!skidBuffer[tid].empty()) { 315 skidBuffer[tid].pop(); 316 } 317 318 // Squash instructions up until this one 319 cpu->removeInstsUntil(squash_seq_num, tid); 320} 321 322template<class Impl> 323unsigned 324DefaultDecode<Impl>::squash(ThreadID tid) 325{ 326 DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 327 328 if (decodeStatus[tid] == Blocked || 329 decodeStatus[tid] == Unblocking) { 330#if !FULL_SYSTEM 331 // In syscall emulation, we can have both a block and a squash due 332 // to a syscall in the same cycle. This would cause both signals to 333 // be high. This shouldn't happen in full system. 334 // @todo: Determine if this still happens. 335 if (toFetch->decodeBlock[tid]) { 336 toFetch->decodeBlock[tid] = 0; 337 } else { 338 toFetch->decodeUnblock[tid] = 1; 339 } 340#else 341 toFetch->decodeUnblock[tid] = 1; 342#endif 343 } 344 345 // Set status to squashing. 346 decodeStatus[tid] = Squashing; 347 348 // Go through incoming instructions from fetch and squash them. 349 unsigned squash_count = 0; 350 351 for (int i=0; i<fromFetch->size; i++) { 352 if (fromFetch->insts[i]->threadNumber == tid) { 353 fromFetch->insts[i]->setSquashed(); 354 squash_count++; 355 } 356 } 357 358 // Clear the instruction list and skid buffer in case they have any 359 // insts in them. 360 while (!insts[tid].empty()) { 361 insts[tid].pop(); 362 } 363 364 while (!skidBuffer[tid].empty()) { 365 skidBuffer[tid].pop(); 366 } 367 368 return squash_count; 369} 370 371template<class Impl> 372void 373DefaultDecode<Impl>::skidInsert(ThreadID tid) 374{ 375 DynInstPtr inst = NULL; 376 377 while (!insts[tid].empty()) { 378 inst = insts[tid].front(); 379 380 insts[tid].pop(); 381 382 assert(tid == inst->threadNumber); 383 384 DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 385 inst->seqNum, inst->readPC(), inst->threadNumber); 386 387 skidBuffer[tid].push(inst); 388 } 389 390 // @todo: Eventually need to enforce this by not letting a thread 391 // fetch past its skidbuffer 392 assert(skidBuffer[tid].size() <= skidBufferMax); 393} 394 395template<class Impl> 396bool 397DefaultDecode<Impl>::skidsEmpty() 398{ 399 list<ThreadID>::iterator threads = activeThreads->begin(); 400 list<ThreadID>::iterator end = activeThreads->end(); 401 402 while (threads != end) { 403 ThreadID tid = *threads++; 404 if (!skidBuffer[tid].empty()) 405 return false; 406 } 407 408 return true; 409} 410 411template<class Impl> 412void 413DefaultDecode<Impl>::updateStatus() 414{ 415 bool any_unblocking = false; 416 417 list<ThreadID>::iterator threads = activeThreads->begin(); 418 list<ThreadID>::iterator end = activeThreads->end(); 419 420 while (threads != end) { 421 ThreadID tid = *threads++; 422 423 if (decodeStatus[tid] == Unblocking) { 424 any_unblocking = true; 425 break; 426 } 427 } 428 429 // Decode will have activity if it's unblocking. 430 if (any_unblocking) { 431 if (_status == Inactive) { 432 _status = Active; 433 434 DPRINTF(Activity, "Activating stage.\n"); 435 436 cpu->activateStage(O3CPU::DecodeIdx); 437 } 438 } else { 439 // If it's not unblocking, then decode will not have any internal 440 // activity. Switch it to inactive. 441 if (_status == Active) { 442 _status = Inactive; 443 DPRINTF(Activity, "Deactivating stage.\n"); 444 445 cpu->deactivateStage(O3CPU::DecodeIdx); 446 } 447 } 448} 449 450template <class Impl> 451void 452DefaultDecode<Impl>::sortInsts() 453{ 454 int insts_from_fetch = fromFetch->size; 455#ifdef DEBUG 456 for (ThreadID tid = 0; tid < numThreads; tid++) 457 assert(insts[tid].empty()); 458#endif 459 for (int i = 0; i < insts_from_fetch; ++i) { 460 insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 461 } 462} 463 464template<class Impl> 465void 466DefaultDecode<Impl>::readStallSignals(ThreadID tid) 467{ 468 if (fromRename->renameBlock[tid]) { 469 stalls[tid].rename = true; 470 } 471 472 if (fromRename->renameUnblock[tid]) { 473 assert(stalls[tid].rename); 474 stalls[tid].rename = false; 475 } 476 477 if (fromIEW->iewBlock[tid]) { 478 stalls[tid].iew = true; 479 } 480 481 if (fromIEW->iewUnblock[tid]) { 482 assert(stalls[tid].iew); 483 stalls[tid].iew = false; 484 } 485 486 if (fromCommit->commitBlock[tid]) { 487 stalls[tid].commit = true; 488 } 489 490 if (fromCommit->commitUnblock[tid]) { 491 assert(stalls[tid].commit); 492 stalls[tid].commit = false; 493 } 494} 495 496template <class Impl> 497bool 498DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 499{ 500 // Check if there's a squash signal, squash if there is. 501 // Check stall signals, block if necessary. 502 // If status was blocked 503 // Check if stall conditions have passed 504 // if so then go to unblocking 505 // If status was Squashing 506 // check if squashing is not high. Switch to running this cycle. 507 508 // Update the per thread stall statuses. 509 readStallSignals(tid); 510 511 // Check squash signals from commit. 512 if (fromCommit->commitInfo[tid].squash) { 513 514 DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 515 "from commit.\n", tid); 516 517 squash(tid); 518 519 return true; 520 } 521 522 // Check ROB squash signals from commit. 523 if (fromCommit->commitInfo[tid].robSquashing) { 524 DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 525 526 // Continue to squash. 527 decodeStatus[tid] = Squashing; 528 529 return true; 530 } 531 532 if (checkStall(tid)) { 533 return block(tid); 534 } 535 536 if (decodeStatus[tid] == Blocked) { 537 DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 538 tid); 539 540 decodeStatus[tid] = Unblocking; 541 542 unblock(tid); 543 544 return true; 545 } 546 547 if (decodeStatus[tid] == Squashing) { 548 // Switch status to running if decode isn't being told to block or 549 // squash this cycle. 550 DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 551 tid); 552 553 decodeStatus[tid] = Running; 554 555 return false; 556 } 557 558 // If we've reached this point, we have not gotten any signals that 559 // cause decode to change its status. Decode remains the same as before. 560 return false; 561} 562 563template<class Impl> 564void 565DefaultDecode<Impl>::tick() 566{ 567 wroteToTimeBuffer = false; 568 569 bool status_change = false; 570 571 toRenameIndex = 0; 572 573 list<ThreadID>::iterator threads = activeThreads->begin(); 574 list<ThreadID>::iterator end = activeThreads->end(); 575 576 sortInsts(); 577 578 //Check stall and squash signals. 579 while (threads != end) { 580 ThreadID tid = *threads++; 581 582 DPRINTF(Decode,"Processing [tid:%i]\n",tid); 583 status_change = checkSignalsAndUpdate(tid) || status_change; 584 585 decode(status_change, tid); 586 } 587 588 if (status_change) { 589 updateStatus(); 590 } 591 592 if (wroteToTimeBuffer) { 593 DPRINTF(Activity, "Activity this cycle.\n"); 594 595 cpu->activityThisCycle(); 596 } 597} 598 599template<class Impl> 600void 601DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 602{ 603 // If status is Running or idle, 604 // call decodeInsts() 605 // If status is Unblocking, 606 // buffer any instructions coming from fetch 607 // continue trying to empty skid buffer 608 // check if stall conditions have passed 609 610 if (decodeStatus[tid] == Blocked) { 611 ++decodeBlockedCycles; 612 } else if (decodeStatus[tid] == Squashing) { 613 ++decodeSquashCycles; 614 } 615 616 // Decode should try to decode as many instructions as its bandwidth 617 // will allow, as long as it is not currently blocked. 618 if (decodeStatus[tid] == Running || 619 decodeStatus[tid] == Idle) { 620 DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 621 "stage.\n",tid); 622 623 decodeInsts(tid); 624 } else if (decodeStatus[tid] == Unblocking) { 625 // Make sure that the skid buffer has something in it if the 626 // status is unblocking. 627 assert(!skidsEmpty()); 628 629 // If the status was unblocking, then instructions from the skid 630 // buffer were used. Remove those instructions and handle 631 // the rest of unblocking. 632 decodeInsts(tid); 633 634 if (fetchInstsValid()) { 635 // Add the current inputs to the skid buffer so they can be 636 // reprocessed when this stage unblocks. 637 skidInsert(tid); 638 } 639 640 status_change = unblock(tid) || status_change; 641 } 642} 643 644template <class Impl> 645void 646DefaultDecode<Impl>::decodeInsts(ThreadID tid) 647{ 648 // Instructions can come either from the skid buffer or the list of 649 // instructions coming from fetch, depending on decode's status. 650 int insts_available = decodeStatus[tid] == Unblocking ? 651 skidBuffer[tid].size() : insts[tid].size(); 652 653 if (insts_available == 0) { 654 DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 655 " early.\n",tid); 656 // Should I change the status to idle? 657 ++decodeIdleCycles; 658 return; 659 } else if (decodeStatus[tid] == Unblocking) { 660 DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 661 "buffer.\n",tid); 662 ++decodeUnblockCycles; 663 } else if (decodeStatus[tid] == Running) { 664 ++decodeRunCycles; 665 } 666 667 DynInstPtr inst; 668 669 std::queue<DynInstPtr> 670 &insts_to_decode = decodeStatus[tid] == Unblocking ? 671 skidBuffer[tid] : insts[tid]; 672 673 DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 674 675 while (insts_available > 0 && toRenameIndex < decodeWidth) { 676 assert(!insts_to_decode.empty()); 677 678 inst = insts_to_decode.front(); 679 680 insts_to_decode.pop(); 681 682 DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 683 "PC %#x\n", 684 tid, inst->seqNum, inst->readPC()); 685 686 if (inst->isSquashed()) { 687 DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 688 "squashed, skipping.\n", 689 tid, inst->seqNum, inst->readPC()); 690 691 ++decodeSquashedInsts; 692 693 --insts_available; 694 695 continue; 696 } 697 698 // Also check if instructions have no source registers. Mark 699 // them as ready to issue at any time. Not sure if this check 700 // should exist here or at a later stage; however it doesn't matter 701 // too much for function correctness. 702 if (inst->numSrcRegs() == 0) { 703 inst->setCanIssue(); 704 } 705 706 // This current instruction is valid, so add it into the decode 707 // queue. The next instruction may not be valid, so check to 708 // see if branches were predicted correctly. 709 toRename->insts[toRenameIndex] = inst; 710 711 ++(toRename->size); 712 ++toRenameIndex; 713 ++decodeDecodedInsts; 714 --insts_available; 715 716 // Ensure that if it was predicted as a branch, it really is a 717 // branch. 718 if (inst->readPredTaken() && !inst->isControl()) { 719 DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 720 inst->readPredPC(), inst->readNextPC() + 4); 721 722 panic("Instruction predicted as a branch!"); 723 724 ++decodeControlMispred; 725 726 // Might want to set some sort of boolean and just do 727 // a check at the end 728 squash(inst, inst->threadNumber); 729 730 break; 731 } 732 733 // Go ahead and compute any PC-relative branches. 734 if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 735 ++decodeBranchResolved; 736 737 if (inst->branchTarget() != inst->readPredPC()) { 738 ++decodeBranchMispred; 739 740 // Might want to set some sort of boolean and just do 741 // a check at the end 742 squash(inst, inst->threadNumber); 743 Addr target = inst->branchTarget(); 744 745#if ISA_HAS_DELAY_SLOT 746 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n", 747 inst->seqNum, inst->readPC() + sizeof(TheISA::MachInst), target); 748 749 //The micro pc after an instruction level branch should be 0 750 inst->setPredTarg(inst->readPC() + sizeof(TheISA::MachInst), target, 0); 751#else 752 DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n", 753 inst->seqNum, target, target + sizeof(TheISA::MachInst)); 754 //The micro pc after an instruction level branch should be 0 755 inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0); 756#endif 757 break; 758 } 759 } 760 } 761 762 // If we didn't process all instructions, then we will need to block 763 // and put all those instructions into the skid buffer. 764 if (!insts_to_decode.empty()) { 765 block(tid); 766 } 767 768 // Record that decode has written to the time buffer for activity 769 // tracking. 770 if (toRenameIndex) { 771 wroteToTimeBuffer = true; 772 } 773} 774