decode_impl.hh revision 6658
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 316658Snate@binkert.org#include "config/the_isa.hh" 321717SN/A#include "cpu/o3/decode.hh" 336221Snate@binkert.org#include "params/DerivO3CPU.hh" 341060SN/A 356221Snate@binkert.orgusing namespace std; 365529Snate@binkert.org 371060SN/Atemplate<class Impl> 385529Snate@binkert.orgDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 394329Sktlim@umich.edu : cpu(_cpu), 404329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 412292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 422292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 432292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 442292SN/A decodeWidth(params->decodeWidth), 455529Snate@binkert.org numThreads(params->numThreads) 461060SN/A{ 472292SN/A _status = Inactive; 482292SN/A 492348SN/A // Setup status, make sure stall signals are clear. 506221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 516221Snate@binkert.org decodeStatus[tid] = Idle; 522292SN/A 536221Snate@binkert.org stalls[tid].rename = false; 546221Snate@binkert.org stalls[tid].iew = false; 556221Snate@binkert.org stalls[tid].commit = false; 562292SN/A } 572292SN/A 582292SN/A // @todo: Make into a parameter 592292SN/A skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth; 602292SN/A} 612292SN/A 622292SN/Atemplate <class Impl> 632292SN/Astd::string 642292SN/ADefaultDecode<Impl>::name() const 652292SN/A{ 662292SN/A return cpu->name() + ".decode"; 671060SN/A} 681060SN/A 691062SN/Atemplate <class Impl> 701062SN/Avoid 712292SN/ADefaultDecode<Impl>::regStats() 721062SN/A{ 731062SN/A decodeIdleCycles 742307SN/A .name(name() + ".DECODE:IdleCycles") 751062SN/A .desc("Number of cycles decode is idle") 761062SN/A .prereq(decodeIdleCycles); 771062SN/A decodeBlockedCycles 782307SN/A .name(name() + ".DECODE:BlockedCycles") 791062SN/A .desc("Number of cycles decode is blocked") 801062SN/A .prereq(decodeBlockedCycles); 812292SN/A decodeRunCycles 822307SN/A .name(name() + ".DECODE:RunCycles") 832292SN/A .desc("Number of cycles decode is running") 842292SN/A .prereq(decodeRunCycles); 851062SN/A decodeUnblockCycles 862307SN/A .name(name() + ".DECODE:UnblockCycles") 871062SN/A .desc("Number of cycles decode is unblocking") 881062SN/A .prereq(decodeUnblockCycles); 891062SN/A decodeSquashCycles 902307SN/A .name(name() + ".DECODE:SquashCycles") 911062SN/A .desc("Number of cycles decode is squashing") 921062SN/A .prereq(decodeSquashCycles); 932307SN/A decodeBranchResolved 942307SN/A .name(name() + ".DECODE:BranchResolved") 952307SN/A .desc("Number of times decode resolved a branch") 962307SN/A .prereq(decodeBranchResolved); 971062SN/A decodeBranchMispred 982307SN/A .name(name() + ".DECODE:BranchMispred") 991062SN/A .desc("Number of times decode detected a branch misprediction") 1001062SN/A .prereq(decodeBranchMispred); 1011062SN/A decodeControlMispred 1022307SN/A .name(name() + ".DECODE:ControlMispred") 1031062SN/A .desc("Number of times decode detected an instruction incorrectly" 1041062SN/A " predicted as a control") 1051062SN/A .prereq(decodeControlMispred); 1061062SN/A decodeDecodedInsts 1072307SN/A .name(name() + ".DECODE:DecodedInsts") 1081062SN/A .desc("Number of instructions handled by decode") 1091062SN/A .prereq(decodeDecodedInsts); 1101062SN/A decodeSquashedInsts 1112307SN/A .name(name() + ".DECODE:SquashedInsts") 1121062SN/A .desc("Number of squashed instructions handled by decode") 1131062SN/A .prereq(decodeSquashedInsts); 1141062SN/A} 1151062SN/A 1161060SN/Atemplate<class Impl> 1171060SN/Avoid 1182292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1191060SN/A{ 1201060SN/A timeBuffer = tb_ptr; 1211060SN/A 1221060SN/A // Setup wire to write information back to fetch. 1231060SN/A toFetch = timeBuffer->getWire(0); 1241060SN/A 1251060SN/A // Create wires to get information from proper places in time buffer. 1261060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1271060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1281060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1291060SN/A} 1301060SN/A 1311060SN/Atemplate<class Impl> 1321060SN/Avoid 1332292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1341060SN/A{ 1351060SN/A decodeQueue = dq_ptr; 1361060SN/A 1371060SN/A // Setup wire to write information to proper place in decode queue. 1381060SN/A toRename = decodeQueue->getWire(0); 1391060SN/A} 1401060SN/A 1411060SN/Atemplate<class Impl> 1421060SN/Avoid 1432292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1441060SN/A{ 1451060SN/A fetchQueue = fq_ptr; 1461060SN/A 1471060SN/A // Setup wire to read information from fetch queue. 1481060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1491060SN/A} 1501060SN/A 1511060SN/Atemplate<class Impl> 1522292SN/Avoid 1536221Snate@binkert.orgDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 1542292SN/A{ 1552292SN/A activeThreads = at_ptr; 1562292SN/A} 1572292SN/A 1582307SN/Atemplate <class Impl> 1592863Sktlim@umich.edubool 1602843Sktlim@umich.eduDefaultDecode<Impl>::drain() 1612307SN/A{ 1622843Sktlim@umich.edu // Decode is done draining at any time. 1632843Sktlim@umich.edu cpu->signalDrained(); 1642863Sktlim@umich.edu return true; 1652307SN/A} 1662307SN/A 1672307SN/Atemplate <class Impl> 1682307SN/Avoid 1692307SN/ADefaultDecode<Impl>::takeOverFrom() 1702307SN/A{ 1712307SN/A _status = Inactive; 1722307SN/A 1732348SN/A // Be sure to reset state and clear out any old instructions. 1746221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 1756221Snate@binkert.org decodeStatus[tid] = Idle; 1762307SN/A 1776221Snate@binkert.org stalls[tid].rename = false; 1786221Snate@binkert.org stalls[tid].iew = false; 1796221Snate@binkert.org stalls[tid].commit = false; 1806221Snate@binkert.org while (!insts[tid].empty()) 1816221Snate@binkert.org insts[tid].pop(); 1826221Snate@binkert.org while (!skidBuffer[tid].empty()) 1836221Snate@binkert.org skidBuffer[tid].pop(); 1846221Snate@binkert.org branchCount[tid] = 0; 1852307SN/A } 1862307SN/A wroteToTimeBuffer = false; 1872307SN/A} 1882307SN/A 1892292SN/Atemplate<class Impl> 1902292SN/Abool 1916221Snate@binkert.orgDefaultDecode<Impl>::checkStall(ThreadID tid) const 1922292SN/A{ 1932292SN/A bool ret_val = false; 1942292SN/A 1952292SN/A if (stalls[tid].rename) { 1962292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 1972292SN/A ret_val = true; 1982292SN/A } else if (stalls[tid].iew) { 1992292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid); 2002292SN/A ret_val = true; 2012292SN/A } else if (stalls[tid].commit) { 2022292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid); 2032292SN/A ret_val = true; 2042292SN/A } 2052292SN/A 2062292SN/A return ret_val; 2072292SN/A} 2082292SN/A 2092292SN/Atemplate<class Impl> 2101681SN/Ainline bool 2112292SN/ADefaultDecode<Impl>::fetchInstsValid() 2121681SN/A{ 2131681SN/A return fromFetch->size > 0; 2141681SN/A} 2151681SN/A 2161681SN/Atemplate<class Impl> 2172292SN/Abool 2186221Snate@binkert.orgDefaultDecode<Impl>::block(ThreadID tid) 2191060SN/A{ 2202292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2211060SN/A 2221060SN/A // Add the current inputs to the skid buffer so they can be 2231060SN/A // reprocessed when this stage unblocks. 2242292SN/A skidInsert(tid); 2251060SN/A 2262348SN/A // If the decode status is blocked or unblocking then decode has not yet 2272348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2282348SN/A // fetch to block. 2292292SN/A if (decodeStatus[tid] != Blocked) { 2302292SN/A // Set the status to Blocked. 2312292SN/A decodeStatus[tid] = Blocked; 2322348SN/A 2332348SN/A if (decodeStatus[tid] != Unblocking) { 2342348SN/A toFetch->decodeBlock[tid] = true; 2352348SN/A wroteToTimeBuffer = true; 2362348SN/A } 2372348SN/A 2382292SN/A return true; 2392292SN/A } 2402292SN/A 2412292SN/A return false; 2421060SN/A} 2431060SN/A 2441060SN/Atemplate<class Impl> 2452292SN/Abool 2466221Snate@binkert.orgDefaultDecode<Impl>::unblock(ThreadID tid) 2471060SN/A{ 2482292SN/A // Decode is done unblocking only if the skid buffer is empty. 2492292SN/A if (skidBuffer[tid].empty()) { 2502292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2512292SN/A toFetch->decodeUnblock[tid] = true; 2522292SN/A wroteToTimeBuffer = true; 2531060SN/A 2542292SN/A decodeStatus[tid] = Running; 2552292SN/A return true; 2561060SN/A } 2571681SN/A 2582329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2592329SN/A 2602292SN/A return false; 2611060SN/A} 2621060SN/A 2631060SN/Atemplate<class Impl> 2641060SN/Avoid 2656221Snate@binkert.orgDefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 2661060SN/A{ 2676036Sksewell@umich.edu DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction " 2686036Sksewell@umich.edu "detected at decode.\n", tid, inst->seqNum); 2692292SN/A 2702348SN/A // Send back mispredict information. 2712292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2722935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2736036Sksewell@umich.edu toFetch->decodeInfo[tid].squash = true; 2742292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 2754636Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].nextMicroPC = inst->readMicroPC(); 2766036Sksewell@umich.edu 2773093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 2786036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->readPC() + sizeof(TheISA::MachInst); 2796036Sksewell@umich.edu toFetch->decodeInfo[tid].nextNPC = inst->branchTarget(); 2802935Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != 2812935Sksewell@umich.edu (inst->readNextPC() + sizeof(TheISA::MachInst)); 2823093Sksewell@umich.edu#else 2836036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 2846036Sksewell@umich.edu toFetch->decodeInfo[tid].nextNPC = 2856036Sksewell@umich.edu inst->branchTarget() + sizeof(TheISA::MachInst); 2863093Sksewell@umich.edu toFetch->decodeInfo[tid].branchTaken = 2873093Sksewell@umich.edu inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); 2884632Sgblack@eecs.umich.edu#endif 2893093Sksewell@umich.edu 2906036Sksewell@umich.edu 2913093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 2922935Sksewell@umich.edu 2932348SN/A // Might have to tell fetch to unblock. 2942292SN/A if (decodeStatus[tid] == Blocked || 2952292SN/A decodeStatus[tid] == Unblocking) { 2962292SN/A toFetch->decodeUnblock[tid] = 1; 2972292SN/A } 2982292SN/A 2991060SN/A // Set status to squashing. 3002292SN/A decodeStatus[tid] = Squashing; 3011060SN/A 3022292SN/A for (int i=0; i<fromFetch->size; i++) { 3032292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3042935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3052731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3062292SN/A } 3072292SN/A } 3082292SN/A 3092348SN/A // Clear the instruction list and skid buffer in case they have any 3102348SN/A // insts in them. 3112292SN/A while (!insts[tid].empty()) { 3122292SN/A insts[tid].pop(); 3132292SN/A } 3141060SN/A 3152292SN/A while (!skidBuffer[tid].empty()) { 3162292SN/A skidBuffer[tid].pop(); 3172292SN/A } 3182292SN/A 3192292SN/A // Squash instructions up until this one 3202935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3212292SN/A} 3222292SN/A 3232292SN/Atemplate<class Impl> 3242292SN/Aunsigned 3256221Snate@binkert.orgDefaultDecode<Impl>::squash(ThreadID tid) 3262292SN/A{ 3272292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3282292SN/A 3292292SN/A if (decodeStatus[tid] == Blocked || 3302292SN/A decodeStatus[tid] == Unblocking) { 3312292SN/A#if !FULL_SYSTEM 3322292SN/A // In syscall emulation, we can have both a block and a squash due 3332292SN/A // to a syscall in the same cycle. This would cause both signals to 3342292SN/A // be high. This shouldn't happen in full system. 3352329SN/A // @todo: Determine if this still happens. 3362292SN/A if (toFetch->decodeBlock[tid]) { 3372292SN/A toFetch->decodeBlock[tid] = 0; 3382292SN/A } else { 3392292SN/A toFetch->decodeUnblock[tid] = 1; 3402292SN/A } 3412292SN/A#else 3422292SN/A toFetch->decodeUnblock[tid] = 1; 3432292SN/A#endif 3442292SN/A } 3452292SN/A 3462292SN/A // Set status to squashing. 3472292SN/A decodeStatus[tid] = Squashing; 3482292SN/A 3492292SN/A // Go through incoming instructions from fetch and squash them. 3502292SN/A unsigned squash_count = 0; 3512292SN/A 3522292SN/A for (int i=0; i<fromFetch->size; i++) { 3532292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3542731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3552292SN/A squash_count++; 3562292SN/A } 3572292SN/A } 3582292SN/A 3592348SN/A // Clear the instruction list and skid buffer in case they have any 3602348SN/A // insts in them. 3612292SN/A while (!insts[tid].empty()) { 3622292SN/A insts[tid].pop(); 3632292SN/A } 3642292SN/A 3652292SN/A while (!skidBuffer[tid].empty()) { 3662292SN/A skidBuffer[tid].pop(); 3672292SN/A } 3682292SN/A 3692292SN/A return squash_count; 3702292SN/A} 3712292SN/A 3722292SN/Atemplate<class Impl> 3732292SN/Avoid 3746221Snate@binkert.orgDefaultDecode<Impl>::skidInsert(ThreadID tid) 3752292SN/A{ 3762292SN/A DynInstPtr inst = NULL; 3772292SN/A 3782292SN/A while (!insts[tid].empty()) { 3792292SN/A inst = insts[tid].front(); 3802292SN/A 3812292SN/A insts[tid].pop(); 3822292SN/A 3832292SN/A assert(tid == inst->threadNumber); 3842292SN/A 3852292SN/A DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n", 3862292SN/A inst->seqNum, inst->readPC(), inst->threadNumber); 3872292SN/A 3882292SN/A skidBuffer[tid].push(inst); 3892292SN/A } 3902292SN/A 3912329SN/A // @todo: Eventually need to enforce this by not letting a thread 3922292SN/A // fetch past its skidbuffer 3932292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 3942292SN/A} 3952292SN/A 3962292SN/Atemplate<class Impl> 3972292SN/Abool 3982292SN/ADefaultDecode<Impl>::skidsEmpty() 3992292SN/A{ 4006221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4016221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4022292SN/A 4033867Sbinkertn@umich.edu while (threads != end) { 4046221Snate@binkert.org ThreadID tid = *threads++; 4053867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4062292SN/A return false; 4072292SN/A } 4082292SN/A 4092292SN/A return true; 4102292SN/A} 4112292SN/A 4122292SN/Atemplate<class Impl> 4132292SN/Avoid 4142292SN/ADefaultDecode<Impl>::updateStatus() 4152292SN/A{ 4162292SN/A bool any_unblocking = false; 4172292SN/A 4186221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4196221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4202292SN/A 4213867Sbinkertn@umich.edu while (threads != end) { 4226221Snate@binkert.org ThreadID tid = *threads++; 4232292SN/A 4242292SN/A if (decodeStatus[tid] == Unblocking) { 4252292SN/A any_unblocking = true; 4262292SN/A break; 4272292SN/A } 4282292SN/A } 4292292SN/A 4302292SN/A // Decode will have activity if it's unblocking. 4312292SN/A if (any_unblocking) { 4322292SN/A if (_status == Inactive) { 4332292SN/A _status = Active; 4342292SN/A 4352292SN/A DPRINTF(Activity, "Activating stage.\n"); 4362292SN/A 4372733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4382292SN/A } 4392292SN/A } else { 4402292SN/A // If it's not unblocking, then decode will not have any internal 4412292SN/A // activity. Switch it to inactive. 4422292SN/A if (_status == Active) { 4432292SN/A _status = Inactive; 4442292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4452292SN/A 4462733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4472292SN/A } 4482292SN/A } 4492292SN/A} 4502292SN/A 4512292SN/Atemplate <class Impl> 4522292SN/Avoid 4532292SN/ADefaultDecode<Impl>::sortInsts() 4542292SN/A{ 4552292SN/A int insts_from_fetch = fromFetch->size; 4562329SN/A#ifdef DEBUG 4576221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 4586221Snate@binkert.org assert(insts[tid].empty()); 4592329SN/A#endif 4602292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4612292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4621060SN/A } 4631060SN/A} 4641060SN/A 4651060SN/Atemplate<class Impl> 4661060SN/Avoid 4676221Snate@binkert.orgDefaultDecode<Impl>::readStallSignals(ThreadID tid) 4681060SN/A{ 4692292SN/A if (fromRename->renameBlock[tid]) { 4702292SN/A stalls[tid].rename = true; 4712292SN/A } 4721060SN/A 4732292SN/A if (fromRename->renameUnblock[tid]) { 4742292SN/A assert(stalls[tid].rename); 4752292SN/A stalls[tid].rename = false; 4762292SN/A } 4771060SN/A 4782292SN/A if (fromIEW->iewBlock[tid]) { 4792292SN/A stalls[tid].iew = true; 4802292SN/A } 4811062SN/A 4822292SN/A if (fromIEW->iewUnblock[tid]) { 4832292SN/A assert(stalls[tid].iew); 4842292SN/A stalls[tid].iew = false; 4852292SN/A } 4861061SN/A 4872292SN/A if (fromCommit->commitBlock[tid]) { 4882292SN/A stalls[tid].commit = true; 4892292SN/A } 4901062SN/A 4912292SN/A if (fromCommit->commitUnblock[tid]) { 4922292SN/A assert(stalls[tid].commit); 4932292SN/A stalls[tid].commit = false; 4942292SN/A } 4952292SN/A} 4961060SN/A 4972292SN/Atemplate <class Impl> 4982292SN/Abool 4996221Snate@binkert.orgDefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 5002292SN/A{ 5012292SN/A // Check if there's a squash signal, squash if there is. 5022292SN/A // Check stall signals, block if necessary. 5032292SN/A // If status was blocked 5042292SN/A // Check if stall conditions have passed 5052292SN/A // if so then go to unblocking 5062292SN/A // If status was Squashing 5072292SN/A // check if squashing is not high. Switch to running this cycle. 5081060SN/A 5092292SN/A // Update the per thread stall statuses. 5102292SN/A readStallSignals(tid); 5111060SN/A 5122292SN/A // Check squash signals from commit. 5132292SN/A if (fromCommit->commitInfo[tid].squash) { 5141681SN/A 5152292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5162292SN/A "from commit.\n", tid); 5172292SN/A 5182292SN/A squash(tid); 5192292SN/A 5202292SN/A return true; 5212292SN/A } 5222292SN/A 5232292SN/A // Check ROB squash signals from commit. 5242292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 5252703Sktlim@umich.edu DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid); 5262292SN/A 5272292SN/A // Continue to squash. 5282292SN/A decodeStatus[tid] = Squashing; 5292292SN/A 5302292SN/A return true; 5312292SN/A } 5322292SN/A 5332292SN/A if (checkStall(tid)) { 5342292SN/A return block(tid); 5352292SN/A } 5362292SN/A 5372292SN/A if (decodeStatus[tid] == Blocked) { 5382292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5392292SN/A tid); 5402292SN/A 5412292SN/A decodeStatus[tid] = Unblocking; 5422292SN/A 5432292SN/A unblock(tid); 5442292SN/A 5452292SN/A return true; 5462292SN/A } 5472292SN/A 5482292SN/A if (decodeStatus[tid] == Squashing) { 5492292SN/A // Switch status to running if decode isn't being told to block or 5502292SN/A // squash this cycle. 5512292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5522292SN/A tid); 5532292SN/A 5542292SN/A decodeStatus[tid] = Running; 5552292SN/A 5562292SN/A return false; 5572292SN/A } 5582292SN/A 5592292SN/A // If we've reached this point, we have not gotten any signals that 5602292SN/A // cause decode to change its status. Decode remains the same as before. 5612292SN/A return false; 5622292SN/A} 5632292SN/A 5642292SN/Atemplate<class Impl> 5652292SN/Avoid 5662292SN/ADefaultDecode<Impl>::tick() 5672292SN/A{ 5682292SN/A wroteToTimeBuffer = false; 5692292SN/A 5702292SN/A bool status_change = false; 5712292SN/A 5722292SN/A toRenameIndex = 0; 5732292SN/A 5746221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5756221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5762292SN/A 5772292SN/A sortInsts(); 5782292SN/A 5792292SN/A //Check stall and squash signals. 5803867Sbinkertn@umich.edu while (threads != end) { 5816221Snate@binkert.org ThreadID tid = *threads++; 5822292SN/A 5832292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 5842292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 5852292SN/A 5862292SN/A decode(status_change, tid); 5872292SN/A } 5882292SN/A 5892292SN/A if (status_change) { 5902292SN/A updateStatus(); 5912292SN/A } 5922292SN/A 5932292SN/A if (wroteToTimeBuffer) { 5942292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 5952292SN/A 5962292SN/A cpu->activityThisCycle(); 5971060SN/A } 5981060SN/A} 5991060SN/A 6001060SN/Atemplate<class Impl> 6011060SN/Avoid 6026221Snate@binkert.orgDefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 6031060SN/A{ 6042292SN/A // If status is Running or idle, 6052292SN/A // call decodeInsts() 6062292SN/A // If status is Unblocking, 6072292SN/A // buffer any instructions coming from fetch 6082292SN/A // continue trying to empty skid buffer 6092292SN/A // check if stall conditions have passed 6102292SN/A 6112292SN/A if (decodeStatus[tid] == Blocked) { 6122292SN/A ++decodeBlockedCycles; 6132292SN/A } else if (decodeStatus[tid] == Squashing) { 6142292SN/A ++decodeSquashCycles; 6151060SN/A } 6161060SN/A 6172292SN/A // Decode should try to decode as many instructions as its bandwidth 6182292SN/A // will allow, as long as it is not currently blocked. 6192292SN/A if (decodeStatus[tid] == Running || 6202292SN/A decodeStatus[tid] == Idle) { 6212935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6222292SN/A "stage.\n",tid); 6232292SN/A 6242292SN/A decodeInsts(tid); 6252292SN/A } else if (decodeStatus[tid] == Unblocking) { 6262292SN/A // Make sure that the skid buffer has something in it if the 6272292SN/A // status is unblocking. 6282292SN/A assert(!skidsEmpty()); 6292292SN/A 6302292SN/A // If the status was unblocking, then instructions from the skid 6312292SN/A // buffer were used. Remove those instructions and handle 6322292SN/A // the rest of unblocking. 6332292SN/A decodeInsts(tid); 6342292SN/A 6352292SN/A if (fetchInstsValid()) { 6362292SN/A // Add the current inputs to the skid buffer so they can be 6372292SN/A // reprocessed when this stage unblocks. 6382292SN/A skidInsert(tid); 6392292SN/A } 6402292SN/A 6412292SN/A status_change = unblock(tid) || status_change; 6421060SN/A } 6432292SN/A} 6441060SN/A 6452292SN/Atemplate <class Impl> 6462292SN/Avoid 6476221Snate@binkert.orgDefaultDecode<Impl>::decodeInsts(ThreadID tid) 6482292SN/A{ 6492292SN/A // Instructions can come either from the skid buffer or the list of 6502292SN/A // instructions coming from fetch, depending on decode's status. 6512292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6522292SN/A skidBuffer[tid].size() : insts[tid].size(); 6532292SN/A 6542292SN/A if (insts_available == 0) { 6552292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6562292SN/A " early.\n",tid); 6571060SN/A // Should I change the status to idle? 6581062SN/A ++decodeIdleCycles; 6591060SN/A return; 6602292SN/A } else if (decodeStatus[tid] == Unblocking) { 6612292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6622292SN/A "buffer.\n",tid); 6632292SN/A ++decodeUnblockCycles; 6642292SN/A } else if (decodeStatus[tid] == Running) { 6652292SN/A ++decodeRunCycles; 6661060SN/A } 6671060SN/A 6681061SN/A DynInstPtr inst; 6691061SN/A 6702292SN/A std::queue<DynInstPtr> 6712292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6722292SN/A skidBuffer[tid] : insts[tid]; 6731061SN/A 6742292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 6751060SN/A 6762292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6772292SN/A assert(!insts_to_decode.empty()); 6781060SN/A 6792292SN/A inst = insts_to_decode.front(); 6801062SN/A 6812292SN/A insts_to_decode.pop(); 6821061SN/A 6832292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 6842292SN/A "PC %#x\n", 6852292SN/A tid, inst->seqNum, inst->readPC()); 6861061SN/A 6871061SN/A if (inst->isSquashed()) { 6882292SN/A DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is " 6891061SN/A "squashed, skipping.\n", 6902292SN/A tid, inst->seqNum, inst->readPC()); 6911061SN/A 6921062SN/A ++decodeSquashedInsts; 6931062SN/A 6941061SN/A --insts_available; 6951061SN/A 6961061SN/A continue; 6971061SN/A } 6981060SN/A 6991681SN/A // Also check if instructions have no source registers. Mark 7001681SN/A // them as ready to issue at any time. Not sure if this check 7011681SN/A // should exist here or at a later stage; however it doesn't matter 7021681SN/A // too much for function correctness. 7031681SN/A if (inst->numSrcRegs() == 0) { 7041681SN/A inst->setCanIssue(); 7051681SN/A } 7061681SN/A 7071060SN/A // This current instruction is valid, so add it into the decode 7081060SN/A // queue. The next instruction may not be valid, so check to 7091060SN/A // see if branches were predicted correctly. 7102292SN/A toRename->insts[toRenameIndex] = inst; 7111061SN/A 7121061SN/A ++(toRename->size); 7132292SN/A ++toRenameIndex; 7142292SN/A ++decodeDecodedInsts; 7152292SN/A --insts_available; 7161060SN/A 7171060SN/A // Ensure that if it was predicted as a branch, it really is a 7181061SN/A // branch. 7193796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7203967Sgblack@eecs.umich.edu DPRINTF(Decode, "PredPC : %#x != NextPC: %#x\n", 7213967Sgblack@eecs.umich.edu inst->readPredPC(), inst->readNextPC() + 4); 7222935Sksewell@umich.edu 7231060SN/A panic("Instruction predicted as a branch!"); 7241060SN/A 7251062SN/A ++decodeControlMispred; 7262292SN/A 7271060SN/A // Might want to set some sort of boolean and just do 7281060SN/A // a check at the end 7292292SN/A squash(inst, inst->threadNumber); 7302292SN/A 7311060SN/A break; 7321060SN/A } 7331060SN/A 7341062SN/A // Go ahead and compute any PC-relative branches. 7351063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7362307SN/A ++decodeBranchResolved; 7371062SN/A 7383796Sgblack@eecs.umich.edu if (inst->branchTarget() != inst->readPredPC()) { 7391062SN/A ++decodeBranchMispred; 7402292SN/A 7411060SN/A // Might want to set some sort of boolean and just do 7421060SN/A // a check at the end 7432292SN/A squash(inst, inst->threadNumber); 7443796Sgblack@eecs.umich.edu Addr target = inst->branchTarget(); 7456036Sksewell@umich.edu 7466036Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 7476036Sksewell@umich.edu DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n", 7486036Sksewell@umich.edu inst->seqNum, inst->readPC() + sizeof(TheISA::MachInst), target); 7496036Sksewell@umich.edu 7506036Sksewell@umich.edu //The micro pc after an instruction level branch should be 0 7516036Sksewell@umich.edu inst->setPredTarg(inst->readPC() + sizeof(TheISA::MachInst), target, 0); 7526036Sksewell@umich.edu#else 7536036Sksewell@umich.edu DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %#x PredNextPC: %#x\n", 7546036Sksewell@umich.edu inst->seqNum, target, target + sizeof(TheISA::MachInst)); 7554636Sgblack@eecs.umich.edu //The micro pc after an instruction level branch should be 0 7564636Sgblack@eecs.umich.edu inst->setPredTarg(target, target + sizeof(TheISA::MachInst), 0); 7576036Sksewell@umich.edu#endif 7582935Sksewell@umich.edu break; 7592935Sksewell@umich.edu } 7602935Sksewell@umich.edu } 7611060SN/A } 7621061SN/A 7632292SN/A // If we didn't process all instructions, then we will need to block 7642292SN/A // and put all those instructions into the skid buffer. 7652292SN/A if (!insts_to_decode.empty()) { 7662292SN/A block(tid); 7672292SN/A } 7682292SN/A 7692292SN/A // Record that decode has written to the time buffer for activity 7702292SN/A // tracking. 7712292SN/A if (toRenameIndex) { 7722292SN/A wroteToTimeBuffer = true; 7732292SN/A } 7741060SN/A} 775