decode_impl.hh revision 2863
11689SN/A/*
22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
311717SN/A#include "cpu/o3/decode.hh"
321060SN/A
332292SN/Ausing namespace std;
342292SN/A
351060SN/Atemplate<class Impl>
362292SN/ADefaultDecode<Impl>::DefaultDecode(Params *params)
372292SN/A    : renameToDecodeDelay(params->renameToDecodeDelay),
382292SN/A      iewToDecodeDelay(params->iewToDecodeDelay),
392292SN/A      commitToDecodeDelay(params->commitToDecodeDelay),
402292SN/A      fetchToDecodeDelay(params->fetchToDecodeDelay),
412292SN/A      decodeWidth(params->decodeWidth),
422292SN/A      numThreads(params->numberOfThreads)
431060SN/A{
442292SN/A    _status = Inactive;
452292SN/A
462348SN/A    // Setup status, make sure stall signals are clear.
472292SN/A    for (int i = 0; i < numThreads; ++i) {
482292SN/A        decodeStatus[i] = Idle;
492292SN/A
502292SN/A        stalls[i].rename = false;
512292SN/A        stalls[i].iew = false;
522292SN/A        stalls[i].commit = false;
532292SN/A    }
542292SN/A
552292SN/A    // @todo: Make into a parameter
562292SN/A    skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
572292SN/A}
582292SN/A
592292SN/Atemplate <class Impl>
602292SN/Astd::string
612292SN/ADefaultDecode<Impl>::name() const
622292SN/A{
632292SN/A    return cpu->name() + ".decode";
641060SN/A}
651060SN/A
661062SN/Atemplate <class Impl>
671062SN/Avoid
682292SN/ADefaultDecode<Impl>::regStats()
691062SN/A{
701062SN/A    decodeIdleCycles
712307SN/A        .name(name() + ".DECODE:IdleCycles")
721062SN/A        .desc("Number of cycles decode is idle")
731062SN/A        .prereq(decodeIdleCycles);
741062SN/A    decodeBlockedCycles
752307SN/A        .name(name() + ".DECODE:BlockedCycles")
761062SN/A        .desc("Number of cycles decode is blocked")
771062SN/A        .prereq(decodeBlockedCycles);
782292SN/A    decodeRunCycles
792307SN/A        .name(name() + ".DECODE:RunCycles")
802292SN/A        .desc("Number of cycles decode is running")
812292SN/A        .prereq(decodeRunCycles);
821062SN/A    decodeUnblockCycles
832307SN/A        .name(name() + ".DECODE:UnblockCycles")
841062SN/A        .desc("Number of cycles decode is unblocking")
851062SN/A        .prereq(decodeUnblockCycles);
861062SN/A    decodeSquashCycles
872307SN/A        .name(name() + ".DECODE:SquashCycles")
881062SN/A        .desc("Number of cycles decode is squashing")
891062SN/A        .prereq(decodeSquashCycles);
902307SN/A    decodeBranchResolved
912307SN/A        .name(name() + ".DECODE:BranchResolved")
922307SN/A        .desc("Number of times decode resolved a branch")
932307SN/A        .prereq(decodeBranchResolved);
941062SN/A    decodeBranchMispred
952307SN/A        .name(name() + ".DECODE:BranchMispred")
961062SN/A        .desc("Number of times decode detected a branch misprediction")
971062SN/A        .prereq(decodeBranchMispred);
981062SN/A    decodeControlMispred
992307SN/A        .name(name() + ".DECODE:ControlMispred")
1001062SN/A        .desc("Number of times decode detected an instruction incorrectly"
1011062SN/A              " predicted as a control")
1021062SN/A        .prereq(decodeControlMispred);
1031062SN/A    decodeDecodedInsts
1042307SN/A        .name(name() + ".DECODE:DecodedInsts")
1051062SN/A        .desc("Number of instructions handled by decode")
1061062SN/A        .prereq(decodeDecodedInsts);
1071062SN/A    decodeSquashedInsts
1082307SN/A        .name(name() + ".DECODE:SquashedInsts")
1091062SN/A        .desc("Number of squashed instructions handled by decode")
1101062SN/A        .prereq(decodeSquashedInsts);
1111062SN/A}
1121062SN/A
1131060SN/Atemplate<class Impl>
1141060SN/Avoid
1152733Sktlim@umich.eduDefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr)
1161060SN/A{
1172292SN/A    DPRINTF(Decode, "Setting CPU pointer.\n");
1181060SN/A    cpu = cpu_ptr;
1191060SN/A}
1201060SN/A
1211060SN/Atemplate<class Impl>
1221060SN/Avoid
1232292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
1241060SN/A{
1252292SN/A    DPRINTF(Decode, "Setting time buffer pointer.\n");
1261060SN/A    timeBuffer = tb_ptr;
1271060SN/A
1281060SN/A    // Setup wire to write information back to fetch.
1291060SN/A    toFetch = timeBuffer->getWire(0);
1301060SN/A
1311060SN/A    // Create wires to get information from proper places in time buffer.
1321060SN/A    fromRename = timeBuffer->getWire(-renameToDecodeDelay);
1331060SN/A    fromIEW = timeBuffer->getWire(-iewToDecodeDelay);
1341060SN/A    fromCommit = timeBuffer->getWire(-commitToDecodeDelay);
1351060SN/A}
1361060SN/A
1371060SN/Atemplate<class Impl>
1381060SN/Avoid
1392292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
1401060SN/A{
1412292SN/A    DPRINTF(Decode, "Setting decode queue pointer.\n");
1421060SN/A    decodeQueue = dq_ptr;
1431060SN/A
1441060SN/A    // Setup wire to write information to proper place in decode queue.
1451060SN/A    toRename = decodeQueue->getWire(0);
1461060SN/A}
1471060SN/A
1481060SN/Atemplate<class Impl>
1491060SN/Avoid
1502292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
1511060SN/A{
1522292SN/A    DPRINTF(Decode, "Setting fetch queue pointer.\n");
1531060SN/A    fetchQueue = fq_ptr;
1541060SN/A
1551060SN/A    // Setup wire to read information from fetch queue.
1561060SN/A    fromFetch = fetchQueue->getWire(-fetchToDecodeDelay);
1571060SN/A}
1581060SN/A
1591060SN/Atemplate<class Impl>
1602292SN/Avoid
1612292SN/ADefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
1622292SN/A{
1632292SN/A    DPRINTF(Decode, "Setting active threads list pointer.\n");
1642292SN/A    activeThreads = at_ptr;
1652292SN/A}
1662292SN/A
1672307SN/Atemplate <class Impl>
1682863Sktlim@umich.edubool
1692843Sktlim@umich.eduDefaultDecode<Impl>::drain()
1702307SN/A{
1712843Sktlim@umich.edu    // Decode is done draining at any time.
1722843Sktlim@umich.edu    cpu->signalDrained();
1732863Sktlim@umich.edu    return true;
1742307SN/A}
1752307SN/A
1762307SN/Atemplate <class Impl>
1772307SN/Avoid
1782307SN/ADefaultDecode<Impl>::takeOverFrom()
1792307SN/A{
1802307SN/A    _status = Inactive;
1812307SN/A
1822348SN/A    // Be sure to reset state and clear out any old instructions.
1832307SN/A    for (int i = 0; i < numThreads; ++i) {
1842307SN/A        decodeStatus[i] = Idle;
1852307SN/A
1862307SN/A        stalls[i].rename = false;
1872307SN/A        stalls[i].iew = false;
1882307SN/A        stalls[i].commit = false;
1892307SN/A        while (!insts[i].empty())
1902307SN/A            insts[i].pop();
1912307SN/A        while (!skidBuffer[i].empty())
1922307SN/A            skidBuffer[i].pop();
1932307SN/A        branchCount[i] = 0;
1942307SN/A    }
1952307SN/A    wroteToTimeBuffer = false;
1962307SN/A}
1972307SN/A
1982292SN/Atemplate<class Impl>
1992292SN/Abool
2002292SN/ADefaultDecode<Impl>::checkStall(unsigned tid) const
2012292SN/A{
2022292SN/A    bool ret_val = false;
2032292SN/A
2042292SN/A    if (stalls[tid].rename) {
2052292SN/A        DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
2062292SN/A        ret_val = true;
2072292SN/A    } else if (stalls[tid].iew) {
2082292SN/A        DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
2092292SN/A        ret_val = true;
2102292SN/A    } else if (stalls[tid].commit) {
2112292SN/A        DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
2122292SN/A        ret_val = true;
2132292SN/A    }
2142292SN/A
2152292SN/A    return ret_val;
2162292SN/A}
2172292SN/A
2182292SN/Atemplate<class Impl>
2191681SN/Ainline bool
2202292SN/ADefaultDecode<Impl>::fetchInstsValid()
2211681SN/A{
2221681SN/A    return fromFetch->size > 0;
2231681SN/A}
2241681SN/A
2251681SN/Atemplate<class Impl>
2262292SN/Abool
2272292SN/ADefaultDecode<Impl>::block(unsigned tid)
2281060SN/A{
2292292SN/A    DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
2301060SN/A
2311060SN/A    // Add the current inputs to the skid buffer so they can be
2321060SN/A    // reprocessed when this stage unblocks.
2332292SN/A    skidInsert(tid);
2341060SN/A
2352348SN/A    // If the decode status is blocked or unblocking then decode has not yet
2362348SN/A    // signalled fetch to unblock. In that case, there is no need to tell
2372348SN/A    // fetch to block.
2382292SN/A    if (decodeStatus[tid] != Blocked) {
2392292SN/A        // Set the status to Blocked.
2402292SN/A        decodeStatus[tid] = Blocked;
2412348SN/A
2422348SN/A        if (decodeStatus[tid] != Unblocking) {
2432348SN/A            toFetch->decodeBlock[tid] = true;
2442348SN/A            wroteToTimeBuffer = true;
2452348SN/A        }
2462348SN/A
2472292SN/A        return true;
2482292SN/A    }
2492292SN/A
2502292SN/A    return false;
2511060SN/A}
2521060SN/A
2531060SN/Atemplate<class Impl>
2542292SN/Abool
2552292SN/ADefaultDecode<Impl>::unblock(unsigned tid)
2561060SN/A{
2572292SN/A    // Decode is done unblocking only if the skid buffer is empty.
2582292SN/A    if (skidBuffer[tid].empty()) {
2592292SN/A        DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
2602292SN/A        toFetch->decodeUnblock[tid] = true;
2612292SN/A        wroteToTimeBuffer = true;
2621060SN/A
2632292SN/A        decodeStatus[tid] = Running;
2642292SN/A        return true;
2651060SN/A    }
2661681SN/A
2672329SN/A    DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
2682329SN/A
2692292SN/A    return false;
2701060SN/A}
2711060SN/A
2721060SN/Atemplate<class Impl>
2731060SN/Avoid
2742292SN/ADefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
2751060SN/A{
2762292SN/A    DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
2772292SN/A            "detected at decode.\n", tid);
2782292SN/A
2792348SN/A    // Send back mispredict information.
2802292SN/A    toFetch->decodeInfo[tid].branchMispredict = true;
2812292SN/A    toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
2822292SN/A    toFetch->decodeInfo[tid].predIncorrect = true;
2832292SN/A    toFetch->decodeInfo[tid].squash = true;
2842678Sktlim@umich.edu    toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
2852348SN/A    toFetch->decodeInfo[tid].branchTaken =
2862348SN/A        inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
2872292SN/A
2882348SN/A    // Might have to tell fetch to unblock.
2892292SN/A    if (decodeStatus[tid] == Blocked ||
2902292SN/A        decodeStatus[tid] == Unblocking) {
2912292SN/A        toFetch->decodeUnblock[tid] = 1;
2922292SN/A    }
2932292SN/A
2941060SN/A    // Set status to squashing.
2952292SN/A    decodeStatus[tid] = Squashing;
2961060SN/A
2972292SN/A    for (int i=0; i<fromFetch->size; i++) {
2982292SN/A        if (fromFetch->insts[i]->threadNumber == tid &&
2992292SN/A            fromFetch->insts[i]->seqNum > inst->seqNum) {
3002731Sktlim@umich.edu            fromFetch->insts[i]->setSquashed();
3012292SN/A        }
3022292SN/A    }
3032292SN/A
3042348SN/A    // Clear the instruction list and skid buffer in case they have any
3052348SN/A    // insts in them.
3062292SN/A    while (!insts[tid].empty()) {
3072292SN/A        insts[tid].pop();
3082292SN/A    }
3091060SN/A
3102292SN/A    while (!skidBuffer[tid].empty()) {
3112292SN/A        skidBuffer[tid].pop();
3122292SN/A    }
3132292SN/A
3142292SN/A    // Squash instructions up until this one
3152292SN/A    cpu->removeInstsUntil(inst->seqNum, tid);
3162292SN/A}
3172292SN/A
3182292SN/Atemplate<class Impl>
3192292SN/Aunsigned
3202292SN/ADefaultDecode<Impl>::squash(unsigned tid)
3212292SN/A{
3222292SN/A    DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
3232292SN/A
3242292SN/A    if (decodeStatus[tid] == Blocked ||
3252292SN/A        decodeStatus[tid] == Unblocking) {
3262292SN/A#if !FULL_SYSTEM
3272292SN/A        // In syscall emulation, we can have both a block and a squash due
3282292SN/A        // to a syscall in the same cycle.  This would cause both signals to
3292292SN/A        // be high.  This shouldn't happen in full system.
3302329SN/A        // @todo: Determine if this still happens.
3312292SN/A        if (toFetch->decodeBlock[tid]) {
3322292SN/A            toFetch->decodeBlock[tid] = 0;
3332292SN/A        } else {
3342292SN/A            toFetch->decodeUnblock[tid] = 1;
3352292SN/A        }
3362292SN/A#else
3372292SN/A        toFetch->decodeUnblock[tid] = 1;
3382292SN/A#endif
3392292SN/A    }
3402292SN/A
3412292SN/A    // Set status to squashing.
3422292SN/A    decodeStatus[tid] = Squashing;
3432292SN/A
3442292SN/A    // Go through incoming instructions from fetch and squash them.
3452292SN/A    unsigned squash_count = 0;
3462292SN/A
3472292SN/A    for (int i=0; i<fromFetch->size; i++) {
3482292SN/A        if (fromFetch->insts[i]->threadNumber == tid) {
3492731Sktlim@umich.edu            fromFetch->insts[i]->setSquashed();
3502292SN/A            squash_count++;
3512292SN/A        }
3522292SN/A    }
3532292SN/A
3542348SN/A    // Clear the instruction list and skid buffer in case they have any
3552348SN/A    // insts in them.
3562292SN/A    while (!insts[tid].empty()) {
3572292SN/A        insts[tid].pop();
3582292SN/A    }
3592292SN/A
3602292SN/A    while (!skidBuffer[tid].empty()) {
3612292SN/A        skidBuffer[tid].pop();
3622292SN/A    }
3632292SN/A
3642292SN/A    return squash_count;
3652292SN/A}
3662292SN/A
3672292SN/Atemplate<class Impl>
3682292SN/Avoid
3692292SN/ADefaultDecode<Impl>::skidInsert(unsigned tid)
3702292SN/A{
3712292SN/A    DynInstPtr inst = NULL;
3722292SN/A
3732292SN/A    while (!insts[tid].empty()) {
3742292SN/A        inst = insts[tid].front();
3752292SN/A
3762292SN/A        insts[tid].pop();
3772292SN/A
3782292SN/A        assert(tid == inst->threadNumber);
3792292SN/A
3802292SN/A        DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
3812292SN/A                inst->seqNum, inst->readPC(), inst->threadNumber);
3822292SN/A
3832292SN/A        skidBuffer[tid].push(inst);
3842292SN/A    }
3852292SN/A
3862329SN/A    // @todo: Eventually need to enforce this by not letting a thread
3872292SN/A    // fetch past its skidbuffer
3882292SN/A    assert(skidBuffer[tid].size() <= skidBufferMax);
3892292SN/A}
3902292SN/A
3912292SN/Atemplate<class Impl>
3922292SN/Abool
3932292SN/ADefaultDecode<Impl>::skidsEmpty()
3942292SN/A{
3952292SN/A    list<unsigned>::iterator threads = (*activeThreads).begin();
3962292SN/A
3972292SN/A    while (threads != (*activeThreads).end()) {
3982292SN/A        if (!skidBuffer[*threads++].empty())
3992292SN/A            return false;
4002292SN/A    }
4012292SN/A
4022292SN/A    return true;
4032292SN/A}
4042292SN/A
4052292SN/Atemplate<class Impl>
4062292SN/Avoid
4072292SN/ADefaultDecode<Impl>::updateStatus()
4082292SN/A{
4092292SN/A    bool any_unblocking = false;
4102292SN/A
4112292SN/A    list<unsigned>::iterator threads = (*activeThreads).begin();
4122292SN/A
4132292SN/A    threads = (*activeThreads).begin();
4142292SN/A
4152292SN/A    while (threads != (*activeThreads).end()) {
4162292SN/A        unsigned tid = *threads++;
4172292SN/A
4182292SN/A        if (decodeStatus[tid] == Unblocking) {
4192292SN/A            any_unblocking = true;
4202292SN/A            break;
4212292SN/A        }
4222292SN/A    }
4232292SN/A
4242292SN/A    // Decode will have activity if it's unblocking.
4252292SN/A    if (any_unblocking) {
4262292SN/A        if (_status == Inactive) {
4272292SN/A            _status = Active;
4282292SN/A
4292292SN/A            DPRINTF(Activity, "Activating stage.\n");
4302292SN/A
4312733Sktlim@umich.edu            cpu->activateStage(O3CPU::DecodeIdx);
4322292SN/A        }
4332292SN/A    } else {
4342292SN/A        // If it's not unblocking, then decode will not have any internal
4352292SN/A        // activity.  Switch it to inactive.
4362292SN/A        if (_status == Active) {
4372292SN/A            _status = Inactive;
4382292SN/A            DPRINTF(Activity, "Deactivating stage.\n");
4392292SN/A
4402733Sktlim@umich.edu            cpu->deactivateStage(O3CPU::DecodeIdx);
4412292SN/A        }
4422292SN/A    }
4432292SN/A}
4442292SN/A
4452292SN/Atemplate <class Impl>
4462292SN/Avoid
4472292SN/ADefaultDecode<Impl>::sortInsts()
4482292SN/A{
4492292SN/A    int insts_from_fetch = fromFetch->size;
4502329SN/A#ifdef DEBUG
4512292SN/A    for (int i=0; i < numThreads; i++)
4522292SN/A        assert(insts[i].empty());
4532329SN/A#endif
4542292SN/A    for (int i = 0; i < insts_from_fetch; ++i) {
4552292SN/A        insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
4561060SN/A    }
4571060SN/A}
4581060SN/A
4591060SN/Atemplate<class Impl>
4601060SN/Avoid
4612292SN/ADefaultDecode<Impl>::readStallSignals(unsigned tid)
4621060SN/A{
4632292SN/A    if (fromRename->renameBlock[tid]) {
4642292SN/A        stalls[tid].rename = true;
4652292SN/A    }
4661060SN/A
4672292SN/A    if (fromRename->renameUnblock[tid]) {
4682292SN/A        assert(stalls[tid].rename);
4692292SN/A        stalls[tid].rename = false;
4702292SN/A    }
4711060SN/A
4722292SN/A    if (fromIEW->iewBlock[tid]) {
4732292SN/A        stalls[tid].iew = true;
4742292SN/A    }
4751062SN/A
4762292SN/A    if (fromIEW->iewUnblock[tid]) {
4772292SN/A        assert(stalls[tid].iew);
4782292SN/A        stalls[tid].iew = false;
4792292SN/A    }
4801061SN/A
4812292SN/A    if (fromCommit->commitBlock[tid]) {
4822292SN/A        stalls[tid].commit = true;
4832292SN/A    }
4841062SN/A
4852292SN/A    if (fromCommit->commitUnblock[tid]) {
4862292SN/A        assert(stalls[tid].commit);
4872292SN/A        stalls[tid].commit = false;
4882292SN/A    }
4892292SN/A}
4901060SN/A
4912292SN/Atemplate <class Impl>
4922292SN/Abool
4932292SN/ADefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
4942292SN/A{
4952292SN/A    // Check if there's a squash signal, squash if there is.
4962292SN/A    // Check stall signals, block if necessary.
4972292SN/A    // If status was blocked
4982292SN/A    //     Check if stall conditions have passed
4992292SN/A    //         if so then go to unblocking
5002292SN/A    // If status was Squashing
5012292SN/A    //     check if squashing is not high.  Switch to running this cycle.
5021060SN/A
5032292SN/A    // Update the per thread stall statuses.
5042292SN/A    readStallSignals(tid);
5051060SN/A
5062292SN/A    // Check squash signals from commit.
5072292SN/A    if (fromCommit->commitInfo[tid].squash) {
5081681SN/A
5092292SN/A        DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
5102292SN/A                "from commit.\n", tid);
5112292SN/A
5122292SN/A        squash(tid);
5132292SN/A
5142292SN/A        return true;
5152292SN/A    }
5162292SN/A
5172292SN/A    // Check ROB squash signals from commit.
5182292SN/A    if (fromCommit->commitInfo[tid].robSquashing) {
5192703Sktlim@umich.edu        DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
5202292SN/A
5212292SN/A        // Continue to squash.
5222292SN/A        decodeStatus[tid] = Squashing;
5232292SN/A
5242292SN/A        return true;
5252292SN/A    }
5262292SN/A
5272292SN/A    if (checkStall(tid)) {
5282292SN/A        return block(tid);
5292292SN/A    }
5302292SN/A
5312292SN/A    if (decodeStatus[tid] == Blocked) {
5322292SN/A        DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
5332292SN/A                tid);
5342292SN/A
5352292SN/A        decodeStatus[tid] = Unblocking;
5362292SN/A
5372292SN/A        unblock(tid);
5382292SN/A
5392292SN/A        return true;
5402292SN/A    }
5412292SN/A
5422292SN/A    if (decodeStatus[tid] == Squashing) {
5432292SN/A        // Switch status to running if decode isn't being told to block or
5442292SN/A        // squash this cycle.
5452292SN/A        DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
5462292SN/A                tid);
5472292SN/A
5482292SN/A        decodeStatus[tid] = Running;
5492292SN/A
5502292SN/A        return false;
5512292SN/A    }
5522292SN/A
5532292SN/A    // If we've reached this point, we have not gotten any signals that
5542292SN/A    // cause decode to change its status.  Decode remains the same as before.
5552292SN/A    return false;
5562292SN/A}
5572292SN/A
5582292SN/Atemplate<class Impl>
5592292SN/Avoid
5602292SN/ADefaultDecode<Impl>::tick()
5612292SN/A{
5622292SN/A    wroteToTimeBuffer = false;
5632292SN/A
5642292SN/A    bool status_change = false;
5652292SN/A
5662292SN/A    toRenameIndex = 0;
5672292SN/A
5682292SN/A    list<unsigned>::iterator threads = (*activeThreads).begin();
5692292SN/A
5702292SN/A    sortInsts();
5712292SN/A
5722292SN/A    //Check stall and squash signals.
5732292SN/A    while (threads != (*activeThreads).end()) {
5742292SN/A    unsigned tid = *threads++;
5752292SN/A
5762292SN/A        DPRINTF(Decode,"Processing [tid:%i]\n",tid);
5772292SN/A        status_change =  checkSignalsAndUpdate(tid) || status_change;
5782292SN/A
5792292SN/A        decode(status_change, tid);
5802292SN/A    }
5812292SN/A
5822292SN/A    if (status_change) {
5832292SN/A        updateStatus();
5842292SN/A    }
5852292SN/A
5862292SN/A    if (wroteToTimeBuffer) {
5872292SN/A        DPRINTF(Activity, "Activity this cycle.\n");
5882292SN/A
5892292SN/A        cpu->activityThisCycle();
5901060SN/A    }
5911060SN/A}
5921060SN/A
5931060SN/Atemplate<class Impl>
5941060SN/Avoid
5952292SN/ADefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
5961060SN/A{
5972292SN/A    // If status is Running or idle,
5982292SN/A    //     call decodeInsts()
5992292SN/A    // If status is Unblocking,
6002292SN/A    //     buffer any instructions coming from fetch
6012292SN/A    //     continue trying to empty skid buffer
6022292SN/A    //     check if stall conditions have passed
6032292SN/A
6042292SN/A    if (decodeStatus[tid] == Blocked) {
6052292SN/A        ++decodeBlockedCycles;
6062292SN/A    } else if (decodeStatus[tid] == Squashing) {
6072292SN/A        ++decodeSquashCycles;
6081060SN/A    }
6091060SN/A
6102292SN/A    // Decode should try to decode as many instructions as its bandwidth
6112292SN/A    // will allow, as long as it is not currently blocked.
6122292SN/A    if (decodeStatus[tid] == Running ||
6132292SN/A        decodeStatus[tid] == Idle) {
6142292SN/A        DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run "
6152292SN/A                "stage.\n",tid);
6162292SN/A
6172292SN/A        decodeInsts(tid);
6182292SN/A    } else if (decodeStatus[tid] == Unblocking) {
6192292SN/A        // Make sure that the skid buffer has something in it if the
6202292SN/A        // status is unblocking.
6212292SN/A        assert(!skidsEmpty());
6222292SN/A
6232292SN/A        // If the status was unblocking, then instructions from the skid
6242292SN/A        // buffer were used.  Remove those instructions and handle
6252292SN/A        // the rest of unblocking.
6262292SN/A        decodeInsts(tid);
6272292SN/A
6282292SN/A        if (fetchInstsValid()) {
6292292SN/A            // Add the current inputs to the skid buffer so they can be
6302292SN/A            // reprocessed when this stage unblocks.
6312292SN/A            skidInsert(tid);
6322292SN/A        }
6332292SN/A
6342292SN/A        status_change = unblock(tid) || status_change;
6351060SN/A    }
6362292SN/A}
6371060SN/A
6382292SN/Atemplate <class Impl>
6392292SN/Avoid
6402292SN/ADefaultDecode<Impl>::decodeInsts(unsigned tid)
6412292SN/A{
6422292SN/A    // Instructions can come either from the skid buffer or the list of
6432292SN/A    // instructions coming from fetch, depending on decode's status.
6442292SN/A    int insts_available = decodeStatus[tid] == Unblocking ?
6452292SN/A        skidBuffer[tid].size() : insts[tid].size();
6462292SN/A
6472292SN/A    if (insts_available == 0) {
6482292SN/A        DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
6492292SN/A                " early.\n",tid);
6501060SN/A        // Should I change the status to idle?
6511062SN/A        ++decodeIdleCycles;
6521060SN/A        return;
6532292SN/A    } else if (decodeStatus[tid] == Unblocking) {
6542292SN/A        DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
6552292SN/A                "buffer.\n",tid);
6562292SN/A        ++decodeUnblockCycles;
6572292SN/A    } else if (decodeStatus[tid] == Running) {
6582292SN/A        ++decodeRunCycles;
6591060SN/A    }
6601060SN/A
6611061SN/A    DynInstPtr inst;
6621061SN/A
6632292SN/A    std::queue<DynInstPtr>
6642292SN/A        &insts_to_decode = decodeStatus[tid] == Unblocking ?
6652292SN/A        skidBuffer[tid] : insts[tid];
6661061SN/A
6672292SN/A    DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
6681060SN/A
6692292SN/A    while (insts_available > 0 && toRenameIndex < decodeWidth) {
6702292SN/A        assert(!insts_to_decode.empty());
6711060SN/A
6722292SN/A        inst = insts_to_decode.front();
6731062SN/A
6742292SN/A        insts_to_decode.pop();
6751061SN/A
6762292SN/A        DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
6772292SN/A                "PC %#x\n",
6782292SN/A                tid, inst->seqNum, inst->readPC());
6791061SN/A
6801061SN/A        if (inst->isSquashed()) {
6812292SN/A            DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
6821061SN/A                    "squashed, skipping.\n",
6832292SN/A                    tid, inst->seqNum, inst->readPC());
6841061SN/A
6851062SN/A            ++decodeSquashedInsts;
6861062SN/A
6871061SN/A            --insts_available;
6881061SN/A
6891061SN/A            continue;
6901061SN/A        }
6911060SN/A
6921681SN/A        // Also check if instructions have no source registers.  Mark
6931681SN/A        // them as ready to issue at any time.  Not sure if this check
6941681SN/A        // should exist here or at a later stage; however it doesn't matter
6951681SN/A        // too much for function correctness.
6961681SN/A        if (inst->numSrcRegs() == 0) {
6971681SN/A            inst->setCanIssue();
6981681SN/A        }
6991681SN/A
7001060SN/A        // This current instruction is valid, so add it into the decode
7011060SN/A        // queue.  The next instruction may not be valid, so check to
7021060SN/A        // see if branches were predicted correctly.
7032292SN/A        toRename->insts[toRenameIndex] = inst;
7041061SN/A
7051061SN/A        ++(toRename->size);
7062292SN/A        ++toRenameIndex;
7072292SN/A        ++decodeDecodedInsts;
7082292SN/A        --insts_available;
7091060SN/A
7101060SN/A        // Ensure that if it was predicted as a branch, it really is a
7111061SN/A        // branch.
7121060SN/A        if (inst->predTaken() && !inst->isControl()) {
7131060SN/A            panic("Instruction predicted as a branch!");
7141060SN/A
7151062SN/A            ++decodeControlMispred;
7162292SN/A
7171060SN/A            // Might want to set some sort of boolean and just do
7181060SN/A            // a check at the end
7192292SN/A            squash(inst, inst->threadNumber);
7202292SN/A
7211060SN/A            break;
7221060SN/A        }
7231060SN/A
7241062SN/A        // Go ahead and compute any PC-relative branches.
7251063SN/A        if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
7262307SN/A            ++decodeBranchResolved;
7271062SN/A
7282678Sktlim@umich.edu            if (inst->branchTarget() != inst->readPredTarg()) {
7291062SN/A                ++decodeBranchMispred;
7302292SN/A
7311060SN/A                // Might want to set some sort of boolean and just do
7321060SN/A                // a check at the end
7332292SN/A                squash(inst, inst->threadNumber);
7342345SN/A                inst->setPredTarg(inst->branchTarget());
7352292SN/A
7361060SN/A                break;
7371060SN/A            }
7381060SN/A        }
7391060SN/A    }
7401061SN/A
7412292SN/A    // If we didn't process all instructions, then we will need to block
7422292SN/A    // and put all those instructions into the skid buffer.
7432292SN/A    if (!insts_to_decode.empty()) {
7442292SN/A        block(tid);
7452292SN/A    }
7462292SN/A
7472292SN/A    // Record that decode has written to the time buffer for activity
7482292SN/A    // tracking.
7492292SN/A    if (toRenameIndex) {
7502292SN/A        wroteToTimeBuffer = true;
7512292SN/A    }
7521060SN/A}
753