decode_impl.hh revision 10328
19444SAndreas.Sandberg@ARM.com/* 210328Smitch.hayenga@arm.com * Copyright (c) 2012, 2014 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_DECODE_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_DECODE_IMPL_HH__ 459944Smatt.horsnell@ARM.com 468230Snate@binkert.org#include "arch/types.hh" 478230Snate@binkert.org#include "base/trace.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 491717SN/A#include "cpu/o3/decode.hh" 508230Snate@binkert.org#include "cpu/inst_seq.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/Decode.hh" 539527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 546221Snate@binkert.org#include "params/DerivO3CPU.hh" 558793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 561060SN/A 578737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 588737Skoansin.tan@gmail.com// we open up the entire namespace std 598737Skoansin.tan@gmail.comusing std::list; 605529Snate@binkert.org 611060SN/Atemplate<class Impl> 625529Snate@binkert.orgDefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) 634329Sktlim@umich.edu : cpu(_cpu), 644329Sktlim@umich.edu renameToDecodeDelay(params->renameToDecodeDelay), 652292SN/A iewToDecodeDelay(params->iewToDecodeDelay), 662292SN/A commitToDecodeDelay(params->commitToDecodeDelay), 672292SN/A fetchToDecodeDelay(params->fetchToDecodeDelay), 682292SN/A decodeWidth(params->decodeWidth), 695529Snate@binkert.org numThreads(params->numThreads) 701060SN/A{ 7110172Sdam.sunwoo@arm.com if (decodeWidth > Impl::MaxWidth) 7210172Sdam.sunwoo@arm.com fatal("decodeWidth (%d) is larger than compiled limit (%d),\n" 7310172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7410172Sdam.sunwoo@arm.com decodeWidth, static_cast<int>(Impl::MaxWidth)); 7510172Sdam.sunwoo@arm.com 769444SAndreas.Sandberg@ARM.com // @todo: Make into a parameter 779444SAndreas.Sandberg@ARM.com skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; 789444SAndreas.Sandberg@ARM.com} 799444SAndreas.Sandberg@ARM.com 809444SAndreas.Sandberg@ARM.comtemplate<class Impl> 819444SAndreas.Sandberg@ARM.comvoid 829444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::startupStage() 839444SAndreas.Sandberg@ARM.com{ 849444SAndreas.Sandberg@ARM.com resetStage(); 859444SAndreas.Sandberg@ARM.com} 869444SAndreas.Sandberg@ARM.com 879444SAndreas.Sandberg@ARM.comtemplate<class Impl> 889444SAndreas.Sandberg@ARM.comvoid 899444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::resetStage() 909444SAndreas.Sandberg@ARM.com{ 912292SN/A _status = Inactive; 922292SN/A 932348SN/A // Setup status, make sure stall signals are clear. 946221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 956221Snate@binkert.org decodeStatus[tid] = Idle; 962292SN/A 976221Snate@binkert.org stalls[tid].rename = false; 982292SN/A } 992292SN/A} 1002292SN/A 1012292SN/Atemplate <class Impl> 1022292SN/Astd::string 1032292SN/ADefaultDecode<Impl>::name() const 1042292SN/A{ 1052292SN/A return cpu->name() + ".decode"; 1061060SN/A} 1071060SN/A 1081062SN/Atemplate <class Impl> 1091062SN/Avoid 1102292SN/ADefaultDecode<Impl>::regStats() 1111062SN/A{ 1121062SN/A decodeIdleCycles 1138240Snate@binkert.org .name(name() + ".IdleCycles") 1141062SN/A .desc("Number of cycles decode is idle") 1151062SN/A .prereq(decodeIdleCycles); 1161062SN/A decodeBlockedCycles 1178240Snate@binkert.org .name(name() + ".BlockedCycles") 1181062SN/A .desc("Number of cycles decode is blocked") 1191062SN/A .prereq(decodeBlockedCycles); 1202292SN/A decodeRunCycles 1218240Snate@binkert.org .name(name() + ".RunCycles") 1222292SN/A .desc("Number of cycles decode is running") 1232292SN/A .prereq(decodeRunCycles); 1241062SN/A decodeUnblockCycles 1258240Snate@binkert.org .name(name() + ".UnblockCycles") 1261062SN/A .desc("Number of cycles decode is unblocking") 1271062SN/A .prereq(decodeUnblockCycles); 1281062SN/A decodeSquashCycles 1298240Snate@binkert.org .name(name() + ".SquashCycles") 1301062SN/A .desc("Number of cycles decode is squashing") 1311062SN/A .prereq(decodeSquashCycles); 1322307SN/A decodeBranchResolved 1338240Snate@binkert.org .name(name() + ".BranchResolved") 1342307SN/A .desc("Number of times decode resolved a branch") 1352307SN/A .prereq(decodeBranchResolved); 1361062SN/A decodeBranchMispred 1378240Snate@binkert.org .name(name() + ".BranchMispred") 1381062SN/A .desc("Number of times decode detected a branch misprediction") 1391062SN/A .prereq(decodeBranchMispred); 1401062SN/A decodeControlMispred 1418240Snate@binkert.org .name(name() + ".ControlMispred") 1421062SN/A .desc("Number of times decode detected an instruction incorrectly" 1431062SN/A " predicted as a control") 1441062SN/A .prereq(decodeControlMispred); 1451062SN/A decodeDecodedInsts 1468240Snate@binkert.org .name(name() + ".DecodedInsts") 1471062SN/A .desc("Number of instructions handled by decode") 1481062SN/A .prereq(decodeDecodedInsts); 1491062SN/A decodeSquashedInsts 1508240Snate@binkert.org .name(name() + ".SquashedInsts") 1511062SN/A .desc("Number of squashed instructions handled by decode") 1521062SN/A .prereq(decodeSquashedInsts); 1531062SN/A} 1541062SN/A 1551060SN/Atemplate<class Impl> 1561060SN/Avoid 1572292SN/ADefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1581060SN/A{ 1591060SN/A timeBuffer = tb_ptr; 1601060SN/A 1611060SN/A // Setup wire to write information back to fetch. 1621060SN/A toFetch = timeBuffer->getWire(0); 1631060SN/A 1641060SN/A // Create wires to get information from proper places in time buffer. 1651060SN/A fromRename = timeBuffer->getWire(-renameToDecodeDelay); 1661060SN/A fromIEW = timeBuffer->getWire(-iewToDecodeDelay); 1671060SN/A fromCommit = timeBuffer->getWire(-commitToDecodeDelay); 1681060SN/A} 1691060SN/A 1701060SN/Atemplate<class Impl> 1711060SN/Avoid 1722292SN/ADefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1731060SN/A{ 1741060SN/A decodeQueue = dq_ptr; 1751060SN/A 1761060SN/A // Setup wire to write information to proper place in decode queue. 1771060SN/A toRename = decodeQueue->getWire(0); 1781060SN/A} 1791060SN/A 1801060SN/Atemplate<class Impl> 1811060SN/Avoid 1822292SN/ADefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) 1831060SN/A{ 1841060SN/A fetchQueue = fq_ptr; 1851060SN/A 1861060SN/A // Setup wire to read information from fetch queue. 1871060SN/A fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); 1881060SN/A} 1891060SN/A 1901060SN/Atemplate<class Impl> 1912292SN/Avoid 1926221Snate@binkert.orgDefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr) 1932292SN/A{ 1942292SN/A activeThreads = at_ptr; 1952292SN/A} 1962292SN/A 1972307SN/Atemplate <class Impl> 1989444SAndreas.Sandberg@ARM.comvoid 1999444SAndreas.Sandberg@ARM.comDefaultDecode<Impl>::drainSanityCheck() const 2002307SN/A{ 2016221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 2029444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 2039444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 2042307SN/A } 2052307SN/A} 2062307SN/A 20710328Smitch.hayenga@arm.comtemplate <class Impl> 20810328Smitch.hayenga@arm.combool 20910328Smitch.hayenga@arm.comDefaultDecode<Impl>::isDrained() const 21010328Smitch.hayenga@arm.com{ 21110328Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 21210328Smitch.hayenga@arm.com if (!insts[tid].empty() || !skidBuffer[tid].empty()) 21310328Smitch.hayenga@arm.com return false; 21410328Smitch.hayenga@arm.com } 21510328Smitch.hayenga@arm.com return true; 21610328Smitch.hayenga@arm.com} 21710328Smitch.hayenga@arm.com 2182292SN/Atemplate<class Impl> 2192292SN/Abool 2206221Snate@binkert.orgDefaultDecode<Impl>::checkStall(ThreadID tid) const 2212292SN/A{ 2222292SN/A bool ret_val = false; 2232292SN/A 2242292SN/A if (stalls[tid].rename) { 2252292SN/A DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid); 2262292SN/A ret_val = true; 2272292SN/A } 2282292SN/A 2292292SN/A return ret_val; 2302292SN/A} 2312292SN/A 2322292SN/Atemplate<class Impl> 2331681SN/Ainline bool 2342292SN/ADefaultDecode<Impl>::fetchInstsValid() 2351681SN/A{ 2361681SN/A return fromFetch->size > 0; 2371681SN/A} 2381681SN/A 2391681SN/Atemplate<class Impl> 2402292SN/Abool 2416221Snate@binkert.orgDefaultDecode<Impl>::block(ThreadID tid) 2421060SN/A{ 2432292SN/A DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid); 2441060SN/A 2451060SN/A // Add the current inputs to the skid buffer so they can be 2461060SN/A // reprocessed when this stage unblocks. 2472292SN/A skidInsert(tid); 2481060SN/A 2492348SN/A // If the decode status is blocked or unblocking then decode has not yet 2502348SN/A // signalled fetch to unblock. In that case, there is no need to tell 2512348SN/A // fetch to block. 2522292SN/A if (decodeStatus[tid] != Blocked) { 2532292SN/A // Set the status to Blocked. 2542292SN/A decodeStatus[tid] = Blocked; 2552348SN/A 2569514SAli.Saidi@ARM.com if (toFetch->decodeUnblock[tid]) { 2579514SAli.Saidi@ARM.com toFetch->decodeUnblock[tid] = false; 2589514SAli.Saidi@ARM.com } else { 2592348SN/A toFetch->decodeBlock[tid] = true; 2602348SN/A wroteToTimeBuffer = true; 2612348SN/A } 2622348SN/A 2632292SN/A return true; 2642292SN/A } 2652292SN/A 2662292SN/A return false; 2671060SN/A} 2681060SN/A 2691060SN/Atemplate<class Impl> 2702292SN/Abool 2716221Snate@binkert.orgDefaultDecode<Impl>::unblock(ThreadID tid) 2721060SN/A{ 2732292SN/A // Decode is done unblocking only if the skid buffer is empty. 2742292SN/A if (skidBuffer[tid].empty()) { 2752292SN/A DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid); 2762292SN/A toFetch->decodeUnblock[tid] = true; 2772292SN/A wroteToTimeBuffer = true; 2781060SN/A 2792292SN/A decodeStatus[tid] = Running; 2802292SN/A return true; 2811060SN/A } 2821681SN/A 2832329SN/A DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid); 2842329SN/A 2852292SN/A return false; 2861060SN/A} 2871060SN/A 2881060SN/Atemplate<class Impl> 2891060SN/Avoid 2906221Snate@binkert.orgDefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid) 2911060SN/A{ 2927720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch " 2937720Sgblack@eecs.umich.edu "prediction detected at decode.\n", tid, inst->seqNum); 2942292SN/A 2952348SN/A // Send back mispredict information. 2962292SN/A toFetch->decodeInfo[tid].branchMispredict = true; 2972935Sksewell@umich.edu toFetch->decodeInfo[tid].predIncorrect = true; 2988842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].mispredictInst = inst; 2996036Sksewell@umich.edu toFetch->decodeInfo[tid].squash = true; 3002292SN/A toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; 3016036Sksewell@umich.edu toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); 3027720Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching(); 3038503Sgblack@eecs.umich.edu toFetch->decodeInfo[tid].squashInst = inst; 3048842Smrinmoy.ghosh@arm.com if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) { 3058842Smrinmoy.ghosh@arm.com toFetch->decodeInfo[tid].branchTaken = true; 3068842Smrinmoy.ghosh@arm.com } 3076036Sksewell@umich.edu 3083093Sksewell@umich.edu InstSeqNum squash_seq_num = inst->seqNum; 3092935Sksewell@umich.edu 3102348SN/A // Might have to tell fetch to unblock. 3112292SN/A if (decodeStatus[tid] == Blocked || 3122292SN/A decodeStatus[tid] == Unblocking) { 3132292SN/A toFetch->decodeUnblock[tid] = 1; 3142292SN/A } 3152292SN/A 3161060SN/A // Set status to squashing. 3172292SN/A decodeStatus[tid] = Squashing; 3181060SN/A 3192292SN/A for (int i=0; i<fromFetch->size; i++) { 3202292SN/A if (fromFetch->insts[i]->threadNumber == tid && 3212935Sksewell@umich.edu fromFetch->insts[i]->seqNum > squash_seq_num) { 3222731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3232292SN/A } 3242292SN/A } 3252292SN/A 3262348SN/A // Clear the instruction list and skid buffer in case they have any 3272348SN/A // insts in them. 3282292SN/A while (!insts[tid].empty()) { 3292292SN/A insts[tid].pop(); 3302292SN/A } 3311060SN/A 3322292SN/A while (!skidBuffer[tid].empty()) { 3332292SN/A skidBuffer[tid].pop(); 3342292SN/A } 3352292SN/A 3362292SN/A // Squash instructions up until this one 3372935Sksewell@umich.edu cpu->removeInstsUntil(squash_seq_num, tid); 3382292SN/A} 3392292SN/A 3402292SN/Atemplate<class Impl> 3412292SN/Aunsigned 3426221Snate@binkert.orgDefaultDecode<Impl>::squash(ThreadID tid) 3432292SN/A{ 3442292SN/A DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid); 3452292SN/A 3462292SN/A if (decodeStatus[tid] == Blocked || 3472292SN/A decodeStatus[tid] == Unblocking) { 3488793Sgblack@eecs.umich.edu if (FullSystem) { 3498793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3502292SN/A } else { 3518793Sgblack@eecs.umich.edu // In syscall emulation, we can have both a block and a squash due 3528793Sgblack@eecs.umich.edu // to a syscall in the same cycle. This would cause both signals 3538793Sgblack@eecs.umich.edu // to be high. This shouldn't happen in full system. 3548793Sgblack@eecs.umich.edu // @todo: Determine if this still happens. 3558793Sgblack@eecs.umich.edu if (toFetch->decodeBlock[tid]) 3568793Sgblack@eecs.umich.edu toFetch->decodeBlock[tid] = 0; 3578793Sgblack@eecs.umich.edu else 3588793Sgblack@eecs.umich.edu toFetch->decodeUnblock[tid] = 1; 3592292SN/A } 3602292SN/A } 3612292SN/A 3622292SN/A // Set status to squashing. 3632292SN/A decodeStatus[tid] = Squashing; 3642292SN/A 3652292SN/A // Go through incoming instructions from fetch and squash them. 3662292SN/A unsigned squash_count = 0; 3672292SN/A 3682292SN/A for (int i=0; i<fromFetch->size; i++) { 3692292SN/A if (fromFetch->insts[i]->threadNumber == tid) { 3702731Sktlim@umich.edu fromFetch->insts[i]->setSquashed(); 3712292SN/A squash_count++; 3722292SN/A } 3732292SN/A } 3742292SN/A 3752348SN/A // Clear the instruction list and skid buffer in case they have any 3762348SN/A // insts in them. 3772292SN/A while (!insts[tid].empty()) { 3782292SN/A insts[tid].pop(); 3792292SN/A } 3802292SN/A 3812292SN/A while (!skidBuffer[tid].empty()) { 3822292SN/A skidBuffer[tid].pop(); 3832292SN/A } 3842292SN/A 3852292SN/A return squash_count; 3862292SN/A} 3872292SN/A 3882292SN/Atemplate<class Impl> 3892292SN/Avoid 3906221Snate@binkert.orgDefaultDecode<Impl>::skidInsert(ThreadID tid) 3912292SN/A{ 3922292SN/A DynInstPtr inst = NULL; 3932292SN/A 3942292SN/A while (!insts[tid].empty()) { 3952292SN/A inst = insts[tid].front(); 3962292SN/A 3972292SN/A insts[tid].pop(); 3982292SN/A 3992292SN/A assert(tid == inst->threadNumber); 4002292SN/A 40110328Smitch.hayenga@arm.com skidBuffer[tid].push(inst); 4022292SN/A 40310328Smitch.hayenga@arm.com DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n", 40410328Smitch.hayenga@arm.com inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size()); 4052292SN/A } 4062292SN/A 4072329SN/A // @todo: Eventually need to enforce this by not letting a thread 4082292SN/A // fetch past its skidbuffer 4092292SN/A assert(skidBuffer[tid].size() <= skidBufferMax); 4102292SN/A} 4112292SN/A 4122292SN/Atemplate<class Impl> 4132292SN/Abool 4142292SN/ADefaultDecode<Impl>::skidsEmpty() 4152292SN/A{ 4166221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4176221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4182292SN/A 4193867Sbinkertn@umich.edu while (threads != end) { 4206221Snate@binkert.org ThreadID tid = *threads++; 4213867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 4222292SN/A return false; 4232292SN/A } 4242292SN/A 4252292SN/A return true; 4262292SN/A} 4272292SN/A 4282292SN/Atemplate<class Impl> 4292292SN/Avoid 4302292SN/ADefaultDecode<Impl>::updateStatus() 4312292SN/A{ 4322292SN/A bool any_unblocking = false; 4332292SN/A 4346221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4356221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4362292SN/A 4373867Sbinkertn@umich.edu while (threads != end) { 4386221Snate@binkert.org ThreadID tid = *threads++; 4392292SN/A 4402292SN/A if (decodeStatus[tid] == Unblocking) { 4412292SN/A any_unblocking = true; 4422292SN/A break; 4432292SN/A } 4442292SN/A } 4452292SN/A 4462292SN/A // Decode will have activity if it's unblocking. 4472292SN/A if (any_unblocking) { 4482292SN/A if (_status == Inactive) { 4492292SN/A _status = Active; 4502292SN/A 4512292SN/A DPRINTF(Activity, "Activating stage.\n"); 4522292SN/A 4532733Sktlim@umich.edu cpu->activateStage(O3CPU::DecodeIdx); 4542292SN/A } 4552292SN/A } else { 4562292SN/A // If it's not unblocking, then decode will not have any internal 4572292SN/A // activity. Switch it to inactive. 4582292SN/A if (_status == Active) { 4592292SN/A _status = Inactive; 4602292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 4612292SN/A 4622733Sktlim@umich.edu cpu->deactivateStage(O3CPU::DecodeIdx); 4632292SN/A } 4642292SN/A } 4652292SN/A} 4662292SN/A 4672292SN/Atemplate <class Impl> 4682292SN/Avoid 4692292SN/ADefaultDecode<Impl>::sortInsts() 4702292SN/A{ 4712292SN/A int insts_from_fetch = fromFetch->size; 4722292SN/A for (int i = 0; i < insts_from_fetch; ++i) { 4732292SN/A insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); 4741060SN/A } 4751060SN/A} 4761060SN/A 4771060SN/Atemplate<class Impl> 4781060SN/Avoid 4796221Snate@binkert.orgDefaultDecode<Impl>::readStallSignals(ThreadID tid) 4801060SN/A{ 4812292SN/A if (fromRename->renameBlock[tid]) { 4822292SN/A stalls[tid].rename = true; 4832292SN/A } 4841060SN/A 4852292SN/A if (fromRename->renameUnblock[tid]) { 4862292SN/A assert(stalls[tid].rename); 4872292SN/A stalls[tid].rename = false; 4882292SN/A } 4892292SN/A} 4901060SN/A 4912292SN/Atemplate <class Impl> 4922292SN/Abool 4936221Snate@binkert.orgDefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid) 4942292SN/A{ 4952292SN/A // Check if there's a squash signal, squash if there is. 4962292SN/A // Check stall signals, block if necessary. 4972292SN/A // If status was blocked 4982292SN/A // Check if stall conditions have passed 4992292SN/A // if so then go to unblocking 5002292SN/A // If status was Squashing 5012292SN/A // check if squashing is not high. Switch to running this cycle. 5021060SN/A 5032292SN/A // Update the per thread stall statuses. 5042292SN/A readStallSignals(tid); 5051060SN/A 5062292SN/A // Check squash signals from commit. 5072292SN/A if (fromCommit->commitInfo[tid].squash) { 5081681SN/A 5092292SN/A DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash " 5102292SN/A "from commit.\n", tid); 5112292SN/A 5122292SN/A squash(tid); 5132292SN/A 5142292SN/A return true; 5152292SN/A } 5162292SN/A 5172292SN/A if (checkStall(tid)) { 5182292SN/A return block(tid); 5192292SN/A } 5202292SN/A 5212292SN/A if (decodeStatus[tid] == Blocked) { 5222292SN/A DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n", 5232292SN/A tid); 5242292SN/A 5252292SN/A decodeStatus[tid] = Unblocking; 5262292SN/A 5272292SN/A unblock(tid); 5282292SN/A 5292292SN/A return true; 5302292SN/A } 5312292SN/A 5322292SN/A if (decodeStatus[tid] == Squashing) { 5332292SN/A // Switch status to running if decode isn't being told to block or 5342292SN/A // squash this cycle. 5352292SN/A DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n", 5362292SN/A tid); 5372292SN/A 5382292SN/A decodeStatus[tid] = Running; 5392292SN/A 5402292SN/A return false; 5412292SN/A } 5422292SN/A 5432292SN/A // If we've reached this point, we have not gotten any signals that 5442292SN/A // cause decode to change its status. Decode remains the same as before. 5452292SN/A return false; 5462292SN/A} 5472292SN/A 5482292SN/Atemplate<class Impl> 5492292SN/Avoid 5502292SN/ADefaultDecode<Impl>::tick() 5512292SN/A{ 5522292SN/A wroteToTimeBuffer = false; 5532292SN/A 5542292SN/A bool status_change = false; 5552292SN/A 5562292SN/A toRenameIndex = 0; 5572292SN/A 5586221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5596221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5602292SN/A 5612292SN/A sortInsts(); 5622292SN/A 5632292SN/A //Check stall and squash signals. 5643867Sbinkertn@umich.edu while (threads != end) { 5656221Snate@binkert.org ThreadID tid = *threads++; 5662292SN/A 5672292SN/A DPRINTF(Decode,"Processing [tid:%i]\n",tid); 5682292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 5692292SN/A 5702292SN/A decode(status_change, tid); 5712292SN/A } 5722292SN/A 5732292SN/A if (status_change) { 5742292SN/A updateStatus(); 5752292SN/A } 5762292SN/A 5772292SN/A if (wroteToTimeBuffer) { 5782292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 5792292SN/A 5802292SN/A cpu->activityThisCycle(); 5811060SN/A } 5821060SN/A} 5831060SN/A 5841060SN/Atemplate<class Impl> 5851060SN/Avoid 5866221Snate@binkert.orgDefaultDecode<Impl>::decode(bool &status_change, ThreadID tid) 5871060SN/A{ 5882292SN/A // If status is Running or idle, 5892292SN/A // call decodeInsts() 5902292SN/A // If status is Unblocking, 5912292SN/A // buffer any instructions coming from fetch 5922292SN/A // continue trying to empty skid buffer 5932292SN/A // check if stall conditions have passed 5942292SN/A 5952292SN/A if (decodeStatus[tid] == Blocked) { 5962292SN/A ++decodeBlockedCycles; 5972292SN/A } else if (decodeStatus[tid] == Squashing) { 5982292SN/A ++decodeSquashCycles; 5991060SN/A } 6001060SN/A 6012292SN/A // Decode should try to decode as many instructions as its bandwidth 6022292SN/A // will allow, as long as it is not currently blocked. 6032292SN/A if (decodeStatus[tid] == Running || 6042292SN/A decodeStatus[tid] == Idle) { 6052935Sksewell@umich.edu DPRINTF(Decode, "[tid:%u]: Not blocked, so attempting to run " 6062292SN/A "stage.\n",tid); 6072292SN/A 6082292SN/A decodeInsts(tid); 6092292SN/A } else if (decodeStatus[tid] == Unblocking) { 6102292SN/A // Make sure that the skid buffer has something in it if the 6112292SN/A // status is unblocking. 6122292SN/A assert(!skidsEmpty()); 6132292SN/A 6142292SN/A // If the status was unblocking, then instructions from the skid 6152292SN/A // buffer were used. Remove those instructions and handle 6162292SN/A // the rest of unblocking. 6172292SN/A decodeInsts(tid); 6182292SN/A 6192292SN/A if (fetchInstsValid()) { 6202292SN/A // Add the current inputs to the skid buffer so they can be 6212292SN/A // reprocessed when this stage unblocks. 6222292SN/A skidInsert(tid); 6232292SN/A } 6242292SN/A 6252292SN/A status_change = unblock(tid) || status_change; 6261060SN/A } 6272292SN/A} 6281060SN/A 6292292SN/Atemplate <class Impl> 6302292SN/Avoid 6316221Snate@binkert.orgDefaultDecode<Impl>::decodeInsts(ThreadID tid) 6322292SN/A{ 6332292SN/A // Instructions can come either from the skid buffer or the list of 6342292SN/A // instructions coming from fetch, depending on decode's status. 6352292SN/A int insts_available = decodeStatus[tid] == Unblocking ? 6362292SN/A skidBuffer[tid].size() : insts[tid].size(); 6372292SN/A 6382292SN/A if (insts_available == 0) { 6392292SN/A DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out" 6402292SN/A " early.\n",tid); 6411060SN/A // Should I change the status to idle? 6421062SN/A ++decodeIdleCycles; 6431060SN/A return; 6442292SN/A } else if (decodeStatus[tid] == Unblocking) { 6452292SN/A DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid " 6462292SN/A "buffer.\n",tid); 6472292SN/A ++decodeUnblockCycles; 6482292SN/A } else if (decodeStatus[tid] == Running) { 6492292SN/A ++decodeRunCycles; 6501060SN/A } 6511060SN/A 6521061SN/A DynInstPtr inst; 6531061SN/A 6542292SN/A std::queue<DynInstPtr> 6552292SN/A &insts_to_decode = decodeStatus[tid] == Unblocking ? 6562292SN/A skidBuffer[tid] : insts[tid]; 6571061SN/A 6582292SN/A DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid); 6591060SN/A 6602292SN/A while (insts_available > 0 && toRenameIndex < decodeWidth) { 6612292SN/A assert(!insts_to_decode.empty()); 6621060SN/A 6632292SN/A inst = insts_to_decode.front(); 6641062SN/A 6652292SN/A insts_to_decode.pop(); 6661061SN/A 6672292SN/A DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with " 6687720Sgblack@eecs.umich.edu "PC %s\n", tid, inst->seqNum, inst->pcState()); 6691061SN/A 6701061SN/A if (inst->isSquashed()) { 6717720Sgblack@eecs.umich.edu DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %s is " 6721061SN/A "squashed, skipping.\n", 6737720Sgblack@eecs.umich.edu tid, inst->seqNum, inst->pcState()); 6741061SN/A 6751062SN/A ++decodeSquashedInsts; 6761062SN/A 6771061SN/A --insts_available; 6781061SN/A 6791061SN/A continue; 6801061SN/A } 6811060SN/A 6821681SN/A // Also check if instructions have no source registers. Mark 6831681SN/A // them as ready to issue at any time. Not sure if this check 6841681SN/A // should exist here or at a later stage; however it doesn't matter 6851681SN/A // too much for function correctness. 6861681SN/A if (inst->numSrcRegs() == 0) { 6871681SN/A inst->setCanIssue(); 6881681SN/A } 6891681SN/A 6901060SN/A // This current instruction is valid, so add it into the decode 6911060SN/A // queue. The next instruction may not be valid, so check to 6921060SN/A // see if branches were predicted correctly. 6932292SN/A toRename->insts[toRenameIndex] = inst; 6941061SN/A 6951061SN/A ++(toRename->size); 6962292SN/A ++toRenameIndex; 6972292SN/A ++decodeDecodedInsts; 6982292SN/A --insts_available; 6991060SN/A 7008471SGiacomo.Gabrielli@arm.com#if TRACING_ON 7019527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7029527SMatt.Horsnell@arm.com inst->decodeTick = curTick() - inst->fetchTick; 7039527SMatt.Horsnell@arm.com } 7048471SGiacomo.Gabrielli@arm.com#endif 7058471SGiacomo.Gabrielli@arm.com 7061060SN/A // Ensure that if it was predicted as a branch, it really is a 7071061SN/A // branch. 7083796Sgblack@eecs.umich.edu if (inst->readPredTaken() && !inst->isControl()) { 7091060SN/A panic("Instruction predicted as a branch!"); 7101060SN/A 7111062SN/A ++decodeControlMispred; 7122292SN/A 7131060SN/A // Might want to set some sort of boolean and just do 7141060SN/A // a check at the end 7152292SN/A squash(inst, inst->threadNumber); 7162292SN/A 7171060SN/A break; 7181060SN/A } 7191060SN/A 7201062SN/A // Go ahead and compute any PC-relative branches. 7211063SN/A if (inst->isDirectCtrl() && inst->isUncondCtrl()) { 7222307SN/A ++decodeBranchResolved; 7231062SN/A 7247720Sgblack@eecs.umich.edu if (!(inst->branchTarget() == inst->readPredTarg())) { 7251062SN/A ++decodeBranchMispred; 7262292SN/A 7271060SN/A // Might want to set some sort of boolean and just do 7281060SN/A // a check at the end 7292292SN/A squash(inst, inst->threadNumber); 7307720Sgblack@eecs.umich.edu TheISA::PCState target = inst->branchTarget(); 7316036Sksewell@umich.edu 7327720Sgblack@eecs.umich.edu DPRINTF(Decode, "[sn:%i]: Updating predictions: PredPC: %s\n", 7337720Sgblack@eecs.umich.edu inst->seqNum, target); 7346036Sksewell@umich.edu //The micro pc after an instruction level branch should be 0 7357720Sgblack@eecs.umich.edu inst->setPredTarg(target); 7362935Sksewell@umich.edu break; 7372935Sksewell@umich.edu } 7382935Sksewell@umich.edu } 7391060SN/A } 7401061SN/A 7412292SN/A // If we didn't process all instructions, then we will need to block 7422292SN/A // and put all those instructions into the skid buffer. 7432292SN/A if (!insts_to_decode.empty()) { 7442292SN/A block(tid); 7452292SN/A } 7462292SN/A 7472292SN/A // Record that decode has written to the time buffer for activity 7482292SN/A // tracking. 7492292SN/A if (toRenameIndex) { 7502292SN/A wroteToTimeBuffer = true; 7512292SN/A } 7521060SN/A} 7539944Smatt.horsnell@ARM.com 7549944Smatt.horsnell@ARM.com#endif//__CPU_O3_DECODE_IMPL_HH__ 755