cpu_policy.hh revision 2348 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_CPU_POLICY_HH__
30#define __CPU_O3_CPU_POLICY_HH__
31
32#include "cpu/o3/bpred_unit.hh"
33#include "cpu/o3/free_list.hh"
34#include "cpu/o3/inst_queue.hh"
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "cpu/o3/mem_dep_unit.hh"
38#include "cpu/o3/regfile.hh"
39#include "cpu/o3/rename_map.hh"
40#include "cpu/o3/rob.hh"
41#include "cpu/o3/store_set.hh"
42
43#include "cpu/o3/commit.hh"
44#include "cpu/o3/decode.hh"
45#include "cpu/o3/fetch.hh"
46#include "cpu/o3/iew.hh"
47#include "cpu/o3/rename.hh"
48
49#include "cpu/o3/comm.hh"
50
51/**
52 * Struct that defines the key classes to be used by the CPU.  All
53 * classes use the typedefs defined here to determine what are the
54 * classes of the other stages and communication buffers.  In order to
55 * change a structure such as the IQ, simply change the typedef here
56 * to use the desired class instead, and recompile.  In order to
57 * create a different CPU to be used simultaneously with this one, see
58 * the alpha_impl.hh file for instructions.
59 */
60template<class Impl>
61struct SimpleCPUPolicy
62{
63    /** Typedef for the branch prediction unit (which includes the BP,
64     * RAS, and BTB).
65     */
66    typedef BPredUnit<Impl> BPredUnit;
67    /** Typedef for the register file.  Most classes assume a unified
68     * physical register file.
69     */
70    typedef PhysRegFile<Impl> RegFile;
71    /** Typedef for the freelist of registers. */
72    typedef SimpleFreeList FreeList;
73    /** Typedef for the rename map. */
74    typedef SimpleRenameMap RenameMap;
75    /** Typedef for the ROB. */
76    typedef ROB<Impl> ROB;
77    /** Typedef for the instruction queue/scheduler. */
78    typedef InstructionQueue<Impl> IQ;
79    /** Typedef for the memory dependence unit. */
80    typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
81    /** Typedef for the LSQ. */
82    typedef LSQ<Impl> LSQ;
83    /** Typedef for the thread-specific LSQ units. */
84    typedef LSQUnit<Impl> LSQUnit;
85
86    /** Typedef for fetch. */
87    typedef DefaultFetch<Impl> Fetch;
88    /** Typedef for decode. */
89    typedef DefaultDecode<Impl> Decode;
90    /** Typedef for rename. */
91    typedef DefaultRename<Impl> Rename;
92    /** Typedef for Issue/Execute/Writeback. */
93    typedef DefaultIEW<Impl> IEW;
94    /** Typedef for commit. */
95    typedef DefaultCommit<Impl> Commit;
96
97    /** The struct for communication between fetch and decode. */
98    typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
99
100    /** The struct for communication between decode and rename. */
101    typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
102
103    /** The struct for communication between rename and IEW. */
104    typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
105
106    /** The struct for communication between IEW and commit. */
107    typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
108
109    /** The struct for communication within the IEW stage. */
110    typedef IssueStruct<Impl> IssueStruct;
111
112    /** The struct for all backwards communication. */
113    typedef TimeBufStruct<Impl> TimeStruct;
114
115};
116
117#endif //__CPU_O3_CPU_POLICY_HH__
118