cpu_policy.hh revision 2665
11689SN/A/*
21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
311755SN/A#ifndef __CPU_O3_CPU_CPU_POLICY_HH__
321755SN/A#define __CPU_O3_CPU_CPU_POLICY_HH__
331060SN/A
341717SN/A#include "cpu/o3/bpred_unit.hh"
351717SN/A#include "cpu/o3/free_list.hh"
361717SN/A#include "cpu/o3/inst_queue.hh"
371717SN/A#include "cpu/o3/ldstq.hh"
381717SN/A#include "cpu/o3/mem_dep_unit.hh"
391717SN/A#include "cpu/o3/regfile.hh"
401717SN/A#include "cpu/o3/rename_map.hh"
411717SN/A#include "cpu/o3/rob.hh"
421717SN/A#include "cpu/o3/store_set.hh"
431061SN/A
441717SN/A#include "cpu/o3/commit.hh"
451717SN/A#include "cpu/o3/decode.hh"
461717SN/A#include "cpu/o3/fetch.hh"
471717SN/A#include "cpu/o3/iew.hh"
481717SN/A#include "cpu/o3/rename.hh"
491060SN/A
501717SN/A#include "cpu/o3/comm.hh"
511060SN/A
521060SN/Atemplate<class Impl>
531060SN/Astruct SimpleCPUPolicy
541060SN/A{
551062SN/A    typedef TwobitBPredUnit<Impl> BPredUnit;
561060SN/A    typedef PhysRegFile<Impl> RegFile;
571060SN/A    typedef SimpleFreeList FreeList;
581060SN/A    typedef SimpleRenameMap RenameMap;
591060SN/A    typedef ROB<Impl> ROB;
601060SN/A    typedef InstructionQueue<Impl> IQ;
611061SN/A    typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
621061SN/A    typedef LDSTQ<Impl> LDSTQ;
631060SN/A
641060SN/A    typedef SimpleFetch<Impl> Fetch;
651060SN/A    typedef SimpleDecode<Impl> Decode;
661060SN/A    typedef SimpleRename<Impl> Rename;
671681SN/A    typedef SimpleIEW<Impl> IEW;
681060SN/A    typedef SimpleCommit<Impl> Commit;
691061SN/A
701061SN/A    /** The struct for communication between fetch and decode. */
711061SN/A    typedef SimpleFetchSimpleDecode<Impl> FetchStruct;
721061SN/A
731061SN/A    /** The struct for communication between decode and rename. */
741061SN/A    typedef SimpleDecodeSimpleRename<Impl> DecodeStruct;
751061SN/A
761061SN/A    /** The struct for communication between rename and IEW. */
771061SN/A    typedef SimpleRenameSimpleIEW<Impl> RenameStruct;
781061SN/A
791061SN/A    /** The struct for communication between IEW and commit. */
801061SN/A    typedef SimpleIEWSimpleCommit<Impl> IEWStruct;
811061SN/A
821061SN/A    /** The struct for communication within the IEW stage. */
831061SN/A    typedef IssueStruct<Impl> IssueStruct;
841061SN/A
851061SN/A    /** The struct for all backwards communication. */
861061SN/A    typedef TimeBufStruct TimeStruct;
871061SN/A
881060SN/A};
891060SN/A
901755SN/A#endif //__CPU_O3_CPU_CPU_POLICY_HH__
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