cpu.hh revision 9444
11689SN/A/*
29783Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited
37598Sminkyu.jeong@arm.com * All rights reserved
47598Sminkyu.jeong@arm.com *
57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall
67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual
77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating
87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software
97598Sminkyu.jeong@arm.com * licensed hereunder.  You may use the software subject to the license
107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated
117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software,
127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form.
137598Sminkyu.jeong@arm.com *
142326SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
151689SN/A * Copyright (c) 2011 Regents of the University of California
161689SN/A * All rights reserved.
171689SN/A *
181689SN/A * Redistribution and use in source and binary forms, with or without
191689SN/A * modification, are permitted provided that the following conditions are
201689SN/A * met: redistributions of source code must retain the above copyright
211689SN/A * notice, this list of conditions and the following disclaimer;
221689SN/A * redistributions in binary form must reproduce the above copyright
231689SN/A * notice, this list of conditions and the following disclaimer in the
241689SN/A * documentation and/or other materials provided with the distribution;
251689SN/A * neither the name of the copyright holders nor the names of its
261689SN/A * contributors may be used to endorse or promote products derived from
271689SN/A * this software without specific prior written permission.
281689SN/A *
291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402665Ssaidi@eecs.umich.edu *
411689SN/A * Authors: Kevin Lim
421689SN/A *          Korey Sewell
439944Smatt.horsnell@ARM.com *          Rick Strong
449944Smatt.horsnell@ARM.com */
459944Smatt.horsnell@ARM.com
461060SN/A#ifndef __CPU_O3_CPU_HH__
471060SN/A#define __CPU_O3_CPU_HH__
481689SN/A
491060SN/A#include <iostream>
501060SN/A#include <list>
511060SN/A#include <queue>
528230Snate@binkert.org#include <set>
536658Snate@binkert.org#include <vector>
548887Sgeoffrey.blake@arm.com
552292SN/A#include "arch/types.hh"
561717SN/A#include "base/statistics.hh"
578229Snate@binkert.org#include "config/the_isa.hh"
588232Snate@binkert.org#include "cpu/o3/comm.hh"
599444SAndreas.Sandberg@ARM.com#include "cpu/o3/cpu_policy.hh"
608232Snate@binkert.org#include "cpu/o3/scoreboard.hh"
619527SMatt.Horsnell@arm.com#include "cpu/o3/thread_state.hh"
625529Snate@binkert.org#include "cpu/activity.hh"
631060SN/A#include "cpu/base.hh"
646221Snate@binkert.org#include "cpu/simple_thread.hh"
656221Snate@binkert.org#include "cpu/timebuf.hh"
661681SN/A//#include "cpu/o3/thread_context.hh"
675529Snate@binkert.org#include "params/DerivO3CPU.hh"
682873Sktlim@umich.edu#include "sim/process.hh"
694329Sktlim@umich.edu
704329Sktlim@umich.edutemplate <class>
714329Sktlim@umich.educlass Checker;
722292SN/Aclass ThreadContext;
732292SN/Atemplate <class>
742292SN/Aclass O3ThreadContext;
752292SN/A
762820Sktlim@umich.educlass Checkpoint;
772292SN/Aclass MemObject;
782820Sktlim@umich.educlass Process;
792820Sktlim@umich.edu
809444SAndreas.Sandberg@ARM.comstruct BaseCPUParams;
811060SN/A
8210172Sdam.sunwoo@arm.comclass BaseO3CPU : public BaseCPU
8310172Sdam.sunwoo@arm.com{
8410172Sdam.sunwoo@arm.com    //Stuff that's pretty ISA independent will go here.
8510172Sdam.sunwoo@arm.com  public:
8610172Sdam.sunwoo@arm.com    BaseO3CPU(BaseCPUParams *params);
8710172Sdam.sunwoo@arm.com
8810172Sdam.sunwoo@arm.com    void regStats();
8910172Sdam.sunwoo@arm.com};
9010172Sdam.sunwoo@arm.com
9110172Sdam.sunwoo@arm.com/**
9210172Sdam.sunwoo@arm.com * FullO3CPU class, has each of the stages (fetch through commit)
9310172Sdam.sunwoo@arm.com * within it, as well as all of the time buffers between stages.  The
9410172Sdam.sunwoo@arm.com * tick() function for the CPU is defined here.
952292SN/A */
962292SN/Atemplate <class Impl>
972292SN/Aclass FullO3CPU : public BaseO3CPU
981060SN/A{
991060SN/A  public:
1001060SN/A    // Typedefs from the Impl here.
1011060SN/A    typedef typename Impl::CPUPol CPUPolicy;
1021060SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
1031060SN/A    typedef typename Impl::O3CPU O3CPU;
1041681SN/A
1056221Snate@binkert.org    typedef O3ThreadState<Impl> ImplState;
1066221Snate@binkert.org    typedef O3ThreadState<Impl> Thread;
1076221Snate@binkert.org
1086221Snate@binkert.org    typedef typename std::list<DynInstPtr>::iterator ListIt;
1092292SN/A
1102292SN/A    friend class O3ThreadContext<Impl>;
1112820Sktlim@umich.edu
1122820Sktlim@umich.edu  public:
1132292SN/A    enum Status {
1142292SN/A        Running,
1152820Sktlim@umich.edu        Idle,
1162820Sktlim@umich.edu        Halted,
1172292SN/A        Blocked,
1182292SN/A        SwitchedOut
1192292SN/A    };
1202292SN/A
1212292SN/A    TheISA::TLB * itb;
1222292SN/A    TheISA::TLB * dtb;
1232292SN/A
1242292SN/A    /** Overall CPU status. */
1251060SN/A    Status _status;
1261060SN/A
1271681SN/A  private:
1281062SN/A
12910023Smatt.horsnell@ARM.com    /**
13010023Smatt.horsnell@ARM.com     * IcachePort class for instruction fetch.
13110023Smatt.horsnell@ARM.com     */
13210023Smatt.horsnell@ARM.com    class IcachePort : public CpuPort
13310023Smatt.horsnell@ARM.com    {
13410023Smatt.horsnell@ARM.com      protected:
13510023Smatt.horsnell@ARM.com        /** Pointer to fetch. */
13610023Smatt.horsnell@ARM.com        DefaultFetch<Impl> *fetch;
1372292SN/A
1381062SN/A      public:
1392301SN/A        /** Default constructor. */
1402301SN/A        IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
1411062SN/A            : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
1422727Sktlim@umich.edu        { }
1431062SN/A
1441062SN/A      protected:
1451062SN/A
1461062SN/A        /** Timing version of receive.  Handles setting fetch to the
1471062SN/A         * proper status to start fetching. */
1481062SN/A        virtual bool recvTimingResp(PacketPtr pkt);
1491062SN/A        virtual void recvTimingSnoopReq(PacketPtr pkt) { }
1501062SN/A
1511062SN/A        /** Handles doing a retry of a failed fetch. */
1521062SN/A        virtual void recvRetry();
1531062SN/A    };
1541062SN/A
1551062SN/A    /**
1561062SN/A     * DcachePort class for the load/store queue.
1571062SN/A     */
1581062SN/A    class DcachePort : public CpuPort
1591062SN/A    {
1601062SN/A      protected:
1611062SN/A
1621062SN/A        /** Pointer to LSQ. */
1631062SN/A        LSQ<Impl> *lsq;
1641062SN/A
1651062SN/A      public:
1661062SN/A        /** Default constructor. */
1671062SN/A        DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
1681062SN/A            : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
1691062SN/A        { }
1701062SN/A
1711062SN/A      protected:
1721062SN/A
1731062SN/A        /** Timing version of receive.  Handles writing back and
1741062SN/A         * completing the load or store that has returned from
1751062SN/A         * memory. */
1761062SN/A        virtual bool recvTimingResp(PacketPtr pkt);
1771062SN/A        virtual void recvTimingSnoopReq(PacketPtr pkt);
1781062SN/A
1791062SN/A        /** Handles doing a retry of the previous send. */
1801062SN/A        virtual void recvRetry();
1811062SN/A
1821062SN/A        /**
1831062SN/A         * As this CPU requires snooping to maintain the load store queue
1842292SN/A         * change the behaviour from the base CPU port.
1852292SN/A         *
1862292SN/A         * @return true since we have to snoop
1872292SN/A         */
1881062SN/A        virtual bool isSnooping() const { return true; }
1891062SN/A    };
1901062SN/A
1911062SN/A    class TickEvent : public Event
1921062SN/A    {
1931062SN/A      private:
1941062SN/A        /** Pointer to the CPU. */
1952292SN/A        FullO3CPU<Impl> *cpu;
1962292SN/A
1972292SN/A      public:
1982292SN/A        /** Constructs a tick event. */
1992292SN/A        TickEvent(FullO3CPU<Impl> *c);
2002292SN/A
2012292SN/A        /** Processes a tick event, calling tick() on the CPU. */
2022292SN/A        void process();
2032292SN/A        /** Returns the description of the tick event. */
2042292SN/A        const char *description() const;
2052301SN/A    };
2062727Sktlim@umich.edu
2072353SN/A    /** The tick event used for scheduling CPU ticks. */
2082727Sktlim@umich.edu    TickEvent tickEvent;
2092727Sktlim@umich.edu
2102727Sktlim@umich.edu    /** Schedule tick event, regardless of its current state. */
2116221Snate@binkert.org    void scheduleTickEvent(Cycles delay)
2122353SN/A    {
2132727Sktlim@umich.edu        if (tickEvent.squashed())
2142727Sktlim@umich.edu            reschedule(tickEvent, clockEdge(delay));
2152727Sktlim@umich.edu        else if (!tickEvent.scheduled())
2162727Sktlim@umich.edu            schedule(tickEvent, clockEdge(delay));
2172353SN/A    }
2182727Sktlim@umich.edu
2192727Sktlim@umich.edu    /** Unschedule tick event, regardless of its current state. */
2202727Sktlim@umich.edu    void unscheduleTickEvent()
2216221Snate@binkert.org    {
2228240Snate@binkert.org        if (tickEvent.scheduled())
2232301SN/A            tickEvent.squash();
2242727Sktlim@umich.edu    }
2252301SN/A
2262727Sktlim@umich.edu    class ActivateThreadEvent : public Event
2276221Snate@binkert.org    {
2288240Snate@binkert.org      private:
2292301SN/A        /** Number of Thread to Activate */
2302727Sktlim@umich.edu        ThreadID tid;
2312301SN/A
2322727Sktlim@umich.edu        /** Pointer to the CPU. */
2336221Snate@binkert.org        FullO3CPU<Impl> *cpu;
2348240Snate@binkert.org
2352301SN/A      public:
2362727Sktlim@umich.edu        /** Constructs the event. */
2372301SN/A        ActivateThreadEvent();
2382727Sktlim@umich.edu
2396221Snate@binkert.org        /** Initialize Event */
2408240Snate@binkert.org        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
2412301SN/A
2422727Sktlim@umich.edu        /** Processes the event, calling activateThread() on the CPU. */
2432301SN/A        void process();
2442301SN/A
2458240Snate@binkert.org        /** Returns the description of the event. */
2462301SN/A        const char *description() const;
2472727Sktlim@umich.edu    };
2482727Sktlim@umich.edu
2492727Sktlim@umich.edu    /** Schedule thread to activate , regardless of its current state. */
2502727Sktlim@umich.edu    void
2518240Snate@binkert.org    scheduleActivateThreadEvent(ThreadID tid, Cycles delay)
2522727Sktlim@umich.edu    {
2532727Sktlim@umich.edu        // Schedule thread to activate, regardless of its current state.
2542727Sktlim@umich.edu        if (activateThreadEvent[tid].squashed())
2552727Sktlim@umich.edu            reschedule(activateThreadEvent[tid],
2562301SN/A                       clockEdge(delay));
2572301SN/A        else if (!activateThreadEvent[tid].scheduled()) {
2586221Snate@binkert.org            Tick when = clockEdge(delay);
2598240Snate@binkert.org
2602301SN/A            // Check if the deallocateEvent is also scheduled, and make
2612727Sktlim@umich.edu            // sure they do not happen at same time causing a sleep that
2622301SN/A            // is never woken from.
2632326SN/A            if (deallocateContextEvent[tid].scheduled() &&
2646221Snate@binkert.org                deallocateContextEvent[tid].when() == when) {
2658240Snate@binkert.org                when++;
2662301SN/A            }
2672727Sktlim@umich.edu
2682301SN/A            schedule(activateThreadEvent[tid], when);
2692326SN/A        }
2706221Snate@binkert.org    }
2718240Snate@binkert.org
2722301SN/A    /** Unschedule actiavte thread event, regardless of its current state. */
2732727Sktlim@umich.edu    void
2742301SN/A    unscheduleActivateThreadEvent(ThreadID tid)
2752326SN/A    {
2766221Snate@binkert.org        if (activateThreadEvent[tid].scheduled())
2778240Snate@binkert.org            activateThreadEvent[tid].squash();
2782301SN/A    }
2792727Sktlim@umich.edu
2802301SN/A    /** The tick event used for scheduling CPU ticks. */
2812326SN/A    ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
2826221Snate@binkert.org
2838240Snate@binkert.org    class DeallocateContextEvent : public Event
2842301SN/A    {
2852727Sktlim@umich.edu      private:
2862301SN/A        /** Number of Thread to deactivate */
2872326SN/A        ThreadID tid;
2888240Snate@binkert.org
2892301SN/A        /** Should the thread be removed from the CPU? */
2902727Sktlim@umich.edu        bool remove;
2912301SN/A
2922326SN/A        /** Pointer to the CPU. */
2932301SN/A        FullO3CPU<Impl> *cpu;
2942326SN/A
2958240Snate@binkert.org      public:
2962301SN/A        /** Constructs the event. */
2972727Sktlim@umich.edu        DeallocateContextEvent();
2982301SN/A
2992326SN/A        /** Initialize Event */
3002301SN/A        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
3012326SN/A
3028240Snate@binkert.org        /** Processes the event, calling activateThread() on the CPU. */
3032301SN/A        void process();
3042727Sktlim@umich.edu
3052326SN/A        /** Sets whether the thread should also be removed from the CPU. */
3061062SN/A        void setRemove(bool _remove) { remove = _remove; }
3071062SN/A
3081681SN/A        /** Returns the description of the event. */
3091060SN/A        const char *description() const;
3109427SAndreas.Sandberg@ARM.com    };
3111060SN/A
3126221Snate@binkert.org    /** Schedule cpu to deallocate thread context.*/
3132292SN/A    void
3142292SN/A    scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay)
3152292SN/A    {
3162292SN/A        // Schedule thread to activate, regardless of its current state.
3172292SN/A        if (deallocateContextEvent[tid].squashed())
3182292SN/A            reschedule(deallocateContextEvent[tid],
3192292SN/A                       clockEdge(delay));
3202292SN/A        else if (!deallocateContextEvent[tid].scheduled())
3212292SN/A            schedule(deallocateContextEvent[tid],
3228887Sgeoffrey.blake@arm.com                     clockEdge(delay));
3238733Sgeoffrey.blake@arm.com    }
3248850Sandreas.hansson@arm.com
3258887Sgeoffrey.blake@arm.com    /** Unschedule thread deallocation in CPU */
3268733Sgeoffrey.blake@arm.com    void
3272733Sktlim@umich.edu    unscheduleDeallocateContextEvent(ThreadID tid)
3281060SN/A    {
3291060SN/A        if (deallocateContextEvent[tid].scheduled())
3301681SN/A            deallocateContextEvent[tid].squash();
3311060SN/A    }
3322292SN/A
3331060SN/A    /** The tick event used for scheduling CPU ticks. */
3341060SN/A    DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
3351060SN/A
3361060SN/A    /**
3371060SN/A     * Check if the pipeline has drained and signal the DrainManager.
3381060SN/A     *
3391060SN/A     * This method checks if a drain has been requested and if the CPU
3401060SN/A     * has drained successfully (i.e., there are no instructions in
3411060SN/A     * the pipeline). If the CPU has drained, it deschedules the tick
3422292SN/A     * event and signals the drain manager.
3432292SN/A     *
3441060SN/A     * @return False if a drain hasn't been requested or the CPU
3451060SN/A     * hasn't drained, true otherwise.
3461060SN/A     */
3471060SN/A    bool tryDrain();
3481681SN/A
3491060SN/A    /**
3502292SN/A     * Perform sanity checks after a drain.
3511060SN/A     *
3521060SN/A     * This method is called from drain() when it has determined that
3531060SN/A     * the CPU is fully drained when gem5 is compiled with the NDEBUG
3541060SN/A     * macro undefined. The intention of this method is to do more
3551060SN/A     * extensive tests than the isDrained() method to weed out any
3561060SN/A     * draining bugs.
3571060SN/A     */
3581681SN/A    void drainSanityCheck() const;
3591060SN/A
3602292SN/A    /** Check if a system is in a drained state. */
3611060SN/A    bool isDrained() const;
3621060SN/A
3631060SN/A  public:
3641060SN/A    /** Constructs a CPU with the given parameters. */
3651060SN/A    FullO3CPU(DerivO3CPUParams *params);
3661060SN/A    /** Destructor. */
3671060SN/A    ~FullO3CPU();
3681681SN/A
3691060SN/A    /** Registers statistics. */
3706221Snate@binkert.org    void regStats();
3711060SN/A
3722292SN/A    void demapPage(Addr vaddr, uint64_t asn)
3732292SN/A    {
3742292SN/A        this->itb->demapPage(vaddr, asn);
3752292SN/A        this->dtb->demapPage(vaddr, asn);
3761060SN/A    }
3771060SN/A
3781681SN/A    void demapInstPage(Addr vaddr, uint64_t asn)
3791060SN/A    {
3802292SN/A        this->itb->demapPage(vaddr, asn);
3811060SN/A    }
3822292SN/A
3831060SN/A    void demapDataPage(Addr vaddr, uint64_t asn)
3841060SN/A    {
3852307SN/A        this->dtb->demapPage(vaddr, asn);
3862863Sktlim@umich.edu    }
3879444SAndreas.Sandberg@ARM.com
3882307SN/A    /** Ticks CPU, calling tick() on each stage, and checking the overall
3899444SAndreas.Sandberg@ARM.com     *  activity to see if the CPU should deschedule itself.
3909444SAndreas.Sandberg@ARM.com     */
3919444SAndreas.Sandberg@ARM.com    void tick();
3929444SAndreas.Sandberg@ARM.com
3939444SAndreas.Sandberg@ARM.com    /** Initialize the CPU */
3949444SAndreas.Sandberg@ARM.com    void init();
3959444SAndreas.Sandberg@ARM.com
3969444SAndreas.Sandberg@ARM.com    void startup();
3979444SAndreas.Sandberg@ARM.com
3989444SAndreas.Sandberg@ARM.com    /** Returns the Number of Active Threads in the CPU */
3999444SAndreas.Sandberg@ARM.com    int numActiveThreads()
4009444SAndreas.Sandberg@ARM.com    { return activeThreads.size(); }
4019444SAndreas.Sandberg@ARM.com
4029783Sandreas.hansson@arm.com    /** Add Thread to Active Threads List */
4039783Sandreas.hansson@arm.com    void activateThread(ThreadID tid);
4049783Sandreas.hansson@arm.com
4059783Sandreas.hansson@arm.com    /** Remove Thread from Active Threads List */
4069783Sandreas.hansson@arm.com    void deactivateThread(ThreadID tid);
4079783Sandreas.hansson@arm.com
4089783Sandreas.hansson@arm.com    /** Setup CPU to insert a thread's context */
4099783Sandreas.hansson@arm.com    void insertThread(ThreadID tid);
4109444SAndreas.Sandberg@ARM.com
4111681SN/A    /** Remove all of a thread's context from CPU */
4121681SN/A    void removeThread(ThreadID tid);
4132316SN/A
4141681SN/A    /** Count the Total Instructions Committed in the CPU. */
4159444SAndreas.Sandberg@ARM.com    virtual Counter totalInsts() const;
4162843Sktlim@umich.edu
4179444SAndreas.Sandberg@ARM.com    /** Count the Total Ops (including micro ops) committed in the CPU. */
4182843Sktlim@umich.edu    virtual Counter totalOps() const;
4199444SAndreas.Sandberg@ARM.com
4209444SAndreas.Sandberg@ARM.com    /** Add Thread to Active Threads List. */
4211681SN/A    void activateContext(ThreadID tid, Cycles delay);
4221681SN/A
4232307SN/A    /** Remove Thread from Active Threads List */
4241681SN/A    void suspendContext(ThreadID tid);
4252307SN/A
4261060SN/A    /** Remove Thread from Active Threads List &&
4272348SN/A     *  Possibly Remove Thread Context from CPU.
4282307SN/A     */
4292307SN/A    bool scheduleDeallocateContext(ThreadID tid, bool remove,
4302307SN/A                                   Cycles delay = Cycles(1));
4311060SN/A
4322307SN/A    /** Remove Thread from Active Threads List &&
4332307SN/A     *  Remove Thread Context from CPU.
4349444SAndreas.Sandberg@ARM.com     */
4351060SN/A    void haltContext(ThreadID tid);
4369427SAndreas.Sandberg@ARM.com
4372307SN/A    /** Activate a Thread When CPU Resources are Available. */
4381060SN/A    void activateWhenReady(ThreadID tid);
4396221Snate@binkert.org
4406221Snate@binkert.org    /** Add or Remove a Thread Context in the CPU. */
4416221Snate@binkert.org    void doContextSwitch();
4426221Snate@binkert.org
4432307SN/A    /** Update The Order In Which We Process Threads. */
4441060SN/A    void updateThreadPriority();
4452307SN/A
4462307SN/A    /** Is the CPU draining? */
4472873Sktlim@umich.edu    bool isDraining() const { return getDrainState() == Drainable::Draining; }
4482307SN/A
4491060SN/A    /** Serialize state. */
4501060SN/A    virtual void serialize(std::ostream &os);
4511060SN/A
4521681SN/A    /** Unserialize from a checkpoint. */
4531060SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
4546221Snate@binkert.org
4552107SN/A  public:
4566221Snate@binkert.org    /** Executes a syscall.
4572107SN/A     * @todo: Determine if this needs to be virtual.
4582292SN/A     */
4592292SN/A    void syscall(int64_t callnum, ThreadID tid);
4602107SN/A
4612292SN/A    /** Starts draining the CPU's pipeline of all instructions in
4622326SN/A     * order to stop all memory accesses. */
4632292SN/A    unsigned int drain(DrainManager *drain_manager);
4642107SN/A
4652292SN/A    /** Resumes execution after a drain. */
4662935Sksewell@umich.edu    void drainResume();
4674632Sgblack@eecs.umich.edu
4682935Sksewell@umich.edu    /**
4692292SN/A     * Commit has reached a safe point to drain a thread.
4702292SN/A     *
4712292SN/A     * Commit calls this method to inform the pipeline that it has
4722292SN/A     * reached a point where it is not executed microcode and is about
4732292SN/A     * to squash uncommitted instructions to fully drain the pipeline.
4742107SN/A     */
4752292SN/A    void commitDrained(ThreadID tid);
4762107SN/A
4772292SN/A    /** Switches out this CPU. */
4782292SN/A    virtual void switchOut();
4792107SN/A
4802702Sktlim@umich.edu    /** Takes over from another CPU. */
4812107SN/A    virtual void takeOverFrom(BaseCPU *oldCPU);
4822107SN/A
4832107SN/A    /** Get the current instruction sequence number, and increment it. */
4842107SN/A    InstSeqNum getAndIncrementInstSeq()
4856221Snate@binkert.org    { return globalSeqNum++; }
4862292SN/A
4877720Sgblack@eecs.umich.edu    /** Traps to handle given fault. */
4887720Sgblack@eecs.umich.edu    void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
4892292SN/A
4907852SMatt.Horsnell@arm.com    /** HW return from error interrupt. */
4917852SMatt.Horsnell@arm.com    Fault hwrei(ThreadID tid);
4927852SMatt.Horsnell@arm.com
4937852SMatt.Horsnell@arm.com    bool simPalCheck(int palFunc, ThreadID tid);
4947852SMatt.Horsnell@arm.com
4952935Sksewell@umich.edu    /** Returns the Fault for any valid interrupt. */
4967852SMatt.Horsnell@arm.com    Fault getInterrupts();
4977852SMatt.Horsnell@arm.com
4982292SN/A    /** Processes any an interrupt fault. */
4997852SMatt.Horsnell@arm.com    void processInterrupts(Fault interrupt);
5007852SMatt.Horsnell@arm.com
5017852SMatt.Horsnell@arm.com    /** Halts the CPU. */
5022292SN/A    void halt() { panic("Halt not implemented!\n"); }
5037852SMatt.Horsnell@arm.com
5047852SMatt.Horsnell@arm.com    /** Check if this address is a valid instruction address. */
5057852SMatt.Horsnell@arm.com    bool validInstAddr(Addr addr) { return true; }
5062292SN/A
5072292SN/A    /** Check if this address is a valid data address. */
5082292SN/A    bool validDataAddr(Addr addr) { return true; }
5092292SN/A
5106221Snate@binkert.org    /** Register accessors.  Index refers to the physical register index. */
5112292SN/A
5128513SGiacomo.Gabrielli@arm.com    /** Reads a miscellaneous register. */
5138513SGiacomo.Gabrielli@arm.com    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
5148513SGiacomo.Gabrielli@arm.com
5158513SGiacomo.Gabrielli@arm.com    /** Reads a misc. register, including any side effects the read
5168513SGiacomo.Gabrielli@arm.com     * might have as defined by the architecture.
5178513SGiacomo.Gabrielli@arm.com     */
5188513SGiacomo.Gabrielli@arm.com    TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
5198513SGiacomo.Gabrielli@arm.com
5208513SGiacomo.Gabrielli@arm.com    /** Sets a miscellaneous register. */
5218513SGiacomo.Gabrielli@arm.com    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
5228513SGiacomo.Gabrielli@arm.com            ThreadID tid);
5232292SN/A
5247852SMatt.Horsnell@arm.com    /** Sets a misc. register, including any side effects the write
5258513SGiacomo.Gabrielli@arm.com     * might have as defined by the architecture.
5268137SAli.Saidi@ARM.com     */
5272292SN/A    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
5288513SGiacomo.Gabrielli@arm.com            ThreadID tid);
5298513SGiacomo.Gabrielli@arm.com
5302292SN/A    uint64_t readIntReg(int reg_idx);
5317852SMatt.Horsnell@arm.com
5327852SMatt.Horsnell@arm.com    TheISA::FloatReg readFloatReg(int reg_idx);
5332292SN/A
5342292SN/A    TheISA::FloatRegBits readFloatRegBits(int reg_idx);
5352292SN/A
5362292SN/A    void setIntReg(int reg_idx, uint64_t val);
5376221Snate@binkert.org
5382292SN/A    void setFloatReg(int reg_idx, TheISA::FloatReg val);
5392292SN/A
5407720Sgblack@eecs.umich.edu    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
5417852SMatt.Horsnell@arm.com
5427852SMatt.Horsnell@arm.com    uint64_t readArchIntReg(int reg_idx, ThreadID tid);
5437852SMatt.Horsnell@arm.com
5442292SN/A    float readArchFloatReg(int reg_idx, ThreadID tid);
5457852SMatt.Horsnell@arm.com
5467852SMatt.Horsnell@arm.com    uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
5478137SAli.Saidi@ARM.com
5482292SN/A    /** Architectural register accessors.  Looks up in the commit
5497852SMatt.Horsnell@arm.com     * rename table to obtain the true physical index of the
5507852SMatt.Horsnell@arm.com     * architected register first, then accesses that physical
5512292SN/A     * register.
5527852SMatt.Horsnell@arm.com     */
5532292SN/A    void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
5547852SMatt.Horsnell@arm.com
5557852SMatt.Horsnell@arm.com    void setArchFloatReg(int reg_idx, float val, ThreadID tid);
5562292SN/A
5572292SN/A    void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
5582292SN/A
5592292SN/A    /** Sets the commit PC state of a specific thread. */
5606221Snate@binkert.org    void pcState(const TheISA::PCState &newPCState, ThreadID tid);
5612292SN/A
5622292SN/A    /** Reads the commit PC state of a specific thread. */
5632292SN/A    TheISA::PCState pcState(ThreadID tid);
5642292SN/A
5652292SN/A    /** Reads the commit PC of a specific thread. */
5662292SN/A    Addr instAddr(ThreadID tid);
5672292SN/A
5682292SN/A    /** Reads the commit micro PC of a specific thread. */
5692292SN/A    MicroPC microPC(ThreadID tid);
5702292SN/A
5712292SN/A    /** Reads the next PC of a specific thread. */
5722292SN/A    Addr nextInstAddr(ThreadID tid);
5732292SN/A
5742292SN/A    /** Initiates a squash of all in-flight instructions for a given
5752292SN/A     * thread.  The source of the squash is an external update of
5762292SN/A     * state through the TC.
5772292SN/A     */
5782292SN/A    void squashFromTC(ThreadID tid);
5796221Snate@binkert.org
5802292SN/A    /** Function to add instruction onto the head of the list of the
5812292SN/A     *  instructions.  Used when new instructions are fetched.
5822292SN/A     */
5832292SN/A    ListIt addInst(DynInstPtr &inst);
5842292SN/A
5852292SN/A    /** Function to tell the CPU that an instruction has completed. */
5862292SN/A    void instDone(ThreadID tid, DynInstPtr &inst);
5872292SN/A
5882292SN/A    /** Remove an instruction from the front end of the list.  There's
5892292SN/A     *  no restriction on location of the instruction.
5902292SN/A     */
5912292SN/A    void removeFrontInst(DynInstPtr &inst);
5922292SN/A
5932292SN/A    /** Remove all instructions that are not currently in the ROB.
5942292SN/A     *  There's also an option to not squash delay slot instructions.*/
5952292SN/A    void removeInstsNotInROB(ThreadID tid);
5962292SN/A
5971060SN/A    /** Remove all instructions younger than the given sequence number. */
5981681SN/A    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
5991060SN/A
6001060SN/A    /** Removes the instruction pointed to by the iterator. */
6012292SN/A    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
6022292SN/A
6032292SN/A    /** Cleans up all instructions on the remove list. */
6042292SN/A    void cleanUpRemovedInsts();
6052292SN/A
6062292SN/A    /** Debug function to print all instructions on the list. */
6071681SN/A    void dumpInsts();
6081681SN/A
6091060SN/A  public:
6102292SN/A#ifndef NDEBUG
6111060SN/A    /** Count of total number of dynamic instructions in flight. */
6122292SN/A    int instcount;
6132292SN/A#endif
6141060SN/A
6152292SN/A    /** List of all the instructions in flight. */
6162292SN/A    std::list<DynInstPtr> instList;
6172292SN/A
6182292SN/A    /** List of all the instructions that will be removed at the end of this
6193221Sktlim@umich.edu     *  cycle.
6203221Sktlim@umich.edu     */
6213221Sktlim@umich.edu    std::queue<ListIt> removeList;
6223221Sktlim@umich.edu
6233221Sktlim@umich.edu#ifdef DEBUG
6242292SN/A    /** Debug structure to keep track of the sequence numbers still in
6252292SN/A     * flight.
6262292SN/A     */
6272292SN/A    std::set<InstSeqNum> snList;
6282326SN/A#endif
6292292SN/A
6302292SN/A    /** Records if instructions need to be removed this cycle due to
6312820Sktlim@umich.edu     *  being retired or squashed.
6322292SN/A     */
6332292SN/A    bool removeInstsThisCycle;
6342292SN/A
6352292SN/A  protected:
6362353SN/A    /** The fetch stage. */
6372292SN/A    typename CPUPolicy::Fetch fetch;
6382292SN/A
6392353SN/A    /** The decode stage. */
6402353SN/A    typename CPUPolicy::Decode decode;
6412292SN/A
6422292SN/A    /** The dispatch stage. */
6432292SN/A    typename CPUPolicy::Rename rename;
6442292SN/A
6452292SN/A    /** The issue/execute/writeback stages. */
6462292SN/A    typename CPUPolicy::IEW iew;
6472292SN/A
6482292SN/A    /** The commit stage. */
6492292SN/A    typename CPUPolicy::Commit commit;
6502292SN/A
6512292SN/A    /** The register file. */
6522292SN/A    typename CPUPolicy::RegFile regFile;
6532731Sktlim@umich.edu
6542292SN/A    /** The free list. */
6552292SN/A    typename CPUPolicy::FreeList freeList;
6562292SN/A
6572292SN/A    /** The rename map. */
6582292SN/A    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
6592292SN/A
6602292SN/A    /** The commit rename map. */
6612292SN/A    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
6626221Snate@binkert.org
6632292SN/A    /** The re-order buffer. */
6642292SN/A    typename CPUPolicy::ROB rob;
6652292SN/A
6662292SN/A    /** Active Threads List */
6672292SN/A    std::list<ThreadID> activeThreads;
6682292SN/A
6692292SN/A    /** Integer Register Scoreboard */
6702292SN/A    Scoreboard scoreboard;
6719937SFaissal.Sleiman@arm.com
6722292SN/A    std::vector<TheISA::ISA *> isa;
6737720Sgblack@eecs.umich.edu
6742292SN/A    /** Instruction port. Note that it has to appear after the fetch stage. */
6752292SN/A    IcachePort icachePort;
6762292SN/A
6772292SN/A    /** Data port. Note that it has to appear after the iew stages */
6782292SN/A    DcachePort dcachePort;
6792292SN/A
6802292SN/A  public:
6812292SN/A    /** Enum to give each stage a specific index, so when calling
6822292SN/A     *  activateStage() or deactivateStage(), they can specify which stage
6832292SN/A     *  is being activated/deactivated.
6842292SN/A     */
6852292SN/A    enum StageIdx {
6862292SN/A        FetchIdx,
6872292SN/A        DecodeIdx,
6886221Snate@binkert.org        RenameIdx,
6896221Snate@binkert.org        IEWIdx,
6902292SN/A        CommitIdx,
6913867Sbinkertn@umich.edu        NumStages };
6926221Snate@binkert.org
6933867Sbinkertn@umich.edu    /** Typedefs from the Impl to get the structs that each of the
6942292SN/A     *  time buffers should use.
6952292SN/A     */
6962292SN/A    typedef typename CPUPolicy::TimeStruct TimeStruct;
6972292SN/A
6982292SN/A    typedef typename CPUPolicy::FetchStruct FetchStruct;
6992292SN/A
7002292SN/A    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
7012292SN/A
7022292SN/A    typedef typename CPUPolicy::RenameStruct RenameStruct;
7032292SN/A
7042292SN/A    typedef typename CPUPolicy::IEWStruct IEWStruct;
7056221Snate@binkert.org
7066221Snate@binkert.org    /** The main time buffer to do backwards communication. */
7072292SN/A    TimeBuffer<TimeStruct> timeBuffer;
7083867Sbinkertn@umich.edu
7096221Snate@binkert.org    /** The fetch stage's instruction queue. */
7103867Sbinkertn@umich.edu    TimeBuffer<FetchStruct> fetchQueue;
7113867Sbinkertn@umich.edu
7122292SN/A    /** The decode stage's instruction queue. */
7132292SN/A    TimeBuffer<DecodeStruct> decodeQueue;
7142292SN/A
7152292SN/A    /** The rename stage's instruction queue. */
7161062SN/A    TimeBuffer<RenameStruct> renameQueue;
7171062SN/A
7181681SN/A    /** The IEW stage's instruction queue. */
7191062SN/A    TimeBuffer<IEWStruct> iewQueue;
7202292SN/A
7211062SN/A  private:
7222292SN/A    /** The activity recorder; used to tell if the CPU has any
7231062SN/A     * activity remaining or if it can go to idle and deschedule
7246221Snate@binkert.org     * itself.
7256221Snate@binkert.org     */
7261062SN/A    ActivityRecorder activityRec;
7273867Sbinkertn@umich.edu
7286221Snate@binkert.org  public:
7291062SN/A    /** Records that there was time buffer activity this cycle. */
7302292SN/A    void activityThisCycle() { activityRec.activity(); }
7312292SN/A
7322292SN/A    /** Changes a stage's status to active within the activity recorder. */
7332292SN/A    void activateStage(const StageIdx idx)
7342292SN/A    { activityRec.activateStage(idx); }
7351062SN/A
7362292SN/A    /** Changes a stage's status to inactive within the activity recorder. */
7372292SN/A    void deactivateStage(const StageIdx idx)
7382292SN/A    { activityRec.deactivateStage(idx); }
7397897Shestness@cs.utexas.edu
7402292SN/A    /** Wakes the CPU, rescheduling the CPU if it's not already active. */
7412292SN/A    void wakeCPU();
7422292SN/A
7431062SN/A    virtual void wakeup();
7442292SN/A
7451062SN/A    /** Gets a free thread id. Use if thread ids change across system. */
7462292SN/A    ThreadID getFreeTid();
7472292SN/A
7482292SN/A  public:
7492292SN/A    /** Returns a pointer to a thread context. */
7502292SN/A    ThreadContext *
7512292SN/A    tcBase(ThreadID tid)
7521062SN/A    {
7532292SN/A        return thread[tid]->getTC();
7541062SN/A    }
7552292SN/A
7561062SN/A    /** The global sequence number counter. */
7571062SN/A    InstSeqNum globalSeqNum;//[Impl::MaxThreads];
7581062SN/A
7591681SN/A    /** Pointer to the checker, which can dynamically verify
7601062SN/A     * instruction results at run time.  This can be set to NULL if it
7612292SN/A     * is not being used.
7621062SN/A     */
7632292SN/A    Checker<Impl> *checker;
7642292SN/A
7652292SN/A    /** Pointer to the system. */
7661062SN/A    System *system;
7672292SN/A
7682292SN/A    /** DrainManager to notify when draining has completed. */
7696221Snate@binkert.org    DrainManager *drainManager;
7702292SN/A
7712292SN/A    /** Pointers to all of the threads in the CPU. */
7722292SN/A    std::vector<Thread *> thread;
7732292SN/A
7741062SN/A    /** Is there a context switch pending? */
7752292SN/A    bool contextSwitch;
7762292SN/A
7772292SN/A    /** Threads Scheduled to Enter CPU */
7782292SN/A    std::list<int> cpuWaitList;
7792292SN/A
7802292SN/A    /** The cycle that the CPU was last running, used for statistics. */
7812292SN/A    Cycles lastRunningCycle;
7822292SN/A
7836221Snate@binkert.org    /** The cycle that the CPU was last activated by a new thread*/
7842292SN/A    Tick lastActivatedCycle;
7852292SN/A
7862292SN/A    /** Mapping for system thread id to cpu id */
7872292SN/A    std::map<ThreadID, unsigned> threadMap;
7882292SN/A
7892292SN/A    /** Available thread ids in the cpu*/
7902292SN/A    std::vector<ThreadID> tids;
7912292SN/A
7922292SN/A    /** CPU read function, forwards read to LSQ. */
7932292SN/A    Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
7942292SN/A               uint8_t *data, int load_idx)
7952292SN/A    {
7962292SN/A        return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
7972292SN/A                                        data, load_idx);
7982292SN/A    }
7992292SN/A
8002292SN/A    /** CPU write function, forwards write to LSQ. */
8012292SN/A    Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
8022292SN/A                uint8_t *data, int store_idx)
8032292SN/A    {
8042292SN/A        return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
8052292SN/A                                         data, store_idx);
8062292SN/A    }
8072292SN/A
8082292SN/A    /** Used by the fetch unit to get a hold of the instruction port. */
8092292SN/A    virtual CpuPort &getInstPort() { return icachePort; }
8102292SN/A
8112292SN/A    /** Get the dcache port (used to find block size for translations). */
8122292SN/A    virtual CpuPort &getDataPort() { return dcachePort; }
8132292SN/A
8142292SN/A    /** Stat for total number of times the CPU is descheduled. */
8152292SN/A    Stats::Scalar timesIdled;
8162292SN/A    /** Stat for total number of cycles the CPU spends descheduled. */
8172292SN/A    Stats::Scalar idleCycles;
8182292SN/A    /** Stat for total number of cycles the CPU spends descheduled due to a
8196221Snate@binkert.org     * quiesce operation or waiting for an interrupt. */
8202292SN/A    Stats::Scalar quiesceCycles;
8212292SN/A    /** Stat for the number of committed instructions per thread. */
8222292SN/A    Stats::Vector committedInsts;
8232292SN/A    /** Stat for the number of committed ops (including micro ops) per thread. */
8242292SN/A    Stats::Vector committedOps;
8252292SN/A    /** Stat for the total number of committed instructions. */
8262292SN/A    Stats::Scalar totalCommittedInsts;
8272292SN/A    /** Stat for the CPI per thread. */
8282292SN/A    Stats::Formula cpi;
8292292SN/A    /** Stat for the total CPI. */
8302292SN/A    Stats::Formula totalCpi;
8312292SN/A    /** Stat for the IPC per thread. */
8322292SN/A    Stats::Formula ipc;
8332292SN/A    /** Stat for the total IPC. */
8342292SN/A    Stats::Formula totalIpc;
8352292SN/A
8362292SN/A    //number of integer register file accesses
8372292SN/A    Stats::Scalar intRegfileReads;
8382292SN/A    Stats::Scalar intRegfileWrites;
8392292SN/A    //number of float register file accesses
8402292SN/A    Stats::Scalar fpRegfileReads;
8412292SN/A    Stats::Scalar fpRegfileWrites;
8422292SN/A    //number of misc
8432292SN/A    Stats::Scalar miscRegfileReads;
8442292SN/A    Stats::Scalar miscRegfileWrites;
8452702Sktlim@umich.edu};
8462292SN/A
8472292SN/A#endif // __CPU_O3_CPU_HH__
8482702Sktlim@umich.edu