cpu.hh revision 7897
12440SN/A/* 22440SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32440SN/A * Copyright (c) 2011 Regents of the University of California 42440SN/A * All rights reserved. 52440SN/A * 62440SN/A * Redistribution and use in source and binary forms, with or without 72440SN/A * modification, are permitted provided that the following conditions are 82440SN/A * met: redistributions of source code must retain the above copyright 92440SN/A * notice, this list of conditions and the following disclaimer; 102440SN/A * redistributions in binary form must reproduce the above copyright 112440SN/A * notice, this list of conditions and the following disclaimer in the 122440SN/A * documentation and/or other materials provided with the distribution; 132440SN/A * neither the name of the copyright holders nor the names of its 142440SN/A * contributors may be used to endorse or promote products derived from 152440SN/A * this software without specific prior written permission. 162440SN/A * 172440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665SN/A * 292440SN/A * Authors: Kevin Lim 302440SN/A * Korey Sewell 316329Sgblack@eecs.umich.edu * Rick Strong 326329Sgblack@eecs.umich.edu */ 332440SN/A 348961Sgblack@eecs.umich.edu#ifndef __CPU_O3_CPU_HH__ 356327SN/A#define __CPU_O3_CPU_HH__ 3612104Snathanael.premillieu@arm.com 3712109SRekai.GonzalezAlberquilla@arm.com#include <iostream> 386329Sgblack@eecs.umich.edu#include <list> 392440SN/A#include <queue> 405569SN/A#include <set> 412972SN/A#include <vector> 426329Sgblack@eecs.umich.edu 436329Sgblack@eecs.umich.edu#include "arch/types.hh" 446327SN/A#include "base/statistics.hh" 459046SAli.Saidi@ARM.com#include "cpu/timebuf.hh" 469046SAli.Saidi@ARM.com#include "config/full_system.hh" 479046SAli.Saidi@ARM.com#include "config/the_isa.hh" 4813556Sgabeblack@google.com#include "config/use_checker.hh" 496327SN/A#include "cpu/activity.hh" 506329Sgblack@eecs.umich.edu#include "cpu/base.hh" 5113556Sgabeblack@google.com#include "cpu/simple_thread.hh" 5213556Sgabeblack@google.com#include "cpu/o3/comm.hh" 536327SN/A#include "cpu/o3/cpu_policy.hh" 546329Sgblack@eecs.umich.edu#include "cpu/o3/scoreboard.hh" 5513556Sgabeblack@google.com#include "cpu/o3/thread_state.hh" 566327SN/A//#include "cpu/o3/thread_context.hh" 579920Syasuko.eckert@amd.com#include "sim/process.hh" 589920Syasuko.eckert@amd.com 599920Syasuko.eckert@amd.com#include "params/DerivO3CPU.hh" 6012109SRekai.GonzalezAlberquilla@arm.com 6112109SRekai.GonzalezAlberquilla@arm.comtemplate <class> 6212109SRekai.GonzalezAlberquilla@arm.comclass Checker; 6312109SRekai.GonzalezAlberquilla@arm.comclass ThreadContext; 6412109SRekai.GonzalezAlberquilla@arm.comtemplate <class> 6512109SRekai.GonzalezAlberquilla@arm.comclass O3ThreadContext; 6612109SRekai.GonzalezAlberquilla@arm.com 6712109SRekai.GonzalezAlberquilla@arm.comclass Checkpoint; 6812109SRekai.GonzalezAlberquilla@arm.comclass MemObject; 696329Sgblack@eecs.umich.educlass Process; 706329Sgblack@eecs.umich.edu 716329Sgblack@eecs.umich.educlass BaseCPUParams; 726329Sgblack@eecs.umich.edu 736329Sgblack@eecs.umich.educlass BaseO3CPU : public BaseCPU 746329Sgblack@eecs.umich.edu{ 757699Sgblack@eecs.umich.edu //Stuff that's pretty ISA independent will go here. 767699Sgblack@eecs.umich.edu public: 776329Sgblack@eecs.umich.edu BaseO3CPU(BaseCPUParams *params); 785569SN/A 796329Sgblack@eecs.umich.edu void regStats(); 806329Sgblack@eecs.umich.edu}; 816329Sgblack@eecs.umich.edu 826329Sgblack@eecs.umich.edu/** 836329Sgblack@eecs.umich.edu * FullO3CPU class, has each of the stages (fetch through commit) 846329Sgblack@eecs.umich.edu * within it, as well as all of the time buffers between stages. The 856329Sgblack@eecs.umich.edu * tick() function for the CPU is defined here. 866329Sgblack@eecs.umich.edu */ 876329Sgblack@eecs.umich.edutemplate <class Impl> 886329Sgblack@eecs.umich.educlass FullO3CPU : public BaseO3CPU 896329Sgblack@eecs.umich.edu{ 906329Sgblack@eecs.umich.edu public: 916329Sgblack@eecs.umich.edu // Typedefs from the Impl here. 926329Sgblack@eecs.umich.edu typedef typename Impl::CPUPol CPUPolicy; 936329Sgblack@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 946329Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 956329Sgblack@eecs.umich.edu 966329Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 976329Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> Thread; 986329Sgblack@eecs.umich.edu 996329Sgblack@eecs.umich.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 1009920Syasuko.eckert@amd.com 1019917Ssteve.reinhardt@amd.com friend class O3ThreadContext<Impl>; 1026329Sgblack@eecs.umich.edu 1036329Sgblack@eecs.umich.edu public: 1047699Sgblack@eecs.umich.edu enum Status { 1056329Sgblack@eecs.umich.edu Running, 1062440SN/A Idle, 1072440SN/A Halted, 1085569SN/A Blocked, 109 SwitchedOut 110 }; 111 112 TheISA::TLB * itb; 113 TheISA::TLB * dtb; 114 115 /** Overall CPU status. */ 116 Status _status; 117 118 /** Per-thread status in CPU, used for SMT. */ 119 Status _threadStatus[Impl::MaxThreads]; 120 121 private: 122 class TickEvent : public Event 123 { 124 private: 125 /** Pointer to the CPU. */ 126 FullO3CPU<Impl> *cpu; 127 128 public: 129 /** Constructs a tick event. */ 130 TickEvent(FullO3CPU<Impl> *c); 131 132 /** Processes a tick event, calling tick() on the CPU. */ 133 void process(); 134 /** Returns the description of the tick event. */ 135 const char *description() const; 136 }; 137 138 /** The tick event used for scheduling CPU ticks. */ 139 TickEvent tickEvent; 140 141 /** Schedule tick event, regardless of its current state. */ 142 void scheduleTickEvent(int delay) 143 { 144 if (tickEvent.squashed()) 145 reschedule(tickEvent, nextCycle(curTick() + ticks(delay))); 146 else if (!tickEvent.scheduled()) 147 schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 148 } 149 150 /** Unschedule tick event, regardless of its current state. */ 151 void unscheduleTickEvent() 152 { 153 if (tickEvent.scheduled()) 154 tickEvent.squash(); 155 } 156 157 class ActivateThreadEvent : public Event 158 { 159 private: 160 /** Number of Thread to Activate */ 161 ThreadID tid; 162 163 /** Pointer to the CPU. */ 164 FullO3CPU<Impl> *cpu; 165 166 public: 167 /** Constructs the event. */ 168 ActivateThreadEvent(); 169 170 /** Initialize Event */ 171 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 172 173 /** Processes the event, calling activateThread() on the CPU. */ 174 void process(); 175 176 /** Returns the description of the event. */ 177 const char *description() const; 178 }; 179 180 /** Schedule thread to activate , regardless of its current state. */ 181 void 182 scheduleActivateThreadEvent(ThreadID tid, int delay) 183 { 184 // Schedule thread to activate, regardless of its current state. 185 if (activateThreadEvent[tid].squashed()) 186 reschedule(activateThreadEvent[tid], 187 nextCycle(curTick() + ticks(delay))); 188 else if (!activateThreadEvent[tid].scheduled()) 189 schedule(activateThreadEvent[tid], 190 nextCycle(curTick() + ticks(delay))); 191 } 192 193 /** Unschedule actiavte thread event, regardless of its current state. */ 194 void 195 unscheduleActivateThreadEvent(ThreadID tid) 196 { 197 if (activateThreadEvent[tid].scheduled()) 198 activateThreadEvent[tid].squash(); 199 } 200 201 /** The tick event used for scheduling CPU ticks. */ 202 ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 203 204 class DeallocateContextEvent : public Event 205 { 206 private: 207 /** Number of Thread to deactivate */ 208 ThreadID tid; 209 210 /** Should the thread be removed from the CPU? */ 211 bool remove; 212 213 /** Pointer to the CPU. */ 214 FullO3CPU<Impl> *cpu; 215 216 public: 217 /** Constructs the event. */ 218 DeallocateContextEvent(); 219 220 /** Initialize Event */ 221 void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 222 223 /** Processes the event, calling activateThread() on the CPU. */ 224 void process(); 225 226 /** Sets whether the thread should also be removed from the CPU. */ 227 void setRemove(bool _remove) { remove = _remove; } 228 229 /** Returns the description of the event. */ 230 const char *description() const; 231 }; 232 233 /** Schedule cpu to deallocate thread context.*/ 234 void 235 scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay) 236 { 237 // Schedule thread to activate, regardless of its current state. 238 if (deallocateContextEvent[tid].squashed()) 239 reschedule(deallocateContextEvent[tid], 240 nextCycle(curTick() + ticks(delay))); 241 else if (!deallocateContextEvent[tid].scheduled()) 242 schedule(deallocateContextEvent[tid], 243 nextCycle(curTick() + ticks(delay))); 244 } 245 246 /** Unschedule thread deallocation in CPU */ 247 void 248 unscheduleDeallocateContextEvent(ThreadID tid) 249 { 250 if (deallocateContextEvent[tid].scheduled()) 251 deallocateContextEvent[tid].squash(); 252 } 253 254 /** The tick event used for scheduling CPU ticks. */ 255 DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 256 257 public: 258 /** Constructs a CPU with the given parameters. */ 259 FullO3CPU(DerivO3CPUParams *params); 260 /** Destructor. */ 261 ~FullO3CPU(); 262 263 /** Registers statistics. */ 264 void regStats(); 265 266 void demapPage(Addr vaddr, uint64_t asn) 267 { 268 this->itb->demapPage(vaddr, asn); 269 this->dtb->demapPage(vaddr, asn); 270 } 271 272 void demapInstPage(Addr vaddr, uint64_t asn) 273 { 274 this->itb->demapPage(vaddr, asn); 275 } 276 277 void demapDataPage(Addr vaddr, uint64_t asn) 278 { 279 this->dtb->demapPage(vaddr, asn); 280 } 281 282 /** Returns a specific port. */ 283 Port *getPort(const std::string &if_name, int idx); 284 285 /** Ticks CPU, calling tick() on each stage, and checking the overall 286 * activity to see if the CPU should deschedule itself. 287 */ 288 void tick(); 289 290 /** Initialize the CPU */ 291 void init(); 292 293 /** Returns the Number of Active Threads in the CPU */ 294 int numActiveThreads() 295 { return activeThreads.size(); } 296 297 /** Add Thread to Active Threads List */ 298 void activateThread(ThreadID tid); 299 300 /** Remove Thread from Active Threads List */ 301 void deactivateThread(ThreadID tid); 302 303 /** Setup CPU to insert a thread's context */ 304 void insertThread(ThreadID tid); 305 306 /** Remove all of a thread's context from CPU */ 307 void removeThread(ThreadID tid); 308 309 /** Count the Total Instructions Committed in the CPU. */ 310 virtual Counter totalInstructions() const; 311 312 /** Add Thread to Active Threads List. */ 313 void activateContext(ThreadID tid, int delay); 314 315 /** Remove Thread from Active Threads List */ 316 void suspendContext(ThreadID tid); 317 318 /** Remove Thread from Active Threads List && 319 * Possibly Remove Thread Context from CPU. 320 */ 321 bool deallocateContext(ThreadID tid, bool remove, int delay = 1); 322 323 /** Remove Thread from Active Threads List && 324 * Remove Thread Context from CPU. 325 */ 326 void haltContext(ThreadID tid); 327 328 /** Activate a Thread When CPU Resources are Available. */ 329 void activateWhenReady(ThreadID tid); 330 331 /** Add or Remove a Thread Context in the CPU. */ 332 void doContextSwitch(); 333 334 /** Update The Order In Which We Process Threads. */ 335 void updateThreadPriority(); 336 337 /** Serialize state. */ 338 virtual void serialize(std::ostream &os); 339 340 /** Unserialize from a checkpoint. */ 341 virtual void unserialize(Checkpoint *cp, const std::string §ion); 342 343 public: 344#if !FULL_SYSTEM 345 /** Executes a syscall. 346 * @todo: Determine if this needs to be virtual. 347 */ 348 void syscall(int64_t callnum, ThreadID tid); 349#endif 350 351 /** Starts draining the CPU's pipeline of all instructions in 352 * order to stop all memory accesses. */ 353 virtual unsigned int drain(Event *drain_event); 354 355 /** Resumes execution after a drain. */ 356 virtual void resume(); 357 358 /** Signals to this CPU that a stage has completed switching out. */ 359 void signalDrained(); 360 361 /** Switches out this CPU. */ 362 virtual void switchOut(); 363 364 /** Takes over from another CPU. */ 365 virtual void takeOverFrom(BaseCPU *oldCPU); 366 367 /** Get the current instruction sequence number, and increment it. */ 368 InstSeqNum getAndIncrementInstSeq() 369 { return globalSeqNum++; } 370 371 /** Traps to handle given fault. */ 372 void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 373 374#if FULL_SYSTEM 375 /** HW return from error interrupt. */ 376 Fault hwrei(ThreadID tid); 377 378 bool simPalCheck(int palFunc, ThreadID tid); 379 380 /** Returns the Fault for any valid interrupt. */ 381 Fault getInterrupts(); 382 383 /** Processes any an interrupt fault. */ 384 void processInterrupts(Fault interrupt); 385 386 /** Halts the CPU. */ 387 void halt() { panic("Halt not implemented!\n"); } 388 389 /** Update the Virt and Phys ports of all ThreadContexts to 390 * reflect change in memory connections. */ 391 void updateMemPorts(); 392 393 /** Check if this address is a valid instruction address. */ 394 bool validInstAddr(Addr addr) { return true; } 395 396 /** Check if this address is a valid data address. */ 397 bool validDataAddr(Addr addr) { return true; } 398#endif 399 400 /** Register accessors. Index refers to the physical register index. */ 401 402 /** Reads a miscellaneous register. */ 403 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 404 405 /** Reads a misc. register, including any side effects the read 406 * might have as defined by the architecture. 407 */ 408 TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 409 410 /** Sets a miscellaneous register. */ 411 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 412 ThreadID tid); 413 414 /** Sets a misc. register, including any side effects the write 415 * might have as defined by the architecture. 416 */ 417 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 418 ThreadID tid); 419 420 uint64_t readIntReg(int reg_idx); 421 422 TheISA::FloatReg readFloatReg(int reg_idx); 423 424 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 425 426 void setIntReg(int reg_idx, uint64_t val); 427 428 void setFloatReg(int reg_idx, TheISA::FloatReg val); 429 430 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 431 432 uint64_t readArchIntReg(int reg_idx, ThreadID tid); 433 434 float readArchFloatReg(int reg_idx, ThreadID tid); 435 436 uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 437 438 /** Architectural register accessors. Looks up in the commit 439 * rename table to obtain the true physical index of the 440 * architected register first, then accesses that physical 441 * register. 442 */ 443 void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 444 445 void setArchFloatReg(int reg_idx, float val, ThreadID tid); 446 447 void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 448 449 /** Sets the commit PC state of a specific thread. */ 450 void pcState(const TheISA::PCState &newPCState, ThreadID tid); 451 452 /** Reads the commit PC state of a specific thread. */ 453 TheISA::PCState pcState(ThreadID tid); 454 455 /** Reads the commit PC of a specific thread. */ 456 Addr instAddr(ThreadID tid); 457 458 /** Reads the commit micro PC of a specific thread. */ 459 MicroPC microPC(ThreadID tid); 460 461 /** Reads the next PC of a specific thread. */ 462 Addr nextInstAddr(ThreadID tid); 463 464 /** Initiates a squash of all in-flight instructions for a given 465 * thread. The source of the squash is an external update of 466 * state through the TC. 467 */ 468 void squashFromTC(ThreadID tid); 469 470 /** Function to add instruction onto the head of the list of the 471 * instructions. Used when new instructions are fetched. 472 */ 473 ListIt addInst(DynInstPtr &inst); 474 475 /** Function to tell the CPU that an instruction has completed. */ 476 void instDone(ThreadID tid); 477 478 /** Add Instructions to the CPU Remove List*/ 479 void addToRemoveList(DynInstPtr &inst); 480 481 /** Remove an instruction from the front end of the list. There's 482 * no restriction on location of the instruction. 483 */ 484 void removeFrontInst(DynInstPtr &inst); 485 486 /** Remove all instructions that are not currently in the ROB. 487 * There's also an option to not squash delay slot instructions.*/ 488 void removeInstsNotInROB(ThreadID tid); 489 490 /** Remove all instructions younger than the given sequence number. */ 491 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 492 493 /** Removes the instruction pointed to by the iterator. */ 494 inline void squashInstIt(const ListIt &instIt, ThreadID tid); 495 496 /** Cleans up all instructions on the remove list. */ 497 void cleanUpRemovedInsts(); 498 499 /** Debug function to print all instructions on the list. */ 500 void dumpInsts(); 501 502 public: 503#ifndef NDEBUG 504 /** Count of total number of dynamic instructions in flight. */ 505 int instcount; 506#endif 507 508 /** List of all the instructions in flight. */ 509 std::list<DynInstPtr> instList; 510 511 /** List of all the instructions that will be removed at the end of this 512 * cycle. 513 */ 514 std::queue<ListIt> removeList; 515 516#ifdef DEBUG 517 /** Debug structure to keep track of the sequence numbers still in 518 * flight. 519 */ 520 std::set<InstSeqNum> snList; 521#endif 522 523 /** Records if instructions need to be removed this cycle due to 524 * being retired or squashed. 525 */ 526 bool removeInstsThisCycle; 527 528 protected: 529 /** The fetch stage. */ 530 typename CPUPolicy::Fetch fetch; 531 532 /** The decode stage. */ 533 typename CPUPolicy::Decode decode; 534 535 /** The dispatch stage. */ 536 typename CPUPolicy::Rename rename; 537 538 /** The issue/execute/writeback stages. */ 539 typename CPUPolicy::IEW iew; 540 541 /** The commit stage. */ 542 typename CPUPolicy::Commit commit; 543 544 /** The register file. */ 545 typename CPUPolicy::RegFile regFile; 546 547 /** The free list. */ 548 typename CPUPolicy::FreeList freeList; 549 550 /** The rename map. */ 551 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 552 553 /** The commit rename map. */ 554 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 555 556 /** The re-order buffer. */ 557 typename CPUPolicy::ROB rob; 558 559 /** Active Threads List */ 560 std::list<ThreadID> activeThreads; 561 562 /** Integer Register Scoreboard */ 563 Scoreboard scoreboard; 564 565 TheISA::ISA isa[Impl::MaxThreads]; 566 567 public: 568 /** Enum to give each stage a specific index, so when calling 569 * activateStage() or deactivateStage(), they can specify which stage 570 * is being activated/deactivated. 571 */ 572 enum StageIdx { 573 FetchIdx, 574 DecodeIdx, 575 RenameIdx, 576 IEWIdx, 577 CommitIdx, 578 NumStages }; 579 580 /** Typedefs from the Impl to get the structs that each of the 581 * time buffers should use. 582 */ 583 typedef typename CPUPolicy::TimeStruct TimeStruct; 584 585 typedef typename CPUPolicy::FetchStruct FetchStruct; 586 587 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 588 589 typedef typename CPUPolicy::RenameStruct RenameStruct; 590 591 typedef typename CPUPolicy::IEWStruct IEWStruct; 592 593 /** The main time buffer to do backwards communication. */ 594 TimeBuffer<TimeStruct> timeBuffer; 595 596 /** The fetch stage's instruction queue. */ 597 TimeBuffer<FetchStruct> fetchQueue; 598 599 /** The decode stage's instruction queue. */ 600 TimeBuffer<DecodeStruct> decodeQueue; 601 602 /** The rename stage's instruction queue. */ 603 TimeBuffer<RenameStruct> renameQueue; 604 605 /** The IEW stage's instruction queue. */ 606 TimeBuffer<IEWStruct> iewQueue; 607 608 private: 609 /** The activity recorder; used to tell if the CPU has any 610 * activity remaining or if it can go to idle and deschedule 611 * itself. 612 */ 613 ActivityRecorder activityRec; 614 615 public: 616 /** Records that there was time buffer activity this cycle. */ 617 void activityThisCycle() { activityRec.activity(); } 618 619 /** Changes a stage's status to active within the activity recorder. */ 620 void activateStage(const StageIdx idx) 621 { activityRec.activateStage(idx); } 622 623 /** Changes a stage's status to inactive within the activity recorder. */ 624 void deactivateStage(const StageIdx idx) 625 { activityRec.deactivateStage(idx); } 626 627 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 628 void wakeCPU(); 629 630#if FULL_SYSTEM 631 virtual void wakeup(); 632#endif 633 634 /** Gets a free thread id. Use if thread ids change across system. */ 635 ThreadID getFreeTid(); 636 637 public: 638 /** Returns a pointer to a thread context. */ 639 ThreadContext * 640 tcBase(ThreadID tid) 641 { 642 return thread[tid]->getTC(); 643 } 644 645 /** The global sequence number counter. */ 646 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 647 648#if USE_CHECKER 649 /** Pointer to the checker, which can dynamically verify 650 * instruction results at run time. This can be set to NULL if it 651 * is not being used. 652 */ 653 Checker<DynInstPtr> *checker; 654#endif 655 656#if FULL_SYSTEM 657 /** Pointer to the system. */ 658 System *system; 659#endif 660 661 /** Event to call process() on once draining has completed. */ 662 Event *drainEvent; 663 664 /** Counter of how many stages have completed draining. */ 665 int drainCount; 666 667 /** Pointers to all of the threads in the CPU. */ 668 std::vector<Thread *> thread; 669 670 /** Whether or not the CPU should defer its registration. */ 671 bool deferRegistration; 672 673 /** Is there a context switch pending? */ 674 bool contextSwitch; 675 676 /** Threads Scheduled to Enter CPU */ 677 std::list<int> cpuWaitList; 678 679 /** The cycle that the CPU was last running, used for statistics. */ 680 Tick lastRunningCycle; 681 682 /** The cycle that the CPU was last activated by a new thread*/ 683 Tick lastActivatedCycle; 684 685 /** Mapping for system thread id to cpu id */ 686 std::map<ThreadID, unsigned> threadMap; 687 688 /** Available thread ids in the cpu*/ 689 std::vector<ThreadID> tids; 690 691 /** CPU read function, forwards read to LSQ. */ 692 Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 693 uint8_t *data, int load_idx) 694 { 695 return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 696 data, load_idx); 697 } 698 699 /** CPU write function, forwards write to LSQ. */ 700 Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 701 uint8_t *data, int store_idx) 702 { 703 return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 704 data, store_idx); 705 } 706 707 /** Get the dcache port (used to find block size for translations). */ 708 Port *getDcachePort() { return this->iew.ldstQueue.getDcachePort(); } 709 710 Addr lockAddr; 711 712 /** Temporary fix for the lock flag, works in the UP case. */ 713 bool lockFlag; 714 715 /** Stat for total number of times the CPU is descheduled. */ 716 Stats::Scalar timesIdled; 717 /** Stat for total number of cycles the CPU spends descheduled. */ 718 Stats::Scalar idleCycles; 719 /** Stat for the number of committed instructions per thread. */ 720 Stats::Vector committedInsts; 721 /** Stat for the total number of committed instructions. */ 722 Stats::Scalar totalCommittedInsts; 723 /** Stat for the CPI per thread. */ 724 Stats::Formula cpi; 725 /** Stat for the total CPI. */ 726 Stats::Formula totalCpi; 727 /** Stat for the IPC per thread. */ 728 Stats::Formula ipc; 729 /** Stat for the total IPC. */ 730 Stats::Formula totalIpc; 731 732 //number of integer register file accesses 733 Stats::Scalar intRegfileReads; 734 Stats::Scalar intRegfileWrites; 735 //number of float register file accesses 736 Stats::Scalar fpRegfileReads; 737 Stats::Scalar fpRegfileWrites; 738 //number of misc 739 Stats::Scalar miscRegfileReads; 740 Stats::Scalar miscRegfileWrites; 741}; 742 743#endif // __CPU_O3_CPU_HH__ 744