cpu.hh revision 5702
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Korey Sewell 302SN/A */ 312SN/A 321388SN/A#ifndef __CPU_O3_CPU_HH__ 332SN/A#define __CPU_O3_CPU_HH__ 342SN/A 352SN/A#include <iostream> 361191SN/A#include <list> 371191SN/A#include <queue> 381191SN/A#include <set> 391388SN/A#include <vector> 401717SN/A 412651Ssaidi@eecs.umich.edu#include "arch/types.hh" 422680Sktlim@umich.edu#include "base/statistics.hh" 431977SN/A#include "base/timebuf.hh" 44161SN/A#include "config/full_system.hh" 452190SN/A#include "config/use_checker.hh" 4656SN/A#include "cpu/activity.hh" 472190SN/A#include "cpu/base.hh" 482SN/A#include "cpu/simple_thread.hh" 491062SN/A#include "cpu/o3/comm.hh" 501062SN/A#include "cpu/o3/cpu_policy.hh" 512SN/A#include "cpu/o3/scoreboard.hh" 522SN/A#include "cpu/o3/thread_state.hh" 532SN/A//#include "cpu/o3/thread_context.hh" 542SN/A#include "sim/process.hh" 552SN/A 562SN/A#include "params/DerivO3CPU.hh" 572SN/A 582SN/Atemplate <class> 592SN/Aclass Checker; 601858SN/Aclass ThreadContext; 611400SN/Atemplate <class> 621695SN/Aclass O3ThreadContext; 631400SN/A 642SN/Aclass Checkpoint; 651400SN/Aclass MemObject; 662856Srdreslin@umich.educlass Process; 672378SN/A 682SN/Aclass BaseCPUParams; 692SN/A 702831Sksewell@umich.educlass BaseO3CPU : public BaseCPU 711062SN/A{ 722SN/A //Stuff that's pretty ISA independent will go here. 732SN/A public: 742SN/A BaseO3CPU(BaseCPUParams *params); 752831Sksewell@umich.edu 761062SN/A void regStats(); 771062SN/A 782SN/A /** Sets this CPU's ID. */ 792SN/A void setCpuId(int id) { cpu_id = id; } 802SN/A 812SN/A /** Reads this CPU's ID. */ 821354SN/A int readCpuId() { return cpu_id; } 832SN/A 84503SN/A protected: 852SN/A int cpu_id; 862SN/A}; 872SN/A 882SN/A/** 891400SN/A * FullO3CPU class, has each of the stages (fetch through commit) 902SN/A * within it, as well as all of the time buffers between stages. The 912667Sstever@eecs.umich.edu * tick() function for the CPU is defined here. 922667Sstever@eecs.umich.edu */ 932SN/Atemplate <class Impl> 941400SN/Aclass FullO3CPU : public BaseO3CPU 952SN/A{ 962SN/A public: 972SN/A // Typedefs from the Impl here. 982SN/A typedef typename Impl::CPUPol CPUPolicy; 992SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1002SN/A typedef typename Impl::O3CPU O3CPU; 101503SN/A 1022SN/A typedef O3ThreadState<Impl> ImplState; 1031400SN/A typedef O3ThreadState<Impl> Thread; 1042SN/A 1052SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 106124SN/A 1071354SN/A friend class O3ThreadContext<Impl>; 108124SN/A 109124SN/A public: 110124SN/A enum Status { 111124SN/A Running, 112124SN/A Idle, 113124SN/A Halted, 1141400SN/A Blocked, 115124SN/A SwitchedOut 1162667Sstever@eecs.umich.edu }; 1172667Sstever@eecs.umich.edu 118124SN/A TheISA::ITB * itb; 1191400SN/A TheISA::DTB * dtb; 120124SN/A 121124SN/A /** Overall CPU status. */ 122124SN/A Status _status; 123124SN/A 124124SN/A /** Per-thread status in CPU, used for SMT. */ 125124SN/A Status _threadStatus[Impl::MaxThreads]; 126124SN/A 127124SN/A private: 1281400SN/A class TickEvent : public Event 129124SN/A { 130124SN/A private: 1311858SN/A /** Pointer to the CPU. */ 1322SN/A FullO3CPU<Impl> *cpu; 1332SN/A 1342SN/A public: 1351191SN/A /** Constructs a tick event. */ 1361191SN/A TickEvent(FullO3CPU<Impl> *c); 1371400SN/A 1381388SN/A /** Processes a tick event, calling tick() on the CPU. */ 1391191SN/A void process(); 1401400SN/A /** Returns the description of the tick event. */ 1411191SN/A const char *description() const; 1421400SN/A }; 1431191SN/A 1441191SN/A /** The tick event used for scheduling CPU ticks. */ 1451191SN/A TickEvent tickEvent; 1461191SN/A 1471191SN/A /** Schedule tick event, regardless of its current state. */ 1481400SN/A void scheduleTickEvent(int delay) 1491191SN/A { 1501191SN/A if (tickEvent.squashed()) 1511917SN/A reschedule(tickEvent, nextCycle(curTick + ticks(delay))); 1521917SN/A else if (!tickEvent.scheduled()) 1531917SN/A schedule(tickEvent, nextCycle(curTick + ticks(delay))); 1541917SN/A } 1551917SN/A 1562190SN/A /** Unschedule tick event, regardless of its current state. */ 1572SN/A void unscheduleTickEvent() 1582SN/A { 1591917SN/A if (tickEvent.scheduled()) 1601917SN/A tickEvent.squash(); 1611917SN/A } 1621917SN/A 1631917SN/A class ActivateThreadEvent : public Event 1642315SN/A { 1651917SN/A private: 1661191SN/A /** Number of Thread to Activate */ 1671191SN/A int tid; 1681191SN/A 1691191SN/A /** Pointer to the CPU. */ 1701191SN/A FullO3CPU<Impl> *cpu; 1711191SN/A 1721191SN/A public: 1731191SN/A /** Constructs the event. */ 1741191SN/A ActivateThreadEvent(); 1751191SN/A 1761191SN/A /** Initialize Event */ 1771129SN/A void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1781129SN/A 1791129SN/A /** Processes the event, calling activateThread() on the CPU. */ 1801400SN/A void process(); 1812680Sktlim@umich.edu 1821129SN/A /** Returns the description of the event. */ 183180SN/A const char *description() const; 1842SN/A }; 1851917SN/A 1861917SN/A /** Schedule thread to activate , regardless of its current state. */ 1871917SN/A void scheduleActivateThreadEvent(int tid, int delay) 1881917SN/A { 1891917SN/A // Schedule thread to activate, regardless of its current state. 1901917SN/A if (activateThreadEvent[tid].squashed()) 1911917SN/A reschedule(activateThreadEvent[tid], 1921917SN/A nextCycle(curTick + ticks(delay))); 1931917SN/A else if (!activateThreadEvent[tid].scheduled()) 1941917SN/A schedule(activateThreadEvent[tid], 1952SN/A nextCycle(curTick + ticks(delay))); 1962SN/A } 197729SN/A 198707SN/A /** Unschedule actiavte thread event, regardless of its current state. */ 199707SN/A void unscheduleActivateThreadEvent(int tid) 200707SN/A { 201707SN/A if (activateThreadEvent[tid].scheduled()) 202707SN/A activateThreadEvent[tid].squash(); 203707SN/A } 2042680Sktlim@umich.edu 2052SN/A#if !FULL_SYSTEM 2062SN/A TheISA::IntReg getSyscallArg(int i, int tid); 2072SN/A 2082SN/A /** Used to shift args for indirect syscall. */ 2092680Sktlim@umich.edu void setSyscallArg(int i, TheISA::IntReg val, int tid); 2102SN/A#endif 2112SN/A 2122680Sktlim@umich.edu /** The tick event used for scheduling CPU ticks. */ 2132190SN/A ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2142190SN/A 2152190SN/A class DeallocateContextEvent : public Event 2162SN/A { 2172SN/A private: 218180SN/A /** Number of Thread to deactivate */ 219180SN/A int tid; 2202680Sktlim@umich.edu 221180SN/A /** Should the thread be removed from the CPU? */ 2222680Sktlim@umich.edu bool remove; 2232680Sktlim@umich.edu 2242378SN/A /** Pointer to the CPU. */ 2251858SN/A FullO3CPU<Impl> *cpu; 2261806SN/A 2271806SN/A public: 2281806SN/A /** Constructs the event. */ 229180SN/A DeallocateContextEvent(); 2302680Sktlim@umich.edu 231180SN/A /** Initialize Event */ 2322680Sktlim@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 233180SN/A 234180SN/A /** Processes the event, calling activateThread() on the CPU. */ 235180SN/A void process(); 236180SN/A 237180SN/A /** Sets whether the thread should also be removed from the CPU. */ 238180SN/A void setRemove(bool _remove) { remove = _remove; } 2392798Sktlim@umich.edu 240180SN/A /** Returns the description of the event. */ 2411545SN/A const char *description() const; 242180SN/A }; 243180SN/A 244180SN/A /** Schedule cpu to deallocate thread context.*/ 245180SN/A void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 246180SN/A { 2472680Sktlim@umich.edu // Schedule thread to activate, regardless of its current state. 248180SN/A if (deallocateContextEvent[tid].squashed()) 2492680Sktlim@umich.edu reschedule(deallocateContextEvent[tid], 2502680Sktlim@umich.edu nextCycle(curTick + ticks(delay))); 2512680Sktlim@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 252180SN/A schedule(deallocateContextEvent[tid], 2532680Sktlim@umich.edu nextCycle(curTick + ticks(delay))); 2542651Ssaidi@eecs.umich.edu } 2552680Sktlim@umich.edu 2562651Ssaidi@eecs.umich.edu /** Unschedule thread deallocation in CPU */ 2572680Sktlim@umich.edu void unscheduleDeallocateContextEvent(int tid) 2581858SN/A { 2592680Sktlim@umich.edu if (deallocateContextEvent[tid].scheduled()) 260180SN/A deallocateContextEvent[tid].squash(); 2612680Sktlim@umich.edu } 2622680Sktlim@umich.edu 263180SN/A /** The tick event used for scheduling CPU ticks. */ 264180SN/A DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 265605SN/A 2661858SN/A public: 2672107SN/A /** Constructs a CPU with the given parameters. */ 268605SN/A FullO3CPU(DerivO3CPUParams *params); 269605SN/A /** Destructor. */ 2702254SN/A ~FullO3CPU(); 2712680Sktlim@umich.edu 2722680Sktlim@umich.edu /** Registers statistics. */ 2732254SN/A void regStats(); 2741917SN/A 2751917SN/A void demapPage(Addr vaddr, uint64_t asn) 276612SN/A { 277180SN/A this->itb->demapPage(vaddr, asn); 278180SN/A this->dtb->demapPage(vaddr, asn); 279180SN/A } 2801858SN/A 2811917SN/A void demapInstPage(Addr vaddr, uint64_t asn) 2821917SN/A { 2831917SN/A this->itb->demapPage(vaddr, asn); 2841917SN/A } 2851917SN/A 2861917SN/A void demapDataPage(Addr vaddr, uint64_t asn) 2871917SN/A { 2882680Sktlim@umich.edu this->dtb->demapPage(vaddr, asn); 2892680Sktlim@umich.edu } 2902680Sktlim@umich.edu 2911917SN/A /** Translates instruction requestion. */ 2922254SN/A Fault translateInstReq(RequestPtr &req, Thread *thread) 2931917SN/A { 2941917SN/A return this->itb->translate(req, thread->getTC()); 2951917SN/A } 2962SN/A 2972SN/A /** Translates data read request. */ 2982SN/A Fault translateDataReadReq(RequestPtr &req, Thread *thread) 2992SN/A { 3002SN/A return this->dtb->translate(req, thread->getTC(), false); 3012107SN/A } 3022SN/A 3032SN/A /** Translates data write request. */ 304822SN/A Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 3052SN/A { 3062SN/A return this->dtb->translate(req, thread->getTC(), true); 3071133SN/A } 3082SN/A 3092SN/A /** Returns a specific port. */ 3102SN/A Port *getPort(const std::string &if_name, int idx); 3112SN/A 3122SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 3132SN/A * activity to see if the CPU should deschedule itself. 3142SN/A */ 3152SN/A void tick(); 3162SN/A 3172107SN/A /** Initialize the CPU */ 3182SN/A void init(); 3192SN/A 320822SN/A /** Returns the Number of Active Threads in the CPU */ 3212SN/A int numActiveThreads() 3222SN/A { return activeThreads.size(); } 3232SN/A 3242SN/A /** Add Thread to Active Threads List */ 3252SN/A void activateThread(unsigned tid); 3262SN/A 3272SN/A /** Remove Thread from Active Threads List */ 3282SN/A void deactivateThread(unsigned tid); 3292SN/A 3302SN/A /** Setup CPU to insert a thread's context */ 3312SN/A void insertThread(unsigned tid); 3322SN/A 3332SN/A /** Remove all of a thread's context from CPU */ 3342SN/A void removeThread(unsigned tid); 3352SN/A 3362SN/A /** Count the Total Instructions Committed in the CPU. */ 337921SN/A virtual Counter totalInstructions() const 338921SN/A { 339921SN/A Counter total(0); 340921SN/A 3412107SN/A for (int i=0; i < thread.size(); i++) 342921SN/A total += thread[i]->numInst; 343921SN/A 344921SN/A return total; 345921SN/A } 346921SN/A 347921SN/A /** Add Thread to Active Threads List. */ 3482107SN/A void activateContext(int tid, int delay); 349921SN/A 350921SN/A /** Remove Thread from Active Threads List */ 351921SN/A void suspendContext(int tid); 3522SN/A 3532SN/A /** Remove Thread from Active Threads List && 3541191SN/A * Possibly Remove Thread Context from CPU. 3551191SN/A */ 3561191SN/A bool deallocateContext(int tid, bool remove, int delay = 1); 3571191SN/A 3581191SN/A /** Remove Thread from Active Threads List && 3591191SN/A * Remove Thread Context from CPU. 3601191SN/A */ 3611191SN/A void haltContext(int tid); 3621191SN/A 3631191SN/A /** Activate a Thread When CPU Resources are Available. */ 3641191SN/A void activateWhenReady(int tid); 3651191SN/A 3661191SN/A /** Add or Remove a Thread Context in the CPU. */ 3671191SN/A void doContextSwitch(); 3681191SN/A 3691191SN/A /** Update The Order In Which We Process Threads. */ 3701191SN/A void updateThreadPriority(); 3711191SN/A 3721191SN/A /** Serialize state. */ 3731191SN/A virtual void serialize(std::ostream &os); 3741191SN/A 3751191SN/A /** Unserialize from a checkpoint. */ 3761191SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 3771191SN/A 3781191SN/A public: 3791191SN/A#if !FULL_SYSTEM 3801191SN/A /** Executes a syscall. 3811191SN/A * @todo: Determine if this needs to be virtual. 3822SN/A */ 383 void syscall(int64_t callnum, int tid); 384 385 /** Sets the return value of a syscall. */ 386 void setSyscallReturn(SyscallReturn return_value, int tid); 387 388#endif 389 390 /** Starts draining the CPU's pipeline of all instructions in 391 * order to stop all memory accesses. */ 392 virtual unsigned int drain(Event *drain_event); 393 394 /** Resumes execution after a drain. */ 395 virtual void resume(); 396 397 /** Signals to this CPU that a stage has completed switching out. */ 398 void signalDrained(); 399 400 /** Switches out this CPU. */ 401 virtual void switchOut(); 402 403 /** Takes over from another CPU. */ 404 virtual void takeOverFrom(BaseCPU *oldCPU); 405 406 /** Get the current instruction sequence number, and increment it. */ 407 InstSeqNum getAndIncrementInstSeq() 408 { return globalSeqNum++; } 409 410 /** Traps to handle given fault. */ 411 void trap(Fault fault, unsigned tid); 412 413#if FULL_SYSTEM 414 /** Posts an interrupt. */ 415 void post_interrupt(int int_num, int index); 416 417 /** HW return from error interrupt. */ 418 Fault hwrei(unsigned tid); 419 420 bool simPalCheck(int palFunc, unsigned tid); 421 422 /** Returns the Fault for any valid interrupt. */ 423 Fault getInterrupts(); 424 425 /** Processes any an interrupt fault. */ 426 void processInterrupts(Fault interrupt); 427 428 /** Halts the CPU. */ 429 void halt() { panic("Halt not implemented!\n"); } 430 431 /** Update the Virt and Phys ports of all ThreadContexts to 432 * reflect change in memory connections. */ 433 void updateMemPorts(); 434 435 /** Check if this address is a valid instruction address. */ 436 bool validInstAddr(Addr addr) { return true; } 437 438 /** Check if this address is a valid data address. */ 439 bool validDataAddr(Addr addr) { return true; } 440 441 /** Get instruction asid. */ 442 int getInstAsid(unsigned tid) 443 { return regFile.miscRegs[tid].getInstAsid(); } 444 445 /** Get data asid. */ 446 int getDataAsid(unsigned tid) 447 { return regFile.miscRegs[tid].getDataAsid(); } 448#else 449 /** Get instruction asid. */ 450 int getInstAsid(unsigned tid) 451 { return thread[tid]->getInstAsid(); } 452 453 /** Get data asid. */ 454 int getDataAsid(unsigned tid) 455 { return thread[tid]->getDataAsid(); } 456 457#endif 458 459 /** Register accessors. Index refers to the physical register index. */ 460 461 /** Reads a miscellaneous register. */ 462 TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); 463 464 /** Reads a misc. register, including any side effects the read 465 * might have as defined by the architecture. 466 */ 467 TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); 468 469 /** Sets a miscellaneous register. */ 470 void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); 471 472 /** Sets a misc. register, including any side effects the write 473 * might have as defined by the architecture. 474 */ 475 void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 476 unsigned tid); 477 478 uint64_t readIntReg(int reg_idx); 479 480 TheISA::FloatReg readFloatReg(int reg_idx); 481 482 TheISA::FloatReg readFloatReg(int reg_idx, int width); 483 484 TheISA::FloatRegBits readFloatRegBits(int reg_idx); 485 486 TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 487 488 void setIntReg(int reg_idx, uint64_t val); 489 490 void setFloatReg(int reg_idx, TheISA::FloatReg val); 491 492 void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 493 494 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 495 496 void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 497 498 uint64_t readArchIntReg(int reg_idx, unsigned tid); 499 500 float readArchFloatRegSingle(int reg_idx, unsigned tid); 501 502 double readArchFloatRegDouble(int reg_idx, unsigned tid); 503 504 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 505 506 /** Architectural register accessors. Looks up in the commit 507 * rename table to obtain the true physical index of the 508 * architected register first, then accesses that physical 509 * register. 510 */ 511 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 512 513 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 514 515 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 516 517 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 518 519 /** Reads the commit PC of a specific thread. */ 520 Addr readPC(unsigned tid); 521 522 /** Sets the commit PC of a specific thread. */ 523 void setPC(Addr new_PC, unsigned tid); 524 525 /** Reads the commit micro PC of a specific thread. */ 526 Addr readMicroPC(unsigned tid); 527 528 /** Sets the commmit micro PC of a specific thread. */ 529 void setMicroPC(Addr new_microPC, unsigned tid); 530 531 /** Reads the next PC of a specific thread. */ 532 Addr readNextPC(unsigned tid); 533 534 /** Sets the next PC of a specific thread. */ 535 void setNextPC(Addr val, unsigned tid); 536 537 /** Reads the next NPC of a specific thread. */ 538 Addr readNextNPC(unsigned tid); 539 540 /** Sets the next NPC of a specific thread. */ 541 void setNextNPC(Addr val, unsigned tid); 542 543 /** Reads the commit next micro PC of a specific thread. */ 544 Addr readNextMicroPC(unsigned tid); 545 546 /** Sets the commit next micro PC of a specific thread. */ 547 void setNextMicroPC(Addr val, unsigned tid); 548 549 /** Initiates a squash of all in-flight instructions for a given 550 * thread. The source of the squash is an external update of 551 * state through the TC. 552 */ 553 void squashFromTC(unsigned tid); 554 555 /** Function to add instruction onto the head of the list of the 556 * instructions. Used when new instructions are fetched. 557 */ 558 ListIt addInst(DynInstPtr &inst); 559 560 /** Function to tell the CPU that an instruction has completed. */ 561 void instDone(unsigned tid); 562 563 /** Add Instructions to the CPU Remove List*/ 564 void addToRemoveList(DynInstPtr &inst); 565 566 /** Remove an instruction from the front end of the list. There's 567 * no restriction on location of the instruction. 568 */ 569 void removeFrontInst(DynInstPtr &inst); 570 571 /** Remove all instructions that are not currently in the ROB. 572 * There's also an option to not squash delay slot instructions.*/ 573 void removeInstsNotInROB(unsigned tid); 574 575 /** Remove all instructions younger than the given sequence number. */ 576 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 577 578 /** Removes the instruction pointed to by the iterator. */ 579 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 580 581 /** Cleans up all instructions on the remove list. */ 582 void cleanUpRemovedInsts(); 583 584 /** Debug function to print all instructions on the list. */ 585 void dumpInsts(); 586 587 public: 588 /** List of all the instructions in flight. */ 589 std::list<DynInstPtr> instList; 590 591 /** List of all the instructions that will be removed at the end of this 592 * cycle. 593 */ 594 std::queue<ListIt> removeList; 595 596#ifdef DEBUG 597 /** Debug structure to keep track of the sequence numbers still in 598 * flight. 599 */ 600 std::set<InstSeqNum> snList; 601#endif 602 603 /** Records if instructions need to be removed this cycle due to 604 * being retired or squashed. 605 */ 606 bool removeInstsThisCycle; 607 608 protected: 609 /** The fetch stage. */ 610 typename CPUPolicy::Fetch fetch; 611 612 /** The decode stage. */ 613 typename CPUPolicy::Decode decode; 614 615 /** The dispatch stage. */ 616 typename CPUPolicy::Rename rename; 617 618 /** The issue/execute/writeback stages. */ 619 typename CPUPolicy::IEW iew; 620 621 /** The commit stage. */ 622 typename CPUPolicy::Commit commit; 623 624 /** The register file. */ 625 typename CPUPolicy::RegFile regFile; 626 627 /** The free list. */ 628 typename CPUPolicy::FreeList freeList; 629 630 /** The rename map. */ 631 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 632 633 /** The commit rename map. */ 634 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 635 636 /** The re-order buffer. */ 637 typename CPUPolicy::ROB rob; 638 639 /** Active Threads List */ 640 std::list<unsigned> activeThreads; 641 642 /** Integer Register Scoreboard */ 643 Scoreboard scoreboard; 644 645 public: 646 /** Enum to give each stage a specific index, so when calling 647 * activateStage() or deactivateStage(), they can specify which stage 648 * is being activated/deactivated. 649 */ 650 enum StageIdx { 651 FetchIdx, 652 DecodeIdx, 653 RenameIdx, 654 IEWIdx, 655 CommitIdx, 656 NumStages }; 657 658 /** Typedefs from the Impl to get the structs that each of the 659 * time buffers should use. 660 */ 661 typedef typename CPUPolicy::TimeStruct TimeStruct; 662 663 typedef typename CPUPolicy::FetchStruct FetchStruct; 664 665 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 666 667 typedef typename CPUPolicy::RenameStruct RenameStruct; 668 669 typedef typename CPUPolicy::IEWStruct IEWStruct; 670 671 /** The main time buffer to do backwards communication. */ 672 TimeBuffer<TimeStruct> timeBuffer; 673 674 /** The fetch stage's instruction queue. */ 675 TimeBuffer<FetchStruct> fetchQueue; 676 677 /** The decode stage's instruction queue. */ 678 TimeBuffer<DecodeStruct> decodeQueue; 679 680 /** The rename stage's instruction queue. */ 681 TimeBuffer<RenameStruct> renameQueue; 682 683 /** The IEW stage's instruction queue. */ 684 TimeBuffer<IEWStruct> iewQueue; 685 686 private: 687 /** The activity recorder; used to tell if the CPU has any 688 * activity remaining or if it can go to idle and deschedule 689 * itself. 690 */ 691 ActivityRecorder activityRec; 692 693 public: 694 /** Records that there was time buffer activity this cycle. */ 695 void activityThisCycle() { activityRec.activity(); } 696 697 /** Changes a stage's status to active within the activity recorder. */ 698 void activateStage(const StageIdx idx) 699 { activityRec.activateStage(idx); } 700 701 /** Changes a stage's status to inactive within the activity recorder. */ 702 void deactivateStage(const StageIdx idx) 703 { activityRec.deactivateStage(idx); } 704 705 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 706 void wakeCPU(); 707 708 /** Gets a free thread id. Use if thread ids change across system. */ 709 int getFreeTid(); 710 711 public: 712 /** Returns a pointer to a thread context. */ 713 ThreadContext *tcBase(unsigned tid) 714 { 715 return thread[tid]->getTC(); 716 } 717 718 /** The global sequence number counter. */ 719 InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 720 721#if USE_CHECKER 722 /** Pointer to the checker, which can dynamically verify 723 * instruction results at run time. This can be set to NULL if it 724 * is not being used. 725 */ 726 Checker<DynInstPtr> *checker; 727#endif 728 729#if FULL_SYSTEM 730 /** Pointer to the system. */ 731 System *system; 732 733 /** Pointer to physical memory. */ 734 PhysicalMemory *physmem; 735#endif 736 737 /** Event to call process() on once draining has completed. */ 738 Event *drainEvent; 739 740 /** Counter of how many stages have completed draining. */ 741 int drainCount; 742 743 /** Pointers to all of the threads in the CPU. */ 744 std::vector<Thread *> thread; 745 746 /** Whether or not the CPU should defer its registration. */ 747 bool deferRegistration; 748 749 /** Is there a context switch pending? */ 750 bool contextSwitch; 751 752 /** Threads Scheduled to Enter CPU */ 753 std::list<int> cpuWaitList; 754 755 /** The cycle that the CPU was last running, used for statistics. */ 756 Tick lastRunningCycle; 757 758 /** The cycle that the CPU was last activated by a new thread*/ 759 Tick lastActivatedCycle; 760 761 /** Number of Threads CPU can process */ 762 unsigned numThreads; 763 764 /** Mapping for system thread id to cpu id */ 765 std::map<unsigned,unsigned> threadMap; 766 767 /** Available thread ids in the cpu*/ 768 std::vector<unsigned> tids; 769 770 /** CPU read function, forwards read to LSQ. */ 771 template <class T> 772 Fault read(RequestPtr &req, T &data, int load_idx) 773 { 774 return this->iew.ldstQueue.read(req, data, load_idx); 775 } 776 777 /** CPU write function, forwards write to LSQ. */ 778 template <class T> 779 Fault write(RequestPtr &req, T &data, int store_idx) 780 { 781 return this->iew.ldstQueue.write(req, data, store_idx); 782 } 783 784 Addr lockAddr; 785 786 /** Temporary fix for the lock flag, works in the UP case. */ 787 bool lockFlag; 788 789 /** Stat for total number of times the CPU is descheduled. */ 790 Stats::Scalar<> timesIdled; 791 /** Stat for total number of cycles the CPU spends descheduled. */ 792 Stats::Scalar<> idleCycles; 793 /** Stat for the number of committed instructions per thread. */ 794 Stats::Vector<> committedInsts; 795 /** Stat for the total number of committed instructions. */ 796 Stats::Scalar<> totalCommittedInsts; 797 /** Stat for the CPI per thread. */ 798 Stats::Formula cpi; 799 /** Stat for the total CPI. */ 800 Stats::Formula totalCpi; 801 /** Stat for the IPC per thread. */ 802 Stats::Formula ipc; 803 /** Stat for the total IPC. */ 804 Stats::Formula totalIpc; 805}; 806 807#endif // __CPU_O3_CPU_HH__ 808