cpu.hh revision 5358:e9acb84bbafb
17119SN/A/*
27119SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
37119SN/A * All rights reserved.
47119SN/A *
57119SN/A * Redistribution and use in source and binary forms, with or without
67119SN/A * modification, are permitted provided that the following conditions are
77119SN/A * met: redistributions of source code must retain the above copyright
87119SN/A * notice, this list of conditions and the following disclaimer;
97119SN/A * redistributions in binary form must reproduce the above copyright
107119SN/A * notice, this list of conditions and the following disclaimer in the
117119SN/A * documentation and/or other materials provided with the distribution;
127119SN/A * neither the name of the copyright holders nor the names of its
137119SN/A * contributors may be used to endorse or promote products derived from
147119SN/A * this software without specific prior written permission.
157119SN/A *
167119SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
177119SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
187119SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
197119SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
207119SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
217119SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
227119SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
237119SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
247119SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
257119SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
267119SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
277119SN/A *
287119SN/A * Authors: Kevin Lim
297119SN/A *          Korey Sewell
307119SN/A */
317119SN/A
327119SN/A#ifndef __CPU_O3_CPU_HH__
337119SN/A#define __CPU_O3_CPU_HH__
347119SN/A
357119SN/A#include <iostream>
367119SN/A#include <list>
377119SN/A#include <queue>
387119SN/A#include <set>
397119SN/A#include <vector>
407119SN/A
417119SN/A#include "arch/types.hh"
427119SN/A#include "base/statistics.hh"
437119SN/A#include "base/timebuf.hh"
447119SN/A#include "config/full_system.hh"
457119SN/A#include "config/use_checker.hh"
467590Sgblack@eecs.umich.edu#include "cpu/activity.hh"
477590Sgblack@eecs.umich.edu#include "cpu/base.hh"
487119SN/A#include "cpu/simple_thread.hh"
497590Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh"
507590Sgblack@eecs.umich.edu#include "cpu/o3/cpu_policy.hh"
517590Sgblack@eecs.umich.edu#include "cpu/o3/scoreboard.hh"
527590Sgblack@eecs.umich.edu#include "cpu/o3/thread_state.hh"
537590Sgblack@eecs.umich.edu//#include "cpu/o3/thread_context.hh"
547590Sgblack@eecs.umich.edu#include "sim/process.hh"
557590Sgblack@eecs.umich.edu
567590Sgblack@eecs.umich.edutemplate <class>
577590Sgblack@eecs.umich.educlass Checker;
587590Sgblack@eecs.umich.educlass ThreadContext;
597590Sgblack@eecs.umich.edutemplate <class>
607590Sgblack@eecs.umich.educlass O3ThreadContext;
617590Sgblack@eecs.umich.edu
627590Sgblack@eecs.umich.educlass Checkpoint;
637590Sgblack@eecs.umich.educlass MemObject;
647590Sgblack@eecs.umich.educlass Process;
657590Sgblack@eecs.umich.edu
667590Sgblack@eecs.umich.educlass BaseO3CPU : public BaseCPU
677590Sgblack@eecs.umich.edu{
687590Sgblack@eecs.umich.edu    //Stuff that's pretty ISA independent will go here.
697590Sgblack@eecs.umich.edu  public:
707590Sgblack@eecs.umich.edu    typedef BaseCPU::Params Params;
717590Sgblack@eecs.umich.edu
727590Sgblack@eecs.umich.edu    BaseO3CPU(Params *params);
737590Sgblack@eecs.umich.edu
747590Sgblack@eecs.umich.edu    void regStats();
757590Sgblack@eecs.umich.edu
767590Sgblack@eecs.umich.edu    /** Sets this CPU's ID. */
777590Sgblack@eecs.umich.edu    void setCpuId(int id) { cpu_id = id; }
787590Sgblack@eecs.umich.edu
797590Sgblack@eecs.umich.edu    /** Reads this CPU's ID. */
807590Sgblack@eecs.umich.edu    int readCpuId() { return cpu_id; }
817590Sgblack@eecs.umich.edu
827590Sgblack@eecs.umich.edu  protected:
837590Sgblack@eecs.umich.edu    int cpu_id;
847590Sgblack@eecs.umich.edu};
857590Sgblack@eecs.umich.edu
867590Sgblack@eecs.umich.edu/**
877590Sgblack@eecs.umich.edu * FullO3CPU class, has each of the stages (fetch through commit)
887590Sgblack@eecs.umich.edu * within it, as well as all of the time buffers between stages.  The
897590Sgblack@eecs.umich.edu * tick() function for the CPU is defined here.
907590Sgblack@eecs.umich.edu */
917590Sgblack@eecs.umich.edutemplate <class Impl>
927590Sgblack@eecs.umich.educlass FullO3CPU : public BaseO3CPU
937590Sgblack@eecs.umich.edu{
947590Sgblack@eecs.umich.edu  public:
957590Sgblack@eecs.umich.edu    // Typedefs from the Impl here.
967590Sgblack@eecs.umich.edu    typedef typename Impl::CPUPol CPUPolicy;
977590Sgblack@eecs.umich.edu    typedef typename Impl::DynInstPtr DynInstPtr;
987590Sgblack@eecs.umich.edu    typedef typename Impl::O3CPU O3CPU;
997590Sgblack@eecs.umich.edu    typedef typename Impl::Params Params;
1007590Sgblack@eecs.umich.edu
1017590Sgblack@eecs.umich.edu    typedef O3ThreadState<Impl> Thread;
1027590Sgblack@eecs.umich.edu
1037590Sgblack@eecs.umich.edu    typedef typename std::list<DynInstPtr>::iterator ListIt;
1047590Sgblack@eecs.umich.edu
1057590Sgblack@eecs.umich.edu    friend class O3ThreadContext<Impl>;
1067590Sgblack@eecs.umich.edu
1077590Sgblack@eecs.umich.edu  public:
1087590Sgblack@eecs.umich.edu    enum Status {
1097590Sgblack@eecs.umich.edu        Running,
1107590Sgblack@eecs.umich.edu        Idle,
1117590Sgblack@eecs.umich.edu        Halted,
1127590Sgblack@eecs.umich.edu        Blocked,
1137590Sgblack@eecs.umich.edu        SwitchedOut
1147590Sgblack@eecs.umich.edu    };
1157590Sgblack@eecs.umich.edu
1167590Sgblack@eecs.umich.edu    TheISA::ITB * itb;
1177590Sgblack@eecs.umich.edu    TheISA::DTB * dtb;
1187590Sgblack@eecs.umich.edu
1197590Sgblack@eecs.umich.edu    /** Overall CPU status. */
1207590Sgblack@eecs.umich.edu    Status _status;
1217590Sgblack@eecs.umich.edu
1227590Sgblack@eecs.umich.edu    /** Per-thread status in CPU, used for SMT.  */
1237590Sgblack@eecs.umich.edu    Status _threadStatus[Impl::MaxThreads];
1247590Sgblack@eecs.umich.edu
1257590Sgblack@eecs.umich.edu  private:
1267590Sgblack@eecs.umich.edu    class TickEvent : public Event
1277590Sgblack@eecs.umich.edu    {
1287590Sgblack@eecs.umich.edu      private:
1297590Sgblack@eecs.umich.edu        /** Pointer to the CPU. */
1307590Sgblack@eecs.umich.edu        FullO3CPU<Impl> *cpu;
1317590Sgblack@eecs.umich.edu
1327590Sgblack@eecs.umich.edu      public:
1337590Sgblack@eecs.umich.edu        /** Constructs a tick event. */
1347590Sgblack@eecs.umich.edu        TickEvent(FullO3CPU<Impl> *c);
1357590Sgblack@eecs.umich.edu
1367590Sgblack@eecs.umich.edu        /** Processes a tick event, calling tick() on the CPU. */
1377590Sgblack@eecs.umich.edu        void process();
1387590Sgblack@eecs.umich.edu        /** Returns the description of the tick event. */
1397590Sgblack@eecs.umich.edu        const char *description() const;
1407590Sgblack@eecs.umich.edu    };
1417590Sgblack@eecs.umich.edu
1427590Sgblack@eecs.umich.edu    /** The tick event used for scheduling CPU ticks. */
1437590Sgblack@eecs.umich.edu    TickEvent tickEvent;
1447590Sgblack@eecs.umich.edu
1457590Sgblack@eecs.umich.edu    /** Schedule tick event, regardless of its current state. */
1467590Sgblack@eecs.umich.edu    void scheduleTickEvent(int delay)
1477590Sgblack@eecs.umich.edu    {
1487590Sgblack@eecs.umich.edu        if (tickEvent.squashed())
1497590Sgblack@eecs.umich.edu            tickEvent.reschedule(nextCycle(curTick + ticks(delay)));
1507590Sgblack@eecs.umich.edu        else if (!tickEvent.scheduled())
1517590Sgblack@eecs.umich.edu            tickEvent.schedule(nextCycle(curTick + ticks(delay)));
1527590Sgblack@eecs.umich.edu    }
1537590Sgblack@eecs.umich.edu
1547590Sgblack@eecs.umich.edu    /** Unschedule tick event, regardless of its current state. */
1557590Sgblack@eecs.umich.edu    void unscheduleTickEvent()
1567590Sgblack@eecs.umich.edu    {
1577590Sgblack@eecs.umich.edu        if (tickEvent.scheduled())
1587590Sgblack@eecs.umich.edu            tickEvent.squash();
1597590Sgblack@eecs.umich.edu    }
1607590Sgblack@eecs.umich.edu
1617590Sgblack@eecs.umich.edu    class ActivateThreadEvent : public Event
1627590Sgblack@eecs.umich.edu    {
1637590Sgblack@eecs.umich.edu      private:
1647590Sgblack@eecs.umich.edu        /** Number of Thread to Activate */
1657590Sgblack@eecs.umich.edu        int tid;
1667590Sgblack@eecs.umich.edu
1677590Sgblack@eecs.umich.edu        /** Pointer to the CPU. */
1687590Sgblack@eecs.umich.edu        FullO3CPU<Impl> *cpu;
1697590Sgblack@eecs.umich.edu
1707590Sgblack@eecs.umich.edu      public:
1717590Sgblack@eecs.umich.edu        /** Constructs the event. */
1727590Sgblack@eecs.umich.edu        ActivateThreadEvent();
1737590Sgblack@eecs.umich.edu
1747590Sgblack@eecs.umich.edu        /** Initialize Event */
1757590Sgblack@eecs.umich.edu        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
1767590Sgblack@eecs.umich.edu
1777590Sgblack@eecs.umich.edu        /** Processes the event, calling activateThread() on the CPU. */
1787590Sgblack@eecs.umich.edu        void process();
1797590Sgblack@eecs.umich.edu
1807590Sgblack@eecs.umich.edu        /** Returns the description of the event. */
1817590Sgblack@eecs.umich.edu        const char *description() const;
1827590Sgblack@eecs.umich.edu    };
1837590Sgblack@eecs.umich.edu
1847590Sgblack@eecs.umich.edu    /** Schedule thread to activate , regardless of its current state. */
1857590Sgblack@eecs.umich.edu    void scheduleActivateThreadEvent(int tid, int delay)
1867590Sgblack@eecs.umich.edu    {
1877590Sgblack@eecs.umich.edu        // Schedule thread to activate, regardless of its current state.
1887590Sgblack@eecs.umich.edu        if (activateThreadEvent[tid].squashed())
1897590Sgblack@eecs.umich.edu            activateThreadEvent[tid].
1907590Sgblack@eecs.umich.edu                reschedule(nextCycle(curTick + ticks(delay)));
1917590Sgblack@eecs.umich.edu        else if (!activateThreadEvent[tid].scheduled())
1927590Sgblack@eecs.umich.edu            activateThreadEvent[tid].
1937590Sgblack@eecs.umich.edu                schedule(nextCycle(curTick + ticks(delay)));
1947590Sgblack@eecs.umich.edu    }
1957590Sgblack@eecs.umich.edu
1967590Sgblack@eecs.umich.edu    /** Unschedule actiavte thread event, regardless of its current state. */
1977590Sgblack@eecs.umich.edu    void unscheduleActivateThreadEvent(int tid)
1987590Sgblack@eecs.umich.edu    {
1997590Sgblack@eecs.umich.edu        if (activateThreadEvent[tid].scheduled())
2007590Sgblack@eecs.umich.edu            activateThreadEvent[tid].squash();
2017590Sgblack@eecs.umich.edu    }
2027590Sgblack@eecs.umich.edu
2037590Sgblack@eecs.umich.edu    /** The tick event used for scheduling CPU ticks. */
2047590Sgblack@eecs.umich.edu    ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
2057590Sgblack@eecs.umich.edu
2067590Sgblack@eecs.umich.edu    class DeallocateContextEvent : public Event
2077590Sgblack@eecs.umich.edu    {
2087590Sgblack@eecs.umich.edu      private:
2097590Sgblack@eecs.umich.edu        /** Number of Thread to deactivate */
2107590Sgblack@eecs.umich.edu        int tid;
2117590Sgblack@eecs.umich.edu
2127590Sgblack@eecs.umich.edu        /** Should the thread be removed from the CPU? */
2137590Sgblack@eecs.umich.edu        bool remove;
2147590Sgblack@eecs.umich.edu
2157590Sgblack@eecs.umich.edu        /** Pointer to the CPU. */
2167590Sgblack@eecs.umich.edu        FullO3CPU<Impl> *cpu;
2177590Sgblack@eecs.umich.edu
2187590Sgblack@eecs.umich.edu      public:
2197590Sgblack@eecs.umich.edu        /** Constructs the event. */
2207590Sgblack@eecs.umich.edu        DeallocateContextEvent();
2217590Sgblack@eecs.umich.edu
2227590Sgblack@eecs.umich.edu        /** Initialize Event */
2237590Sgblack@eecs.umich.edu        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
2247590Sgblack@eecs.umich.edu
2257590Sgblack@eecs.umich.edu        /** Processes the event, calling activateThread() on the CPU. */
2267590Sgblack@eecs.umich.edu        void process();
2277590Sgblack@eecs.umich.edu
2287590Sgblack@eecs.umich.edu        /** Sets whether the thread should also be removed from the CPU. */
2297590Sgblack@eecs.umich.edu        void setRemove(bool _remove) { remove = _remove; }
2307590Sgblack@eecs.umich.edu
2317590Sgblack@eecs.umich.edu        /** Returns the description of the event. */
2327590Sgblack@eecs.umich.edu        const char *description() const;
2337590Sgblack@eecs.umich.edu    };
2347590Sgblack@eecs.umich.edu
2357590Sgblack@eecs.umich.edu    /** Schedule cpu to deallocate thread context.*/
2367590Sgblack@eecs.umich.edu    void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
2377590Sgblack@eecs.umich.edu    {
2387590Sgblack@eecs.umich.edu        // Schedule thread to activate, regardless of its current state.
2397590Sgblack@eecs.umich.edu        if (deallocateContextEvent[tid].squashed())
2407590Sgblack@eecs.umich.edu            deallocateContextEvent[tid].
2417590Sgblack@eecs.umich.edu                reschedule(nextCycle(curTick + ticks(delay)));
2427590Sgblack@eecs.umich.edu        else if (!deallocateContextEvent[tid].scheduled())
2437590Sgblack@eecs.umich.edu            deallocateContextEvent[tid].
2447590Sgblack@eecs.umich.edu                schedule(nextCycle(curTick + ticks(delay)));
2457590Sgblack@eecs.umich.edu    }
2467590Sgblack@eecs.umich.edu
2477590Sgblack@eecs.umich.edu    /** Unschedule thread deallocation in CPU */
2487590Sgblack@eecs.umich.edu    void unscheduleDeallocateContextEvent(int tid)
2497590Sgblack@eecs.umich.edu    {
2507590Sgblack@eecs.umich.edu        if (deallocateContextEvent[tid].scheduled())
2517590Sgblack@eecs.umich.edu            deallocateContextEvent[tid].squash();
2527590Sgblack@eecs.umich.edu    }
2537590Sgblack@eecs.umich.edu
2547590Sgblack@eecs.umich.edu    /** The tick event used for scheduling CPU ticks. */
2557590Sgblack@eecs.umich.edu    DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
2567590Sgblack@eecs.umich.edu
2577590Sgblack@eecs.umich.edu  public:
2587590Sgblack@eecs.umich.edu    /** Constructs a CPU with the given parameters. */
2597590Sgblack@eecs.umich.edu    FullO3CPU(O3CPU *o3_cpu, Params *params);
2607590Sgblack@eecs.umich.edu    /** Destructor. */
2617590Sgblack@eecs.umich.edu    ~FullO3CPU();
2627590Sgblack@eecs.umich.edu
2637590Sgblack@eecs.umich.edu    /** Registers statistics. */
2647590Sgblack@eecs.umich.edu    void fullCPURegStats();
2657590Sgblack@eecs.umich.edu
2667119SN/A    void demapPage(Addr vaddr, uint64_t asn)
2677128Sgblack@eecs.umich.edu    {
2687590Sgblack@eecs.umich.edu        this->itb->demapPage(vaddr, asn);
2697590Sgblack@eecs.umich.edu        this->dtb->demapPage(vaddr, asn);
2707590Sgblack@eecs.umich.edu    }
2717590Sgblack@eecs.umich.edu
2727590Sgblack@eecs.umich.edu    void demapInstPage(Addr vaddr, uint64_t asn)
2737590Sgblack@eecs.umich.edu    {
2747590Sgblack@eecs.umich.edu        this->itb->demapPage(vaddr, asn);
2757590Sgblack@eecs.umich.edu    }
2767590Sgblack@eecs.umich.edu
2777590Sgblack@eecs.umich.edu    void demapDataPage(Addr vaddr, uint64_t asn)
2787590Sgblack@eecs.umich.edu    {
2797590Sgblack@eecs.umich.edu        this->dtb->demapPage(vaddr, asn);
2807590Sgblack@eecs.umich.edu    }
2817590Sgblack@eecs.umich.edu
2827590Sgblack@eecs.umich.edu    /** Translates instruction requestion. */
2837590Sgblack@eecs.umich.edu    Fault translateInstReq(RequestPtr &req, Thread *thread)
2847128Sgblack@eecs.umich.edu    {
2857128Sgblack@eecs.umich.edu        return this->itb->translate(req, thread->getTC());
2867590Sgblack@eecs.umich.edu    }
2877128Sgblack@eecs.umich.edu
2887590Sgblack@eecs.umich.edu    /** Translates data read request. */
2897590Sgblack@eecs.umich.edu    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
2907590Sgblack@eecs.umich.edu    {
2917590Sgblack@eecs.umich.edu        return this->dtb->translate(req, thread->getTC(), false);
2927128Sgblack@eecs.umich.edu    }
2937120Sgblack@eecs.umich.edu
2947590Sgblack@eecs.umich.edu    /** Translates data write request. */
2957590Sgblack@eecs.umich.edu    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
2967590Sgblack@eecs.umich.edu    {
2977590Sgblack@eecs.umich.edu        return this->dtb->translate(req, thread->getTC(), true);
2987590Sgblack@eecs.umich.edu    }
2997590Sgblack@eecs.umich.edu
3007590Sgblack@eecs.umich.edu    /** Returns a specific port. */
3017590Sgblack@eecs.umich.edu    Port *getPort(const std::string &if_name, int idx);
3027590Sgblack@eecs.umich.edu
3037590Sgblack@eecs.umich.edu    /** Ticks CPU, calling tick() on each stage, and checking the overall
3047590Sgblack@eecs.umich.edu     *  activity to see if the CPU should deschedule itself.
3057590Sgblack@eecs.umich.edu     */
3067119SN/A    void tick();
3077128Sgblack@eecs.umich.edu
3087590Sgblack@eecs.umich.edu    /** Initialize the CPU */
3097590Sgblack@eecs.umich.edu    void init();
3107590Sgblack@eecs.umich.edu
3117590Sgblack@eecs.umich.edu    /** Returns the Number of Active Threads in the CPU */
3127590Sgblack@eecs.umich.edu    int numActiveThreads()
3137590Sgblack@eecs.umich.edu    { return activeThreads.size(); }
3147590Sgblack@eecs.umich.edu
3157590Sgblack@eecs.umich.edu    /** Add Thread to Active Threads List */
3167590Sgblack@eecs.umich.edu    void activateThread(unsigned tid);
3177590Sgblack@eecs.umich.edu
3187590Sgblack@eecs.umich.edu    /** Remove Thread from Active Threads List */
3197590Sgblack@eecs.umich.edu    void deactivateThread(unsigned tid);
3207128Sgblack@eecs.umich.edu
3217313Sgblack@eecs.umich.edu    /** Setup CPU to insert a thread's context */
3227590Sgblack@eecs.umich.edu    void insertThread(unsigned tid);
3237590Sgblack@eecs.umich.edu
3247590Sgblack@eecs.umich.edu    /** Remove all of a thread's context from CPU */
3257590Sgblack@eecs.umich.edu    void removeThread(unsigned tid);
3267590Sgblack@eecs.umich.edu
3277590Sgblack@eecs.umich.edu    /** Count the Total Instructions Committed in the CPU. */
3287590Sgblack@eecs.umich.edu    virtual Counter totalInstructions() const
3297590Sgblack@eecs.umich.edu    {
3307313Sgblack@eecs.umich.edu        Counter total(0);
3317120Sgblack@eecs.umich.edu
3327120Sgblack@eecs.umich.edu        for (int i=0; i < thread.size(); i++)
3337120Sgblack@eecs.umich.edu            total += thread[i]->numInst;
3347120Sgblack@eecs.umich.edu
3357120Sgblack@eecs.umich.edu        return total;
3367120Sgblack@eecs.umich.edu    }
3377128Sgblack@eecs.umich.edu
3387313Sgblack@eecs.umich.edu    /** Add Thread to Active Threads List. */
3397313Sgblack@eecs.umich.edu    void activateContext(int tid, int delay);
3407128Sgblack@eecs.umich.edu
3417303Sgblack@eecs.umich.edu    /** Remove Thread from Active Threads List */
3427590Sgblack@eecs.umich.edu    void suspendContext(int tid);
3437590Sgblack@eecs.umich.edu
3447590Sgblack@eecs.umich.edu    /** Remove Thread from Active Threads List &&
3457590Sgblack@eecs.umich.edu     *  Possibly Remove Thread Context from CPU.
3467345Sgblack@eecs.umich.edu     */
3477590Sgblack@eecs.umich.edu    bool deallocateContext(int tid, bool remove, int delay = 1);
3487590Sgblack@eecs.umich.edu
3497590Sgblack@eecs.umich.edu    /** Remove Thread from Active Threads List &&
3507590Sgblack@eecs.umich.edu     *  Remove Thread Context from CPU.
3517119SN/A     */
352    void haltContext(int tid);
353
354    /** Activate a Thread When CPU Resources are Available. */
355    void activateWhenReady(int tid);
356
357    /** Add or Remove a Thread Context in the CPU. */
358    void doContextSwitch();
359
360    /** Update The Order In Which We Process Threads. */
361    void updateThreadPriority();
362
363    /** Serialize state. */
364    virtual void serialize(std::ostream &os);
365
366    /** Unserialize from a checkpoint. */
367    virtual void unserialize(Checkpoint *cp, const std::string &section);
368
369  public:
370    /** Executes a syscall on this cycle.
371     *  ---------------------------------------
372     *  Note: this is a virtual function. CPU-Specific
373     *  functionality defined in derived classes
374     */
375    virtual void syscall(int tid) { panic("Unimplemented!"); }
376
377    /** Starts draining the CPU's pipeline of all instructions in
378     * order to stop all memory accesses. */
379    virtual unsigned int drain(Event *drain_event);
380
381    /** Resumes execution after a drain. */
382    virtual void resume();
383
384    /** Signals to this CPU that a stage has completed switching out. */
385    void signalDrained();
386
387    /** Switches out this CPU. */
388    virtual void switchOut();
389
390    /** Takes over from another CPU. */
391    virtual void takeOverFrom(BaseCPU *oldCPU);
392
393    /** Get the current instruction sequence number, and increment it. */
394    InstSeqNum getAndIncrementInstSeq()
395    { return globalSeqNum++; }
396
397#if FULL_SYSTEM
398    /** Update the Virt and Phys ports of all ThreadContexts to
399     * reflect change in memory connections. */
400    void updateMemPorts();
401
402    /** Check if this address is a valid instruction address. */
403    bool validInstAddr(Addr addr) { return true; }
404
405    /** Check if this address is a valid data address. */
406    bool validDataAddr(Addr addr) { return true; }
407
408    /** Get instruction asid. */
409    int getInstAsid(unsigned tid)
410    { return regFile.miscRegs[tid].getInstAsid(); }
411
412    /** Get data asid. */
413    int getDataAsid(unsigned tid)
414    { return regFile.miscRegs[tid].getDataAsid(); }
415#else
416    /** Get instruction asid. */
417    int getInstAsid(unsigned tid)
418    { return thread[tid]->getInstAsid(); }
419
420    /** Get data asid. */
421    int getDataAsid(unsigned tid)
422    { return thread[tid]->getDataAsid(); }
423
424#endif
425
426    /** Register accessors.  Index refers to the physical register index. */
427    uint64_t readIntReg(int reg_idx);
428
429    TheISA::FloatReg readFloatReg(int reg_idx);
430
431    TheISA::FloatReg readFloatReg(int reg_idx, int width);
432
433    TheISA::FloatRegBits readFloatRegBits(int reg_idx);
434
435    TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
436
437    void setIntReg(int reg_idx, uint64_t val);
438
439    void setFloatReg(int reg_idx, TheISA::FloatReg val);
440
441    void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
442
443    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
444
445    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
446
447    uint64_t readArchIntReg(int reg_idx, unsigned tid);
448
449    float readArchFloatRegSingle(int reg_idx, unsigned tid);
450
451    double readArchFloatRegDouble(int reg_idx, unsigned tid);
452
453    uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
454
455    /** Architectural register accessors.  Looks up in the commit
456     * rename table to obtain the true physical index of the
457     * architected register first, then accesses that physical
458     * register.
459     */
460    void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
461
462    void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
463
464    void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
465
466    void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
467
468    /** Reads the commit PC of a specific thread. */
469    Addr readPC(unsigned tid);
470
471    /** Sets the commit PC of a specific thread. */
472    void setPC(Addr new_PC, unsigned tid);
473
474    /** Reads the commit micro PC of a specific thread. */
475    Addr readMicroPC(unsigned tid);
476
477    /** Sets the commmit micro PC of a specific thread. */
478    void setMicroPC(Addr new_microPC, unsigned tid);
479
480    /** Reads the next PC of a specific thread. */
481    Addr readNextPC(unsigned tid);
482
483    /** Sets the next PC of a specific thread. */
484    void setNextPC(Addr val, unsigned tid);
485
486    /** Reads the next NPC of a specific thread. */
487    Addr readNextNPC(unsigned tid);
488
489    /** Sets the next NPC of a specific thread. */
490    void setNextNPC(Addr val, unsigned tid);
491
492    /** Reads the commit next micro PC of a specific thread. */
493    Addr readNextMicroPC(unsigned tid);
494
495    /** Sets the commit next micro PC of a specific thread. */
496    void setNextMicroPC(Addr val, unsigned tid);
497
498    /** Function to add instruction onto the head of the list of the
499     *  instructions.  Used when new instructions are fetched.
500     */
501    ListIt addInst(DynInstPtr &inst);
502
503    /** Function to tell the CPU that an instruction has completed. */
504    void instDone(unsigned tid);
505
506    /** Add Instructions to the CPU Remove List*/
507    void addToRemoveList(DynInstPtr &inst);
508
509    /** Remove an instruction from the front end of the list.  There's
510     *  no restriction on location of the instruction.
511     */
512    void removeFrontInst(DynInstPtr &inst);
513
514    /** Remove all instructions that are not currently in the ROB.
515     *  There's also an option to not squash delay slot instructions.*/
516    void removeInstsNotInROB(unsigned tid);
517
518    /** Remove all instructions younger than the given sequence number. */
519    void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
520
521    /** Removes the instruction pointed to by the iterator. */
522    inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
523
524    /** Cleans up all instructions on the remove list. */
525    void cleanUpRemovedInsts();
526
527    /** Debug function to print all instructions on the list. */
528    void dumpInsts();
529
530  public:
531    /** List of all the instructions in flight. */
532    std::list<DynInstPtr> instList;
533
534    /** List of all the instructions that will be removed at the end of this
535     *  cycle.
536     */
537    std::queue<ListIt> removeList;
538
539#ifdef DEBUG
540    /** Debug structure to keep track of the sequence numbers still in
541     * flight.
542     */
543    std::set<InstSeqNum> snList;
544#endif
545
546    /** Records if instructions need to be removed this cycle due to
547     *  being retired or squashed.
548     */
549    bool removeInstsThisCycle;
550
551  protected:
552    /** The fetch stage. */
553    typename CPUPolicy::Fetch fetch;
554
555    /** The decode stage. */
556    typename CPUPolicy::Decode decode;
557
558    /** The dispatch stage. */
559    typename CPUPolicy::Rename rename;
560
561    /** The issue/execute/writeback stages. */
562    typename CPUPolicy::IEW iew;
563
564    /** The commit stage. */
565    typename CPUPolicy::Commit commit;
566
567    /** The register file. */
568    typename CPUPolicy::RegFile regFile;
569
570    /** The free list. */
571    typename CPUPolicy::FreeList freeList;
572
573    /** The rename map. */
574    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
575
576    /** The commit rename map. */
577    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
578
579    /** The re-order buffer. */
580    typename CPUPolicy::ROB rob;
581
582    /** Active Threads List */
583    std::list<unsigned> activeThreads;
584
585    /** Integer Register Scoreboard */
586    Scoreboard scoreboard;
587
588  public:
589    /** Enum to give each stage a specific index, so when calling
590     *  activateStage() or deactivateStage(), they can specify which stage
591     *  is being activated/deactivated.
592     */
593    enum StageIdx {
594        FetchIdx,
595        DecodeIdx,
596        RenameIdx,
597        IEWIdx,
598        CommitIdx,
599        NumStages };
600
601    /** Typedefs from the Impl to get the structs that each of the
602     *  time buffers should use.
603     */
604    typedef typename CPUPolicy::TimeStruct TimeStruct;
605
606    typedef typename CPUPolicy::FetchStruct FetchStruct;
607
608    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
609
610    typedef typename CPUPolicy::RenameStruct RenameStruct;
611
612    typedef typename CPUPolicy::IEWStruct IEWStruct;
613
614    /** The main time buffer to do backwards communication. */
615    TimeBuffer<TimeStruct> timeBuffer;
616
617    /** The fetch stage's instruction queue. */
618    TimeBuffer<FetchStruct> fetchQueue;
619
620    /** The decode stage's instruction queue. */
621    TimeBuffer<DecodeStruct> decodeQueue;
622
623    /** The rename stage's instruction queue. */
624    TimeBuffer<RenameStruct> renameQueue;
625
626    /** The IEW stage's instruction queue. */
627    TimeBuffer<IEWStruct> iewQueue;
628
629  private:
630    /** The activity recorder; used to tell if the CPU has any
631     * activity remaining or if it can go to idle and deschedule
632     * itself.
633     */
634    ActivityRecorder activityRec;
635
636  public:
637    /** Records that there was time buffer activity this cycle. */
638    void activityThisCycle() { activityRec.activity(); }
639
640    /** Changes a stage's status to active within the activity recorder. */
641    void activateStage(const StageIdx idx)
642    { activityRec.activateStage(idx); }
643
644    /** Changes a stage's status to inactive within the activity recorder. */
645    void deactivateStage(const StageIdx idx)
646    { activityRec.deactivateStage(idx); }
647
648    /** Wakes the CPU, rescheduling the CPU if it's not already active. */
649    void wakeCPU();
650
651    /** Gets a free thread id. Use if thread ids change across system. */
652    int getFreeTid();
653
654  public:
655    /** Returns a pointer to a thread context. */
656    ThreadContext *tcBase(unsigned tid)
657    {
658        return thread[tid]->getTC();
659    }
660
661    /** The global sequence number counter. */
662    InstSeqNum globalSeqNum;//[Impl::MaxThreads];
663
664#if USE_CHECKER
665    /** Pointer to the checker, which can dynamically verify
666     * instruction results at run time.  This can be set to NULL if it
667     * is not being used.
668     */
669    Checker<DynInstPtr> *checker;
670#endif
671
672#if FULL_SYSTEM
673    /** Pointer to the system. */
674    System *system;
675
676    /** Pointer to physical memory. */
677    PhysicalMemory *physmem;
678#endif
679
680    /** Event to call process() on once draining has completed. */
681    Event *drainEvent;
682
683    /** Counter of how many stages have completed draining. */
684    int drainCount;
685
686    /** Pointers to all of the threads in the CPU. */
687    std::vector<Thread *> thread;
688
689    /** Whether or not the CPU should defer its registration. */
690    bool deferRegistration;
691
692    /** Is there a context switch pending? */
693    bool contextSwitch;
694
695    /** Threads Scheduled to Enter CPU */
696    std::list<int> cpuWaitList;
697
698    /** The cycle that the CPU was last running, used for statistics. */
699    Tick lastRunningCycle;
700
701    /** The cycle that the CPU was last activated by a new thread*/
702    Tick lastActivatedCycle;
703
704    /** Number of Threads CPU can process */
705    unsigned numThreads;
706
707    /** Mapping for system thread id to cpu id */
708    std::map<unsigned,unsigned> threadMap;
709
710    /** Available thread ids in the cpu*/
711    std::vector<unsigned> tids;
712
713    /** Stat for total number of times the CPU is descheduled. */
714    Stats::Scalar<> timesIdled;
715    /** Stat for total number of cycles the CPU spends descheduled. */
716    Stats::Scalar<> idleCycles;
717    /** Stat for the number of committed instructions per thread. */
718    Stats::Vector<> committedInsts;
719    /** Stat for the total number of committed instructions. */
720    Stats::Scalar<> totalCommittedInsts;
721    /** Stat for the CPI per thread. */
722    Stats::Formula cpi;
723    /** Stat for the total CPI. */
724    Stats::Formula totalCpi;
725    /** Stat for the IPC per thread. */
726    Stats::Formula ipc;
727    /** Stat for the total IPC. */
728    Stats::Formula totalIpc;
729};
730
731#endif // __CPU_O3_CPU_HH__
732