cpu.hh revision 2980:eab855f06b79
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_CPU_HH__
33#define __CPU_O3_CPU_HH__
34
35#include <iostream>
36#include <list>
37#include <queue>
38#include <set>
39#include <vector>
40
41#include "arch/types.hh"
42#include "base/statistics.hh"
43#include "base/timebuf.hh"
44#include "config/full_system.hh"
45#include "cpu/activity.hh"
46#include "cpu/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/o3/comm.hh"
49#include "cpu/o3/cpu_policy.hh"
50#include "cpu/o3/scoreboard.hh"
51#include "cpu/o3/thread_state.hh"
52//#include "cpu/o3/thread_context.hh"
53#include "sim/process.hh"
54
55template <class>
56class Checker;
57class ThreadContext;
58template <class>
59class O3ThreadContext;
60
61class Checkpoint;
62class MemObject;
63class Process;
64
65class BaseO3CPU : public BaseCPU
66{
67    //Stuff that's pretty ISA independent will go here.
68  public:
69    typedef BaseCPU::Params Params;
70
71    BaseO3CPU(Params *params);
72
73    void regStats();
74
75    /** Sets this CPU's ID. */
76    void setCpuId(int id) { cpu_id = id; }
77
78    /** Reads this CPU's ID. */
79    int readCpuId() { return cpu_id; }
80
81  protected:
82    int cpu_id;
83};
84
85/**
86 * FullO3CPU class, has each of the stages (fetch through commit)
87 * within it, as well as all of the time buffers between stages.  The
88 * tick() function for the CPU is defined here.
89 */
90template <class Impl>
91class FullO3CPU : public BaseO3CPU
92{
93  public:
94    typedef TheISA::FloatReg FloatReg;
95    typedef TheISA::FloatRegBits FloatRegBits;
96
97    // Typedefs from the Impl here.
98    typedef typename Impl::CPUPol CPUPolicy;
99    typedef typename Impl::Params Params;
100    typedef typename Impl::DynInstPtr DynInstPtr;
101
102    typedef O3ThreadState<Impl> Thread;
103
104    typedef typename std::list<DynInstPtr>::iterator ListIt;
105
106    friend class O3ThreadContext<Impl>;
107
108  public:
109    enum Status {
110        Running,
111        Idle,
112        Halted,
113        Blocked,
114        SwitchedOut
115    };
116
117    /** Overall CPU status. */
118    Status _status;
119
120    /** Per-thread status in CPU, used for SMT.  */
121    Status _threadStatus[Impl::MaxThreads];
122
123  private:
124    class TickEvent : public Event
125    {
126      private:
127        /** Pointer to the CPU. */
128        FullO3CPU<Impl> *cpu;
129
130      public:
131        /** Constructs a tick event. */
132        TickEvent(FullO3CPU<Impl> *c);
133
134        /** Processes a tick event, calling tick() on the CPU. */
135        void process();
136        /** Returns the description of the tick event. */
137        const char *description();
138    };
139
140    /** The tick event used for scheduling CPU ticks. */
141    TickEvent tickEvent;
142
143    /** Schedule tick event, regardless of its current state. */
144    void scheduleTickEvent(int delay)
145    {
146        if (tickEvent.squashed())
147            tickEvent.reschedule(curTick + cycles(delay));
148        else if (!tickEvent.scheduled())
149            tickEvent.schedule(curTick + cycles(delay));
150    }
151
152    /** Unschedule tick event, regardless of its current state. */
153    void unscheduleTickEvent()
154    {
155        if (tickEvent.scheduled())
156            tickEvent.squash();
157    }
158
159    class ActivateThreadEvent : public Event
160    {
161      private:
162        /** Number of Thread to Activate */
163        int tid;
164
165        /** Pointer to the CPU. */
166        FullO3CPU<Impl> *cpu;
167
168      public:
169        /** Constructs the event. */
170        ActivateThreadEvent();
171
172        /** Initialize Event */
173        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
174
175        /** Processes the event, calling activateThread() on the CPU. */
176        void process();
177
178        /** Returns the description of the event. */
179        const char *description();
180    };
181
182    /** Schedule thread to activate , regardless of its current state. */
183    void scheduleActivateThreadEvent(int tid, int delay)
184    {
185        // Schedule thread to activate, regardless of its current state.
186        if (activateThreadEvent[tid].squashed())
187            activateThreadEvent[tid].reschedule(curTick + cycles(delay));
188        else if (!activateThreadEvent[tid].scheduled())
189            activateThreadEvent[tid].schedule(curTick + cycles(delay));
190    }
191
192    /** Unschedule actiavte thread event, regardless of its current state. */
193    void unscheduleActivateThreadEvent(int tid)
194    {
195        if (activateThreadEvent[tid].scheduled())
196            activateThreadEvent[tid].squash();
197    }
198
199    /** The tick event used for scheduling CPU ticks. */
200    ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
201
202    class DeallocateContextEvent : public Event
203    {
204      private:
205        /** Number of Thread to Activate */
206        int tid;
207
208        /** Pointer to the CPU. */
209        FullO3CPU<Impl> *cpu;
210
211      public:
212        /** Constructs the event. */
213        DeallocateContextEvent();
214
215        /** Initialize Event */
216        void init(int thread_num, FullO3CPU<Impl> *thread_cpu);
217
218        /** Processes the event, calling activateThread() on the CPU. */
219        void process();
220
221        /** Returns the description of the event. */
222        const char *description();
223    };
224
225    /** Schedule cpu to deallocate thread context.*/
226    void scheduleDeallocateContextEvent(int tid, int delay)
227    {
228        // Schedule thread to activate, regardless of its current state.
229        if (deallocateContextEvent[tid].squashed())
230            deallocateContextEvent[tid].reschedule(curTick + cycles(delay));
231        else if (!deallocateContextEvent[tid].scheduled())
232            deallocateContextEvent[tid].schedule(curTick + cycles(delay));
233    }
234
235    /** Unschedule thread deallocation in CPU */
236    void unscheduleDeallocateContextEvent(int tid)
237    {
238        if (deallocateContextEvent[tid].scheduled())
239            deallocateContextEvent[tid].squash();
240    }
241
242    /** The tick event used for scheduling CPU ticks. */
243    DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads];
244
245  public:
246    /** Constructs a CPU with the given parameters. */
247    FullO3CPU(Params *params);
248    /** Destructor. */
249    ~FullO3CPU();
250
251    /** Registers statistics. */
252    void fullCPURegStats();
253
254    /** Returns a specific port. */
255    Port *getPort(const std::string &if_name, int idx);
256
257    /** Ticks CPU, calling tick() on each stage, and checking the overall
258     *  activity to see if the CPU should deschedule itself.
259     */
260    void tick();
261
262    /** Initialize the CPU */
263    void init();
264
265    /** Returns the Number of Active Threads in the CPU */
266    int numActiveThreads()
267    { return activeThreads.size(); }
268
269    /** Add Thread to Active Threads List */
270    void activateThread(unsigned tid);
271
272    /** Remove Thread from Active Threads List */
273    void deactivateThread(unsigned tid);
274
275    /** Setup CPU to insert a thread's context */
276    void insertThread(unsigned tid);
277
278    /** Remove all of a thread's context from CPU */
279    void removeThread(unsigned tid);
280
281    /** Count the Total Instructions Committed in the CPU. */
282    virtual Counter totalInstructions() const
283    {
284        Counter total(0);
285
286        for (int i=0; i < thread.size(); i++)
287            total += thread[i]->numInst;
288
289        return total;
290    }
291
292    /** Add Thread to Active Threads List. */
293    void activateContext(int tid, int delay);
294
295    /** Remove Thread from Active Threads List */
296    void suspendContext(int tid);
297
298    /** Remove Thread from Active Threads List &&
299     *  Remove Thread Context from CPU.
300     */
301    void deallocateContext(int tid, int delay = 1);
302
303    /** Remove Thread from Active Threads List &&
304     *  Remove Thread Context from CPU.
305     */
306    void haltContext(int tid);
307
308    /** Activate a Thread When CPU Resources are Available. */
309    void activateWhenReady(int tid);
310
311    /** Add or Remove a Thread Context in the CPU. */
312    void doContextSwitch();
313
314    /** Update The Order In Which We Process Threads. */
315    void updateThreadPriority();
316
317    /** Serialize state. */
318    virtual void serialize(std::ostream &os);
319
320    /** Unserialize from a checkpoint. */
321    virtual void unserialize(Checkpoint *cp, const std::string &section);
322
323  public:
324    /** Executes a syscall on this cycle.
325     *  ---------------------------------------
326     *  Note: this is a virtual function. CPU-Specific
327     *  functionality defined in derived classes
328     */
329    virtual void syscall(int tid) { panic("Unimplemented!"); }
330
331    /** Starts draining the CPU's pipeline of all instructions in
332     * order to stop all memory accesses. */
333    virtual unsigned int drain(Event *drain_event);
334
335    /** Resumes execution after a drain. */
336    virtual void resume();
337
338    /** Signals to this CPU that a stage has completed switching out. */
339    void signalDrained();
340
341    /** Switches out this CPU. */
342    virtual void switchOut();
343
344    /** Takes over from another CPU. */
345    virtual void takeOverFrom(BaseCPU *oldCPU);
346
347    /** Get the current instruction sequence number, and increment it. */
348    InstSeqNum getAndIncrementInstSeq()
349    { return globalSeqNum++; }
350
351#if FULL_SYSTEM
352    /** Check if this address is a valid instruction address. */
353    bool validInstAddr(Addr addr) { return true; }
354
355    /** Check if this address is a valid data address. */
356    bool validDataAddr(Addr addr) { return true; }
357
358    /** Get instruction asid. */
359    int getInstAsid(unsigned tid)
360    { return regFile.miscRegs[tid].getInstAsid(); }
361
362    /** Get data asid. */
363    int getDataAsid(unsigned tid)
364    { return regFile.miscRegs[tid].getDataAsid(); }
365#else
366    /** Get instruction asid. */
367    int getInstAsid(unsigned tid)
368    { return thread[tid]->getInstAsid(); }
369
370    /** Get data asid. */
371    int getDataAsid(unsigned tid)
372    { return thread[tid]->getDataAsid(); }
373
374#endif
375
376    /** Register accessors.  Index refers to the physical register index. */
377    uint64_t readIntReg(int reg_idx);
378
379    FloatReg readFloatReg(int reg_idx);
380
381    FloatReg readFloatReg(int reg_idx, int width);
382
383    FloatRegBits readFloatRegBits(int reg_idx);
384
385    FloatRegBits readFloatRegBits(int reg_idx, int width);
386
387    void setIntReg(int reg_idx, uint64_t val);
388
389    void setFloatReg(int reg_idx, FloatReg val);
390
391    void setFloatReg(int reg_idx, FloatReg val, int width);
392
393    void setFloatRegBits(int reg_idx, FloatRegBits val);
394
395    void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
396
397    uint64_t readArchIntReg(int reg_idx, unsigned tid);
398
399    float readArchFloatRegSingle(int reg_idx, unsigned tid);
400
401    double readArchFloatRegDouble(int reg_idx, unsigned tid);
402
403    uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
404
405    /** Architectural register accessors.  Looks up in the commit
406     * rename table to obtain the true physical index of the
407     * architected register first, then accesses that physical
408     * register.
409     */
410    void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
411
412    void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
413
414    void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
415
416    void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
417
418    /** Reads the commit PC of a specific thread. */
419    uint64_t readPC(unsigned tid);
420
421    /** Sets the commit PC of a specific thread. */
422    void setPC(Addr new_PC, unsigned tid);
423
424    /** Reads the next PC of a specific thread. */
425    uint64_t readNextPC(unsigned tid);
426
427    /** Sets the next PC of a specific thread. */
428    void setNextPC(uint64_t val, unsigned tid);
429
430    /** Reads the next NPC of a specific thread. */
431    uint64_t readNextNPC(unsigned tid);
432
433    /** Sets the next NPC of a specific thread. */
434    void setNextNPC(uint64_t val, unsigned tid);
435
436    /** Function to add instruction onto the head of the list of the
437     *  instructions.  Used when new instructions are fetched.
438     */
439    ListIt addInst(DynInstPtr &inst);
440
441    /** Function to tell the CPU that an instruction has completed. */
442    void instDone(unsigned tid);
443
444    /** Add Instructions to the CPU Remove List*/
445    void addToRemoveList(DynInstPtr &inst);
446
447    /** Remove an instruction from the front end of the list.  There's
448     *  no restriction on location of the instruction.
449     */
450    void removeFrontInst(DynInstPtr &inst);
451
452    /** Remove all instructions that are not currently in the ROB.
453     *  There's also an option to not squash delay slot instructions.*/
454    void removeInstsNotInROB(unsigned tid, bool squash_delay_slot,
455                             const InstSeqNum &delay_slot_seq_num);
456
457    /** Remove all instructions younger than the given sequence number. */
458    void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
459
460    /** Removes the instruction pointed to by the iterator. */
461    inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
462
463    /** Cleans up all instructions on the remove list. */
464    void cleanUpRemovedInsts();
465
466    /** Debug function to print all instructions on the list. */
467    void dumpInsts();
468
469  public:
470    /** List of all the instructions in flight. */
471    std::list<DynInstPtr> instList;
472
473    /** List of all the instructions that will be removed at the end of this
474     *  cycle.
475     */
476    std::queue<ListIt> removeList;
477
478#ifdef DEBUG
479    /** Debug structure to keep track of the sequence numbers still in
480     * flight.
481     */
482    std::set<InstSeqNum> snList;
483#endif
484
485    /** Records if instructions need to be removed this cycle due to
486     *  being retired or squashed.
487     */
488    bool removeInstsThisCycle;
489
490  protected:
491    /** The fetch stage. */
492    typename CPUPolicy::Fetch fetch;
493
494    /** The decode stage. */
495    typename CPUPolicy::Decode decode;
496
497    /** The dispatch stage. */
498    typename CPUPolicy::Rename rename;
499
500    /** The issue/execute/writeback stages. */
501    typename CPUPolicy::IEW iew;
502
503    /** The commit stage. */
504    typename CPUPolicy::Commit commit;
505
506    /** The register file. */
507    typename CPUPolicy::RegFile regFile;
508
509    /** The free list. */
510    typename CPUPolicy::FreeList freeList;
511
512    /** The rename map. */
513    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
514
515    /** The commit rename map. */
516    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
517
518    /** The re-order buffer. */
519    typename CPUPolicy::ROB rob;
520
521    /** Active Threads List */
522    std::list<unsigned> activeThreads;
523
524    /** Integer Register Scoreboard */
525    Scoreboard scoreboard;
526
527  public:
528    /** Enum to give each stage a specific index, so when calling
529     *  activateStage() or deactivateStage(), they can specify which stage
530     *  is being activated/deactivated.
531     */
532    enum StageIdx {
533        FetchIdx,
534        DecodeIdx,
535        RenameIdx,
536        IEWIdx,
537        CommitIdx,
538        NumStages };
539
540    /** Typedefs from the Impl to get the structs that each of the
541     *  time buffers should use.
542     */
543    typedef typename CPUPolicy::TimeStruct TimeStruct;
544
545    typedef typename CPUPolicy::FetchStruct FetchStruct;
546
547    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
548
549    typedef typename CPUPolicy::RenameStruct RenameStruct;
550
551    typedef typename CPUPolicy::IEWStruct IEWStruct;
552
553    /** The main time buffer to do backwards communication. */
554    TimeBuffer<TimeStruct> timeBuffer;
555
556    /** The fetch stage's instruction queue. */
557    TimeBuffer<FetchStruct> fetchQueue;
558
559    /** The decode stage's instruction queue. */
560    TimeBuffer<DecodeStruct> decodeQueue;
561
562    /** The rename stage's instruction queue. */
563    TimeBuffer<RenameStruct> renameQueue;
564
565    /** The IEW stage's instruction queue. */
566    TimeBuffer<IEWStruct> iewQueue;
567
568  private:
569    /** The activity recorder; used to tell if the CPU has any
570     * activity remaining or if it can go to idle and deschedule
571     * itself.
572     */
573    ActivityRecorder activityRec;
574
575  public:
576    /** Records that there was time buffer activity this cycle. */
577    void activityThisCycle() { activityRec.activity(); }
578
579    /** Changes a stage's status to active within the activity recorder. */
580    void activateStage(const StageIdx idx)
581    { activityRec.activateStage(idx); }
582
583    /** Changes a stage's status to inactive within the activity recorder. */
584    void deactivateStage(const StageIdx idx)
585    { activityRec.deactivateStage(idx); }
586
587    /** Wakes the CPU, rescheduling the CPU if it's not already active. */
588    void wakeCPU();
589
590    /** Gets a free thread id. Use if thread ids change across system. */
591    int getFreeTid();
592
593  public:
594    /** Returns a pointer to a thread context. */
595    ThreadContext *tcBase(unsigned tid)
596    {
597        return thread[tid]->getTC();
598    }
599
600    /** The global sequence number counter. */
601    InstSeqNum globalSeqNum;
602
603    /** Pointer to the checker, which can dynamically verify
604     * instruction results at run time.  This can be set to NULL if it
605     * is not being used.
606     */
607    Checker<DynInstPtr> *checker;
608
609#if FULL_SYSTEM
610    /** Pointer to the system. */
611    System *system;
612
613    /** Pointer to physical memory. */
614    PhysicalMemory *physmem;
615#endif
616
617    /** Pointer to memory. */
618    MemObject *mem;
619
620    /** Event to call process() on once draining has completed. */
621    Event *drainEvent;
622
623    /** Counter of how many stages have completed draining. */
624    int drainCount;
625
626    /** Pointers to all of the threads in the CPU. */
627    std::vector<Thread *> thread;
628
629    /** Pointer to the icache interface. */
630    MemInterface *icacheInterface;
631    /** Pointer to the dcache interface. */
632    MemInterface *dcacheInterface;
633
634    /** Whether or not the CPU should defer its registration. */
635    bool deferRegistration;
636
637    /** Is there a context switch pending? */
638    bool contextSwitch;
639
640    /** Threads Scheduled to Enter CPU */
641    std::list<int> cpuWaitList;
642
643    /** The cycle that the CPU was last running, used for statistics. */
644    Tick lastRunningCycle;
645
646    /** The cycle that the CPU was last activated by a new thread*/
647    Tick lastActivatedCycle;
648
649    /** Number of Threads CPU can process */
650    unsigned numThreads;
651
652    /** Mapping for system thread id to cpu id */
653    std::map<unsigned,unsigned> threadMap;
654
655    /** Available thread ids in the cpu*/
656    std::vector<unsigned> tids;
657
658    /** Stat for total number of times the CPU is descheduled. */
659    Stats::Scalar<> timesIdled;
660    /** Stat for total number of cycles the CPU spends descheduled. */
661    Stats::Scalar<> idleCycles;
662    /** Stat for the number of committed instructions per thread. */
663    Stats::Vector<> committedInsts;
664    /** Stat for the total number of committed instructions. */
665    Stats::Scalar<> totalCommittedInsts;
666    /** Stat for the CPI per thread. */
667    Stats::Formula cpi;
668    /** Stat for the total CPI. */
669    Stats::Formula totalCpi;
670    /** Stat for the IPC per thread. */
671    Stats::Formula ipc;
672    /** Stat for the total IPC. */
673    Stats::Formula totalIpc;
674};
675
676#endif // __CPU_O3_CPU_HH__
677