cpu.hh revision 13611:c8b7847b4171
1/*
2 * Copyright (c) 2011-2013, 2016-2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Korey Sewell
44 *          Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/generic/types.hh"
57#include "arch/types.hh"
58#include "base/statistics.hh"
59#include "config/the_isa.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/o3/cpu_policy.hh"
62#include "cpu/o3/scoreboard.hh"
63#include "cpu/o3/thread_state.hh"
64#include "cpu/activity.hh"
65#include "cpu/base.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/timebuf.hh"
68//#include "cpu/o3/thread_context.hh"
69#include "params/DerivO3CPU.hh"
70#include "sim/process.hh"
71
72template <class>
73class Checker;
74class ThreadContext;
75template <class>
76class O3ThreadContext;
77
78class Checkpoint;
79class MemObject;
80class Process;
81
82struct BaseCPUParams;
83
84class BaseO3CPU : public BaseCPU
85{
86    //Stuff that's pretty ISA independent will go here.
87  public:
88    BaseO3CPU(BaseCPUParams *params);
89
90    void regStats();
91};
92
93/**
94 * FullO3CPU class, has each of the stages (fetch through commit)
95 * within it, as well as all of the time buffers between stages.  The
96 * tick() function for the CPU is defined here.
97 */
98template <class Impl>
99class FullO3CPU : public BaseO3CPU
100{
101  public:
102    // Typedefs from the Impl here.
103    typedef typename Impl::CPUPol CPUPolicy;
104    typedef typename Impl::DynInstPtr DynInstPtr;
105    typedef typename Impl::O3CPU O3CPU;
106
107    using VecElem =  TheISA::VecElem;
108    using VecRegContainer =  TheISA::VecRegContainer;
109
110    using VecPredRegContainer = TheISA::VecPredRegContainer;
111
112    typedef O3ThreadState<Impl> ImplState;
113    typedef O3ThreadState<Impl> Thread;
114
115    typedef typename std::list<DynInstPtr>::iterator ListIt;
116
117    friend class O3ThreadContext<Impl>;
118
119  public:
120    enum Status {
121        Running,
122        Idle,
123        Halted,
124        Blocked,
125        SwitchedOut
126    };
127
128    BaseTLB *itb;
129    BaseTLB *dtb;
130    using LSQRequest = typename LSQ<Impl>::LSQRequest;
131
132    /** Overall CPU status. */
133    Status _status;
134
135  private:
136
137    /**
138     * IcachePort class for instruction fetch.
139     */
140    class IcachePort : public MasterPort
141    {
142      protected:
143        /** Pointer to fetch. */
144        DefaultFetch<Impl> *fetch;
145
146      public:
147        /** Default constructor. */
148        IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
149            : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
150        { }
151
152      protected:
153
154        /** Timing version of receive.  Handles setting fetch to the
155         * proper status to start fetching. */
156        virtual bool recvTimingResp(PacketPtr pkt);
157
158        /** Handles doing a retry of a failed fetch. */
159        virtual void recvReqRetry();
160    };
161
162    /**
163     * DcachePort class for the load/store queue.
164     */
165    class DcachePort : public MasterPort
166    {
167      protected:
168
169        /** Pointer to LSQ. */
170        LSQ<Impl> *lsq;
171        FullO3CPU<Impl> *cpu;
172
173      public:
174        /** Default constructor. */
175        DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
176            : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
177              cpu(_cpu)
178        { }
179
180      protected:
181
182        /** Timing version of receive.  Handles writing back and
183         * completing the load or store that has returned from
184         * memory. */
185        virtual bool recvTimingResp(PacketPtr pkt);
186        virtual void recvTimingSnoopReq(PacketPtr pkt);
187
188        virtual void recvFunctionalSnoop(PacketPtr pkt)
189        {
190            // @todo: Is there a need for potential invalidation here?
191        }
192
193        /** Handles doing a retry of the previous send. */
194        virtual void recvReqRetry();
195
196        /**
197         * As this CPU requires snooping to maintain the load store queue
198         * change the behaviour from the base CPU port.
199         *
200         * @return true since we have to snoop
201         */
202        virtual bool isSnooping() const { return true; }
203    };
204
205    /** The tick event used for scheduling CPU ticks. */
206    EventFunctionWrapper tickEvent;
207
208    /** Schedule tick event, regardless of its current state. */
209    void scheduleTickEvent(Cycles delay)
210    {
211        if (tickEvent.squashed())
212            reschedule(tickEvent, clockEdge(delay));
213        else if (!tickEvent.scheduled())
214            schedule(tickEvent, clockEdge(delay));
215    }
216
217    /** Unschedule tick event, regardless of its current state. */
218    void unscheduleTickEvent()
219    {
220        if (tickEvent.scheduled())
221            tickEvent.squash();
222    }
223
224    /**
225     * Check if the pipeline has drained and signal drain done.
226     *
227     * This method checks if a drain has been requested and if the CPU
228     * has drained successfully (i.e., there are no instructions in
229     * the pipeline). If the CPU has drained, it deschedules the tick
230     * event and signals the drain manager.
231     *
232     * @return False if a drain hasn't been requested or the CPU
233     * hasn't drained, true otherwise.
234     */
235    bool tryDrain();
236
237    /**
238     * Perform sanity checks after a drain.
239     *
240     * This method is called from drain() when it has determined that
241     * the CPU is fully drained when gem5 is compiled with the NDEBUG
242     * macro undefined. The intention of this method is to do more
243     * extensive tests than the isDrained() method to weed out any
244     * draining bugs.
245     */
246    void drainSanityCheck() const;
247
248    /** Check if a system is in a drained state. */
249    bool isDrained() const;
250
251  public:
252    /** Constructs a CPU with the given parameters. */
253    FullO3CPU(DerivO3CPUParams *params);
254    /** Destructor. */
255    ~FullO3CPU();
256
257    /** Registers statistics. */
258    void regStats() override;
259
260    ProbePointArg<PacketPtr> *ppInstAccessComplete;
261    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
262
263    /** Register probe points. */
264    void regProbePoints() override;
265
266    void demapPage(Addr vaddr, uint64_t asn)
267    {
268        this->itb->demapPage(vaddr, asn);
269        this->dtb->demapPage(vaddr, asn);
270    }
271
272    void demapInstPage(Addr vaddr, uint64_t asn)
273    {
274        this->itb->demapPage(vaddr, asn);
275    }
276
277    void demapDataPage(Addr vaddr, uint64_t asn)
278    {
279        this->dtb->demapPage(vaddr, asn);
280    }
281
282    /** Ticks CPU, calling tick() on each stage, and checking the overall
283     *  activity to see if the CPU should deschedule itself.
284     */
285    void tick();
286
287    /** Initialize the CPU */
288    void init() override;
289
290    void startup() override;
291
292    /** Returns the Number of Active Threads in the CPU */
293    int numActiveThreads()
294    { return activeThreads.size(); }
295
296    /** Add Thread to Active Threads List */
297    void activateThread(ThreadID tid);
298
299    /** Remove Thread from Active Threads List */
300    void deactivateThread(ThreadID tid);
301
302    /** Setup CPU to insert a thread's context */
303    void insertThread(ThreadID tid);
304
305    /** Remove all of a thread's context from CPU */
306    void removeThread(ThreadID tid);
307
308    /** Count the Total Instructions Committed in the CPU. */
309    Counter totalInsts() const override;
310
311    /** Count the Total Ops (including micro ops) committed in the CPU. */
312    Counter totalOps() const override;
313
314    /** Add Thread to Active Threads List. */
315    void activateContext(ThreadID tid) override;
316
317    /** Remove Thread from Active Threads List */
318    void suspendContext(ThreadID tid) override;
319
320    /** Remove Thread from Active Threads List &&
321     *  Remove Thread Context from CPU.
322     */
323    void haltContext(ThreadID tid) override;
324
325    /** Update The Order In Which We Process Threads. */
326    void updateThreadPriority();
327
328    /** Is the CPU draining? */
329    bool isDraining() const { return drainState() == DrainState::Draining; }
330
331    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
332    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
333
334  public:
335    /** Executes a syscall.
336     * @todo: Determine if this needs to be virtual.
337     */
338    void syscall(int64_t callnum, ThreadID tid, Fault *fault);
339
340    /** Starts draining the CPU's pipeline of all instructions in
341     * order to stop all memory accesses. */
342    DrainState drain() override;
343
344    /** Resumes execution after a drain. */
345    void drainResume() override;
346
347    /**
348     * Commit has reached a safe point to drain a thread.
349     *
350     * Commit calls this method to inform the pipeline that it has
351     * reached a point where it is not executed microcode and is about
352     * to squash uncommitted instructions to fully drain the pipeline.
353     */
354    void commitDrained(ThreadID tid);
355
356    /** Switches out this CPU. */
357    void switchOut() override;
358
359    /** Takes over from another CPU. */
360    void takeOverFrom(BaseCPU *oldCPU) override;
361
362    void verifyMemoryMode() const override;
363
364    /** Get the current instruction sequence number, and increment it. */
365    InstSeqNum getAndIncrementInstSeq()
366    { return globalSeqNum++; }
367
368    /** Traps to handle given fault. */
369    void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
370
371    /** HW return from error interrupt. */
372    Fault hwrei(ThreadID tid);
373
374    bool simPalCheck(int palFunc, ThreadID tid);
375
376    /** Check if a change in renaming is needed for vector registers.
377     * The vecMode variable is updated and propagated to rename maps.
378     *
379     * @param tid ThreadID
380     * @param freelist list of free registers
381     */
382    void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
383
384    /** Returns the Fault for any valid interrupt. */
385    Fault getInterrupts();
386
387    /** Processes any an interrupt fault. */
388    void processInterrupts(const Fault &interrupt);
389
390    /** Halts the CPU. */
391    void halt() { panic("Halt not implemented!\n"); }
392
393    /** Register accessors.  Index refers to the physical register index. */
394
395    /** Reads a miscellaneous register. */
396    RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
397
398    /** Reads a misc. register, including any side effects the read
399     * might have as defined by the architecture.
400     */
401    RegVal readMiscReg(int misc_reg, ThreadID tid);
402
403    /** Sets a miscellaneous register. */
404    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
405
406    /** Sets a misc. register, including any side effects the write
407     * might have as defined by the architecture.
408     */
409    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
410
411    RegVal readIntReg(PhysRegIdPtr phys_reg);
412
413    RegVal readFloatReg(PhysRegIdPtr phys_reg);
414
415    const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
416
417    /**
418     * Read physical vector register for modification.
419     */
420    VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
421
422    /** Returns current vector renaming mode */
423    Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
424
425    /** Sets the current vector renaming mode */
426    void vecRenameMode(Enums::VecRegRenameMode vec_mode)
427    { vecMode = vec_mode; }
428
429    /**
430     * Read physical vector register lane
431     */
432    template<typename VecElem, int LaneIdx>
433    VecLaneT<VecElem, true>
434    readVecLane(PhysRegIdPtr phys_reg) const
435    {
436        vecRegfileReads++;
437        return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
438    }
439
440    /**
441     * Read physical vector register lane
442     */
443    template<typename VecElem>
444    VecLaneT<VecElem, true>
445    readVecLane(PhysRegIdPtr phys_reg) const
446    {
447        vecRegfileReads++;
448        return regFile.readVecLane<VecElem>(phys_reg);
449    }
450
451    /** Write a lane of the destination vector register. */
452    template<typename LD>
453    void
454    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
455    {
456        vecRegfileWrites++;
457        return regFile.setVecLane(phys_reg, val);
458    }
459
460    const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
461
462    const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
463
464    VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
465
466    TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
467
468    void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
469
470    void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
471
472    void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
473
474    void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
475
476    void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
477
478    void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
479
480    RegVal readArchIntReg(int reg_idx, ThreadID tid);
481
482    RegVal readArchFloatReg(int reg_idx, ThreadID tid);
483
484    const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
485    /** Read architectural vector register for modification. */
486    VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
487
488    /** Read architectural vector register lane. */
489    template<typename VecElem>
490    VecLaneT<VecElem, true>
491    readArchVecLane(int reg_idx, int lId, ThreadID tid) const
492    {
493        PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
494                    RegId(VecRegClass, reg_idx));
495        return readVecLane<VecElem>(phys_reg);
496    }
497
498
499    /** Write a lane of the destination vector register. */
500    template<typename LD>
501    void
502    setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
503    {
504        PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
505                    RegId(VecRegClass, reg_idx));
506        setVecLane(phys_reg, val);
507    }
508
509    const VecElem& readArchVecElem(const RegIndex& reg_idx,
510                                   const ElemIndex& ldx, ThreadID tid) const;
511
512    const VecPredRegContainer& readArchVecPredReg(int reg_idx,
513                                                  ThreadID tid) const;
514
515    VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
516
517    TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
518
519    /** Architectural register accessors.  Looks up in the commit
520     * rename table to obtain the true physical index of the
521     * architected register first, then accesses that physical
522     * register.
523     */
524    void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
525
526    void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
527
528    void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
529                           ThreadID tid);
530
531    void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
532
533    void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
534                        const VecElem& val, ThreadID tid);
535
536    void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
537
538    /** Sets the commit PC state of a specific thread. */
539    void pcState(const TheISA::PCState &newPCState, ThreadID tid);
540
541    /** Reads the commit PC state of a specific thread. */
542    TheISA::PCState pcState(ThreadID tid);
543
544    /** Reads the commit PC of a specific thread. */
545    Addr instAddr(ThreadID tid);
546
547    /** Reads the commit micro PC of a specific thread. */
548    MicroPC microPC(ThreadID tid);
549
550    /** Reads the next PC of a specific thread. */
551    Addr nextInstAddr(ThreadID tid);
552
553    /** Initiates a squash of all in-flight instructions for a given
554     * thread.  The source of the squash is an external update of
555     * state through the TC.
556     */
557    void squashFromTC(ThreadID tid);
558
559    /** Function to add instruction onto the head of the list of the
560     *  instructions.  Used when new instructions are fetched.
561     */
562    ListIt addInst(const DynInstPtr &inst);
563
564    /** Function to tell the CPU that an instruction has completed. */
565    void instDone(ThreadID tid, const DynInstPtr &inst);
566
567    /** Remove an instruction from the front end of the list.  There's
568     *  no restriction on location of the instruction.
569     */
570    void removeFrontInst(const DynInstPtr &inst);
571
572    /** Remove all instructions that are not currently in the ROB.
573     *  There's also an option to not squash delay slot instructions.*/
574    void removeInstsNotInROB(ThreadID tid);
575
576    /** Remove all instructions younger than the given sequence number. */
577    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
578
579    /** Removes the instruction pointed to by the iterator. */
580    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
581
582    /** Cleans up all instructions on the remove list. */
583    void cleanUpRemovedInsts();
584
585    /** Debug function to print all instructions on the list. */
586    void dumpInsts();
587
588  public:
589#ifndef NDEBUG
590    /** Count of total number of dynamic instructions in flight. */
591    int instcount;
592#endif
593
594    /** List of all the instructions in flight. */
595    std::list<DynInstPtr> instList;
596
597    /** List of all the instructions that will be removed at the end of this
598     *  cycle.
599     */
600    std::queue<ListIt> removeList;
601
602#ifdef DEBUG
603    /** Debug structure to keep track of the sequence numbers still in
604     * flight.
605     */
606    std::set<InstSeqNum> snList;
607#endif
608
609    /** Records if instructions need to be removed this cycle due to
610     *  being retired or squashed.
611     */
612    bool removeInstsThisCycle;
613
614  protected:
615    /** The fetch stage. */
616    typename CPUPolicy::Fetch fetch;
617
618    /** The decode stage. */
619    typename CPUPolicy::Decode decode;
620
621    /** The dispatch stage. */
622    typename CPUPolicy::Rename rename;
623
624    /** The issue/execute/writeback stages. */
625    typename CPUPolicy::IEW iew;
626
627    /** The commit stage. */
628    typename CPUPolicy::Commit commit;
629
630    /** The rename mode of the vector registers */
631    Enums::VecRegRenameMode vecMode;
632
633    /** The register file. */
634    PhysRegFile regFile;
635
636    /** The free list. */
637    typename CPUPolicy::FreeList freeList;
638
639    /** The rename map. */
640    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
641
642    /** The commit rename map. */
643    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
644
645    /** The re-order buffer. */
646    typename CPUPolicy::ROB rob;
647
648    /** Active Threads List */
649    std::list<ThreadID> activeThreads;
650
651    /** Integer Register Scoreboard */
652    Scoreboard scoreboard;
653
654    std::vector<TheISA::ISA *> isa;
655
656    /** Instruction port. Note that it has to appear after the fetch stage. */
657    IcachePort icachePort;
658
659    /** Data port. Note that it has to appear after the iew stages */
660    DcachePort dcachePort;
661
662  public:
663    /** Enum to give each stage a specific index, so when calling
664     *  activateStage() or deactivateStage(), they can specify which stage
665     *  is being activated/deactivated.
666     */
667    enum StageIdx {
668        FetchIdx,
669        DecodeIdx,
670        RenameIdx,
671        IEWIdx,
672        CommitIdx,
673        NumStages };
674
675    /** Typedefs from the Impl to get the structs that each of the
676     *  time buffers should use.
677     */
678    typedef typename CPUPolicy::TimeStruct TimeStruct;
679
680    typedef typename CPUPolicy::FetchStruct FetchStruct;
681
682    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
683
684    typedef typename CPUPolicy::RenameStruct RenameStruct;
685
686    typedef typename CPUPolicy::IEWStruct IEWStruct;
687
688    /** The main time buffer to do backwards communication. */
689    TimeBuffer<TimeStruct> timeBuffer;
690
691    /** The fetch stage's instruction queue. */
692    TimeBuffer<FetchStruct> fetchQueue;
693
694    /** The decode stage's instruction queue. */
695    TimeBuffer<DecodeStruct> decodeQueue;
696
697    /** The rename stage's instruction queue. */
698    TimeBuffer<RenameStruct> renameQueue;
699
700    /** The IEW stage's instruction queue. */
701    TimeBuffer<IEWStruct> iewQueue;
702
703  private:
704    /** The activity recorder; used to tell if the CPU has any
705     * activity remaining or if it can go to idle and deschedule
706     * itself.
707     */
708    ActivityRecorder activityRec;
709
710  public:
711    /** Records that there was time buffer activity this cycle. */
712    void activityThisCycle() { activityRec.activity(); }
713
714    /** Changes a stage's status to active within the activity recorder. */
715    void activateStage(const StageIdx idx)
716    { activityRec.activateStage(idx); }
717
718    /** Changes a stage's status to inactive within the activity recorder. */
719    void deactivateStage(const StageIdx idx)
720    { activityRec.deactivateStage(idx); }
721
722    /** Wakes the CPU, rescheduling the CPU if it's not already active. */
723    void wakeCPU();
724
725    virtual void wakeup(ThreadID tid) override;
726
727    /** Gets a free thread id. Use if thread ids change across system. */
728    ThreadID getFreeTid();
729
730  public:
731    /** Returns a pointer to a thread context. */
732    ThreadContext *
733    tcBase(ThreadID tid)
734    {
735        return thread[tid]->getTC();
736    }
737
738    /** The global sequence number counter. */
739    InstSeqNum globalSeqNum;//[Impl::MaxThreads];
740
741    /** Pointer to the checker, which can dynamically verify
742     * instruction results at run time.  This can be set to NULL if it
743     * is not being used.
744     */
745    Checker<Impl> *checker;
746
747    /** Pointer to the system. */
748    System *system;
749
750    /** Pointers to all of the threads in the CPU. */
751    std::vector<Thread *> thread;
752
753    /** Threads Scheduled to Enter CPU */
754    std::list<int> cpuWaitList;
755
756    /** The cycle that the CPU was last running, used for statistics. */
757    Cycles lastRunningCycle;
758
759    /** The cycle that the CPU was last activated by a new thread*/
760    Tick lastActivatedCycle;
761
762    /** Mapping for system thread id to cpu id */
763    std::map<ThreadID, unsigned> threadMap;
764
765    /** Available thread ids in the cpu*/
766    std::vector<ThreadID> tids;
767
768    /** CPU pushRequest function, forwards request to LSQ. */
769    Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
770                      unsigned int size, Addr addr, Request::Flags flags,
771                      uint64_t *res)
772    {
773        return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
774                flags, res);
775    }
776
777    /** CPU read function, forwards read to LSQ. */
778    Fault read(LSQRequest* req, int load_idx)
779    {
780        return this->iew.ldstQueue.read(req, load_idx);
781    }
782
783    /** CPU write function, forwards write to LSQ. */
784    Fault write(LSQRequest* req, uint8_t *data, int store_idx)
785    {
786        return this->iew.ldstQueue.write(req, data, store_idx);
787    }
788
789    /** Used by the fetch unit to get a hold of the instruction port. */
790    MasterPort &getInstPort() override { return icachePort; }
791
792    /** Get the dcache port (used to find block size for translations). */
793    MasterPort &getDataPort() override { return dcachePort; }
794
795    /** Stat for total number of times the CPU is descheduled. */
796    Stats::Scalar timesIdled;
797    /** Stat for total number of cycles the CPU spends descheduled. */
798    Stats::Scalar idleCycles;
799    /** Stat for total number of cycles the CPU spends descheduled due to a
800     * quiesce operation or waiting for an interrupt. */
801    Stats::Scalar quiesceCycles;
802    /** Stat for the number of committed instructions per thread. */
803    Stats::Vector committedInsts;
804    /** Stat for the number of committed ops (including micro ops) per thread. */
805    Stats::Vector committedOps;
806    /** Stat for the CPI per thread. */
807    Stats::Formula cpi;
808    /** Stat for the total CPI. */
809    Stats::Formula totalCpi;
810    /** Stat for the IPC per thread. */
811    Stats::Formula ipc;
812    /** Stat for the total IPC. */
813    Stats::Formula totalIpc;
814
815    //number of integer register file accesses
816    Stats::Scalar intRegfileReads;
817    Stats::Scalar intRegfileWrites;
818    //number of float register file accesses
819    Stats::Scalar fpRegfileReads;
820    Stats::Scalar fpRegfileWrites;
821    //number of vector register file accesses
822    mutable Stats::Scalar vecRegfileReads;
823    Stats::Scalar vecRegfileWrites;
824    //number of predicate register file accesses
825    mutable Stats::Scalar vecPredRegfileReads;
826    Stats::Scalar vecPredRegfileWrites;
827    //number of CC register file accesses
828    Stats::Scalar ccRegfileReads;
829    Stats::Scalar ccRegfileWrites;
830    //number of misc
831    Stats::Scalar miscRegfileReads;
832    Stats::Scalar miscRegfileWrites;
833};
834
835#endif // __CPU_O3_CPU_HH__
836