cpu.hh revision 11151:ca4ea9b5c052
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2005 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Korey Sewell
44 *          Rick Strong
45 */
46
47#ifndef __CPU_O3_CPU_HH__
48#define __CPU_O3_CPU_HH__
49
50#include <iostream>
51#include <list>
52#include <queue>
53#include <set>
54#include <vector>
55
56#include "arch/types.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "cpu/o3/comm.hh"
60#include "cpu/o3/cpu_policy.hh"
61#include "cpu/o3/scoreboard.hh"
62#include "cpu/o3/thread_state.hh"
63#include "cpu/activity.hh"
64#include "cpu/base.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/timebuf.hh"
67//#include "cpu/o3/thread_context.hh"
68#include "params/DerivO3CPU.hh"
69#include "sim/process.hh"
70
71template <class>
72class Checker;
73class ThreadContext;
74template <class>
75class O3ThreadContext;
76
77class Checkpoint;
78class MemObject;
79class Process;
80
81struct BaseCPUParams;
82
83class BaseO3CPU : public BaseCPU
84{
85    //Stuff that's pretty ISA independent will go here.
86  public:
87    BaseO3CPU(BaseCPUParams *params);
88
89    void regStats();
90};
91
92/**
93 * FullO3CPU class, has each of the stages (fetch through commit)
94 * within it, as well as all of the time buffers between stages.  The
95 * tick() function for the CPU is defined here.
96 */
97template <class Impl>
98class FullO3CPU : public BaseO3CPU
99{
100  public:
101    // Typedefs from the Impl here.
102    typedef typename Impl::CPUPol CPUPolicy;
103    typedef typename Impl::DynInstPtr DynInstPtr;
104    typedef typename Impl::O3CPU O3CPU;
105
106    typedef O3ThreadState<Impl> ImplState;
107    typedef O3ThreadState<Impl> Thread;
108
109    typedef typename std::list<DynInstPtr>::iterator ListIt;
110
111    friend class O3ThreadContext<Impl>;
112
113  public:
114    enum Status {
115        Running,
116        Idle,
117        Halted,
118        Blocked,
119        SwitchedOut
120    };
121
122    TheISA::TLB * itb;
123    TheISA::TLB * dtb;
124
125    /** Overall CPU status. */
126    Status _status;
127
128  private:
129
130    /**
131     * IcachePort class for instruction fetch.
132     */
133    class IcachePort : public MasterPort
134    {
135      protected:
136        /** Pointer to fetch. */
137        DefaultFetch<Impl> *fetch;
138
139      public:
140        /** Default constructor. */
141        IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
142            : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
143        { }
144
145      protected:
146
147        /** Timing version of receive.  Handles setting fetch to the
148         * proper status to start fetching. */
149        virtual bool recvTimingResp(PacketPtr pkt);
150        virtual void recvTimingSnoopReq(PacketPtr pkt) { }
151
152        /** Handles doing a retry of a failed fetch. */
153        virtual void recvReqRetry();
154    };
155
156    /**
157     * DcachePort class for the load/store queue.
158     */
159    class DcachePort : public MasterPort
160    {
161      protected:
162
163        /** Pointer to LSQ. */
164        LSQ<Impl> *lsq;
165        FullO3CPU<Impl> *cpu;
166
167      public:
168        /** Default constructor. */
169        DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
170            : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
171              cpu(_cpu)
172        { }
173
174      protected:
175
176        /** Timing version of receive.  Handles writing back and
177         * completing the load or store that has returned from
178         * memory. */
179        virtual bool recvTimingResp(PacketPtr pkt);
180        virtual void recvTimingSnoopReq(PacketPtr pkt);
181
182        virtual void recvFunctionalSnoop(PacketPtr pkt)
183        {
184            // @todo: Is there a need for potential invalidation here?
185        }
186
187        /** Handles doing a retry of the previous send. */
188        virtual void recvReqRetry();
189
190        /**
191         * As this CPU requires snooping to maintain the load store queue
192         * change the behaviour from the base CPU port.
193         *
194         * @return true since we have to snoop
195         */
196        virtual bool isSnooping() const { return true; }
197    };
198
199    class TickEvent : public Event
200    {
201      private:
202        /** Pointer to the CPU. */
203        FullO3CPU<Impl> *cpu;
204
205      public:
206        /** Constructs a tick event. */
207        TickEvent(FullO3CPU<Impl> *c);
208
209        /** Processes a tick event, calling tick() on the CPU. */
210        void process();
211        /** Returns the description of the tick event. */
212        const char *description() const;
213    };
214
215    /** The tick event used for scheduling CPU ticks. */
216    TickEvent tickEvent;
217
218    /** Schedule tick event, regardless of its current state. */
219    void scheduleTickEvent(Cycles delay)
220    {
221        if (tickEvent.squashed())
222            reschedule(tickEvent, clockEdge(delay));
223        else if (!tickEvent.scheduled())
224            schedule(tickEvent, clockEdge(delay));
225    }
226
227    /** Unschedule tick event, regardless of its current state. */
228    void unscheduleTickEvent()
229    {
230        if (tickEvent.scheduled())
231            tickEvent.squash();
232    }
233
234    /**
235     * Check if the pipeline has drained and signal drain done.
236     *
237     * This method checks if a drain has been requested and if the CPU
238     * has drained successfully (i.e., there are no instructions in
239     * the pipeline). If the CPU has drained, it deschedules the tick
240     * event and signals the drain manager.
241     *
242     * @return False if a drain hasn't been requested or the CPU
243     * hasn't drained, true otherwise.
244     */
245    bool tryDrain();
246
247    /**
248     * Perform sanity checks after a drain.
249     *
250     * This method is called from drain() when it has determined that
251     * the CPU is fully drained when gem5 is compiled with the NDEBUG
252     * macro undefined. The intention of this method is to do more
253     * extensive tests than the isDrained() method to weed out any
254     * draining bugs.
255     */
256    void drainSanityCheck() const;
257
258    /** Check if a system is in a drained state. */
259    bool isDrained() const;
260
261  public:
262    /** Constructs a CPU with the given parameters. */
263    FullO3CPU(DerivO3CPUParams *params);
264    /** Destructor. */
265    ~FullO3CPU();
266
267    /** Registers statistics. */
268    void regStats();
269
270    ProbePointArg<PacketPtr> *ppInstAccessComplete;
271    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
272
273    /** Register probe points. */
274    void regProbePoints();
275
276    void demapPage(Addr vaddr, uint64_t asn)
277    {
278        this->itb->demapPage(vaddr, asn);
279        this->dtb->demapPage(vaddr, asn);
280    }
281
282    void demapInstPage(Addr vaddr, uint64_t asn)
283    {
284        this->itb->demapPage(vaddr, asn);
285    }
286
287    void demapDataPage(Addr vaddr, uint64_t asn)
288    {
289        this->dtb->demapPage(vaddr, asn);
290    }
291
292    /** Ticks CPU, calling tick() on each stage, and checking the overall
293     *  activity to see if the CPU should deschedule itself.
294     */
295    void tick();
296
297    /** Initialize the CPU */
298    void init();
299
300    void startup();
301
302    /** Returns the Number of Active Threads in the CPU */
303    int numActiveThreads()
304    { return activeThreads.size(); }
305
306    /** Add Thread to Active Threads List */
307    void activateThread(ThreadID tid);
308
309    /** Remove Thread from Active Threads List */
310    void deactivateThread(ThreadID tid);
311
312    /** Setup CPU to insert a thread's context */
313    void insertThread(ThreadID tid);
314
315    /** Remove all of a thread's context from CPU */
316    void removeThread(ThreadID tid);
317
318    /** Count the Total Instructions Committed in the CPU. */
319    virtual Counter totalInsts() const;
320
321    /** Count the Total Ops (including micro ops) committed in the CPU. */
322    virtual Counter totalOps() const;
323
324    /** Add Thread to Active Threads List. */
325    void activateContext(ThreadID tid);
326
327    /** Remove Thread from Active Threads List */
328    void suspendContext(ThreadID tid);
329
330    /** Remove Thread from Active Threads List &&
331     *  Remove Thread Context from CPU.
332     */
333    void haltContext(ThreadID tid);
334
335    /** Update The Order In Which We Process Threads. */
336    void updateThreadPriority();
337
338    /** Is the CPU draining? */
339    bool isDraining() const { return drainState() == DrainState::Draining; }
340
341    void serializeThread(CheckpointOut &cp,
342                         ThreadID tid) const M5_ATTR_OVERRIDE;
343    void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
344
345  public:
346    /** Executes a syscall.
347     * @todo: Determine if this needs to be virtual.
348     */
349    void syscall(int64_t callnum, ThreadID tid);
350
351    /** Starts draining the CPU's pipeline of all instructions in
352     * order to stop all memory accesses. */
353    DrainState drain() M5_ATTR_OVERRIDE;
354
355    /** Resumes execution after a drain. */
356    void drainResume() M5_ATTR_OVERRIDE;
357
358    /**
359     * Commit has reached a safe point to drain a thread.
360     *
361     * Commit calls this method to inform the pipeline that it has
362     * reached a point where it is not executed microcode and is about
363     * to squash uncommitted instructions to fully drain the pipeline.
364     */
365    void commitDrained(ThreadID tid);
366
367    /** Switches out this CPU. */
368    virtual void switchOut();
369
370    /** Takes over from another CPU. */
371    virtual void takeOverFrom(BaseCPU *oldCPU);
372
373    void verifyMemoryMode() const;
374
375    /** Get the current instruction sequence number, and increment it. */
376    InstSeqNum getAndIncrementInstSeq()
377    { return globalSeqNum++; }
378
379    /** Traps to handle given fault. */
380    void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
381
382    /** HW return from error interrupt. */
383    Fault hwrei(ThreadID tid);
384
385    bool simPalCheck(int palFunc, ThreadID tid);
386
387    /** Returns the Fault for any valid interrupt. */
388    Fault getInterrupts();
389
390    /** Processes any an interrupt fault. */
391    void processInterrupts(const Fault &interrupt);
392
393    /** Halts the CPU. */
394    void halt() { panic("Halt not implemented!\n"); }
395
396    /** Check if this address is a valid instruction address. */
397    bool validInstAddr(Addr addr) { return true; }
398
399    /** Check if this address is a valid data address. */
400    bool validDataAddr(Addr addr) { return true; }
401
402    /** Register accessors.  Index refers to the physical register index. */
403
404    /** Reads a miscellaneous register. */
405    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
406
407    /** Reads a misc. register, including any side effects the read
408     * might have as defined by the architecture.
409     */
410    TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
411
412    /** Sets a miscellaneous register. */
413    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
414            ThreadID tid);
415
416    /** Sets a misc. register, including any side effects the write
417     * might have as defined by the architecture.
418     */
419    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
420            ThreadID tid);
421
422    uint64_t readIntReg(int reg_idx);
423
424    TheISA::FloatReg readFloatReg(int reg_idx);
425
426    TheISA::FloatRegBits readFloatRegBits(int reg_idx);
427
428    TheISA::CCReg readCCReg(int reg_idx);
429
430    void setIntReg(int reg_idx, uint64_t val);
431
432    void setFloatReg(int reg_idx, TheISA::FloatReg val);
433
434    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
435
436    void setCCReg(int reg_idx, TheISA::CCReg val);
437
438    uint64_t readArchIntReg(int reg_idx, ThreadID tid);
439
440    float readArchFloatReg(int reg_idx, ThreadID tid);
441
442    uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
443
444    TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
445
446    /** Architectural register accessors.  Looks up in the commit
447     * rename table to obtain the true physical index of the
448     * architected register first, then accesses that physical
449     * register.
450     */
451    void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
452
453    void setArchFloatReg(int reg_idx, float val, ThreadID tid);
454
455    void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
456
457    void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
458
459    /** Sets the commit PC state of a specific thread. */
460    void pcState(const TheISA::PCState &newPCState, ThreadID tid);
461
462    /** Reads the commit PC state of a specific thread. */
463    TheISA::PCState pcState(ThreadID tid);
464
465    /** Reads the commit PC of a specific thread. */
466    Addr instAddr(ThreadID tid);
467
468    /** Reads the commit micro PC of a specific thread. */
469    MicroPC microPC(ThreadID tid);
470
471    /** Reads the next PC of a specific thread. */
472    Addr nextInstAddr(ThreadID tid);
473
474    /** Initiates a squash of all in-flight instructions for a given
475     * thread.  The source of the squash is an external update of
476     * state through the TC.
477     */
478    void squashFromTC(ThreadID tid);
479
480    /** Function to add instruction onto the head of the list of the
481     *  instructions.  Used when new instructions are fetched.
482     */
483    ListIt addInst(DynInstPtr &inst);
484
485    /** Function to tell the CPU that an instruction has completed. */
486    void instDone(ThreadID tid, DynInstPtr &inst);
487
488    /** Remove an instruction from the front end of the list.  There's
489     *  no restriction on location of the instruction.
490     */
491    void removeFrontInst(DynInstPtr &inst);
492
493    /** Remove all instructions that are not currently in the ROB.
494     *  There's also an option to not squash delay slot instructions.*/
495    void removeInstsNotInROB(ThreadID tid);
496
497    /** Remove all instructions younger than the given sequence number. */
498    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
499
500    /** Removes the instruction pointed to by the iterator. */
501    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
502
503    /** Cleans up all instructions on the remove list. */
504    void cleanUpRemovedInsts();
505
506    /** Debug function to print all instructions on the list. */
507    void dumpInsts();
508
509  public:
510#ifndef NDEBUG
511    /** Count of total number of dynamic instructions in flight. */
512    int instcount;
513#endif
514
515    /** List of all the instructions in flight. */
516    std::list<DynInstPtr> instList;
517
518    /** List of all the instructions that will be removed at the end of this
519     *  cycle.
520     */
521    std::queue<ListIt> removeList;
522
523#ifdef DEBUG
524    /** Debug structure to keep track of the sequence numbers still in
525     * flight.
526     */
527    std::set<InstSeqNum> snList;
528#endif
529
530    /** Records if instructions need to be removed this cycle due to
531     *  being retired or squashed.
532     */
533    bool removeInstsThisCycle;
534
535  protected:
536    /** The fetch stage. */
537    typename CPUPolicy::Fetch fetch;
538
539    /** The decode stage. */
540    typename CPUPolicy::Decode decode;
541
542    /** The dispatch stage. */
543    typename CPUPolicy::Rename rename;
544
545    /** The issue/execute/writeback stages. */
546    typename CPUPolicy::IEW iew;
547
548    /** The commit stage. */
549    typename CPUPolicy::Commit commit;
550
551    /** The register file. */
552    PhysRegFile regFile;
553
554    /** The free list. */
555    typename CPUPolicy::FreeList freeList;
556
557    /** The rename map. */
558    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
559
560    /** The commit rename map. */
561    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
562
563    /** The re-order buffer. */
564    typename CPUPolicy::ROB rob;
565
566    /** Active Threads List */
567    std::list<ThreadID> activeThreads;
568
569    /** Integer Register Scoreboard */
570    Scoreboard scoreboard;
571
572    std::vector<TheISA::ISA *> isa;
573
574    /** Instruction port. Note that it has to appear after the fetch stage. */
575    IcachePort icachePort;
576
577    /** Data port. Note that it has to appear after the iew stages */
578    DcachePort dcachePort;
579
580  public:
581    /** Enum to give each stage a specific index, so when calling
582     *  activateStage() or deactivateStage(), they can specify which stage
583     *  is being activated/deactivated.
584     */
585    enum StageIdx {
586        FetchIdx,
587        DecodeIdx,
588        RenameIdx,
589        IEWIdx,
590        CommitIdx,
591        NumStages };
592
593    /** Typedefs from the Impl to get the structs that each of the
594     *  time buffers should use.
595     */
596    typedef typename CPUPolicy::TimeStruct TimeStruct;
597
598    typedef typename CPUPolicy::FetchStruct FetchStruct;
599
600    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
601
602    typedef typename CPUPolicy::RenameStruct RenameStruct;
603
604    typedef typename CPUPolicy::IEWStruct IEWStruct;
605
606    /** The main time buffer to do backwards communication. */
607    TimeBuffer<TimeStruct> timeBuffer;
608
609    /** The fetch stage's instruction queue. */
610    TimeBuffer<FetchStruct> fetchQueue;
611
612    /** The decode stage's instruction queue. */
613    TimeBuffer<DecodeStruct> decodeQueue;
614
615    /** The rename stage's instruction queue. */
616    TimeBuffer<RenameStruct> renameQueue;
617
618    /** The IEW stage's instruction queue. */
619    TimeBuffer<IEWStruct> iewQueue;
620
621  private:
622    /** The activity recorder; used to tell if the CPU has any
623     * activity remaining or if it can go to idle and deschedule
624     * itself.
625     */
626    ActivityRecorder activityRec;
627
628  public:
629    /** Records that there was time buffer activity this cycle. */
630    void activityThisCycle() { activityRec.activity(); }
631
632    /** Changes a stage's status to active within the activity recorder. */
633    void activateStage(const StageIdx idx)
634    { activityRec.activateStage(idx); }
635
636    /** Changes a stage's status to inactive within the activity recorder. */
637    void deactivateStage(const StageIdx idx)
638    { activityRec.deactivateStage(idx); }
639
640    /** Wakes the CPU, rescheduling the CPU if it's not already active. */
641    void wakeCPU();
642
643    virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
644
645    /** Gets a free thread id. Use if thread ids change across system. */
646    ThreadID getFreeTid();
647
648  public:
649    /** Returns a pointer to a thread context. */
650    ThreadContext *
651    tcBase(ThreadID tid)
652    {
653        return thread[tid]->getTC();
654    }
655
656    /** The global sequence number counter. */
657    InstSeqNum globalSeqNum;//[Impl::MaxThreads];
658
659    /** Pointer to the checker, which can dynamically verify
660     * instruction results at run time.  This can be set to NULL if it
661     * is not being used.
662     */
663    Checker<Impl> *checker;
664
665    /** Pointer to the system. */
666    System *system;
667
668    /** Pointers to all of the threads in the CPU. */
669    std::vector<Thread *> thread;
670
671    /** Threads Scheduled to Enter CPU */
672    std::list<int> cpuWaitList;
673
674    /** The cycle that the CPU was last running, used for statistics. */
675    Cycles lastRunningCycle;
676
677    /** The cycle that the CPU was last activated by a new thread*/
678    Tick lastActivatedCycle;
679
680    /** Mapping for system thread id to cpu id */
681    std::map<ThreadID, unsigned> threadMap;
682
683    /** Available thread ids in the cpu*/
684    std::vector<ThreadID> tids;
685
686    /** CPU read function, forwards read to LSQ. */
687    Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
688               uint8_t *data, int load_idx)
689    {
690        return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
691                                        data, load_idx);
692    }
693
694    /** CPU write function, forwards write to LSQ. */
695    Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
696                uint8_t *data, int store_idx)
697    {
698        return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
699                                         data, store_idx);
700    }
701
702    /** Used by the fetch unit to get a hold of the instruction port. */
703    virtual MasterPort &getInstPort() { return icachePort; }
704
705    /** Get the dcache port (used to find block size for translations). */
706    virtual MasterPort &getDataPort() { return dcachePort; }
707
708    /** Stat for total number of times the CPU is descheduled. */
709    Stats::Scalar timesIdled;
710    /** Stat for total number of cycles the CPU spends descheduled. */
711    Stats::Scalar idleCycles;
712    /** Stat for total number of cycles the CPU spends descheduled due to a
713     * quiesce operation or waiting for an interrupt. */
714    Stats::Scalar quiesceCycles;
715    /** Stat for the number of committed instructions per thread. */
716    Stats::Vector committedInsts;
717    /** Stat for the number of committed ops (including micro ops) per thread. */
718    Stats::Vector committedOps;
719    /** Stat for the CPI per thread. */
720    Stats::Formula cpi;
721    /** Stat for the total CPI. */
722    Stats::Formula totalCpi;
723    /** Stat for the IPC per thread. */
724    Stats::Formula ipc;
725    /** Stat for the total IPC. */
726    Stats::Formula totalIpc;
727
728    //number of integer register file accesses
729    Stats::Scalar intRegfileReads;
730    Stats::Scalar intRegfileWrites;
731    //number of float register file accesses
732    Stats::Scalar fpRegfileReads;
733    Stats::Scalar fpRegfileWrites;
734    //number of CC register file accesses
735    Stats::Scalar ccRegfileReads;
736    Stats::Scalar ccRegfileWrites;
737    //number of misc
738    Stats::Scalar miscRegfileReads;
739    Stats::Scalar miscRegfileWrites;
740};
741
742#endif // __CPU_O3_CPU_HH__
743